\n

SCS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

NVIC_IPRN


NVIC_IPRN

IRQ0 ~ IRQ31 Interrupt Priority Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPRN NVIC_IPRN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_4n_0 PRI_4n_1 PRI_4n_2 PRI_4n_3

PRI_4n_0 : Priority of IRQ_4n+0 0 denotes the highest priority and 15 denotes the lowest priority
bits : 4 - 7 (4 bit)
access : read-write

PRI_4n_1 : Priority of IRQ_4n+1 0 denotes the highest priority and 15 denotes the lowest priority
bits : 12 - 15 (4 bit)
access : read-write

PRI_4n_2 : Priority of IRQ_4n+2 0 denotes the highest priority and 15 denotes the lowest priority
bits : 20 - 23 (4 bit)
access : read-write

PRI_4n_3 : Priority of IRQ_4n+3 0 denotes the highest priority and 15 denotes the lowest priority
bits : 28 - 31 (4 bit)
access : read-write



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