Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTEN : Crystal (Power Down) Control\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Crystal off (Power down)
#1 : 1
Crystal on (Normal operation)
End of enumeration elements list.
HXTCTL : Power-down Mode Wake-up Pre-divider Counter Enable Control
The HXT pre-divider controls wake-up time from Power-down mode. The chip will delay (PDWKPSC*256) cycles to wait until the HXT is stable after the reset signal.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDWKPSC counter Disabled
#1 : 1
PDWKPSC counter Enabled
End of enumeration elements list.
PDWKIF : Power-down Mode Wake-up Interrupt Flag
Set by power down wake-up event indicates that resume from Power-down mode
The flag is set if the GPIO, USBH, USBD, UART, TIMER, WDT, RTC or I2C wake-up occurred.
Note1: Write 1 to clear the bit to zero.
Note2: This bit works only if PDWKIEN (CLK_PWRCTL[24]) set to 1
bits : 2 - 2 (1 bit)
access : read-write
PDWKIEN : Power-down Mode Wake-up Interrupt Enable Control\nNote: The interrupt will occur when both PDWKIF and PDWKIEN are set
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power-down Mode Wake-up Interrupt Disabled
#1 : 1
Power-down Mode Wake-up Interrupt Enabled
End of enumeration elements list.
PDWKPSC : PDWKPSC Counter\nAssuming the HXT is stable after the PDWKPSC x 256 HXT cycles, Clock controller would not output clock to system before the counter reaches (PDWKPSC x 256).
bits : 8 - 23 (16 bit)
access : read-write
PDWTCPU : Control Power-down Entry Condition\n
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip enters Power-down mode when the HXTEN bit is set to 1
#1 : 1
Chip enters Power-down mode when the both PDWTCPU and HXTEN bits are set to 1 and CPU run WFI instruction
End of enumeration elements list.
Clock Divider Number Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKDIV : Defines the Clock Divider Number for SYS_CLK\nThe actual clock divider number is (HCLKDIV+1). So,\n
bits : 0 - 3 (4 bit)
access : read-write
HCLKSEL : System Source Clock Select (SYS_SrcCLK)\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
System Clock source from HXT
#1 : 1
System Clock source from PLL_FOUT
End of enumeration elements list.
PCLKDIV : Defines the Clock Divider Number for APB_CLK\nThe actual clock divider number is (PCLKDIV+1). So,\n
bits : 8 - 11 (4 bit)
access : read-write
USBDDIV : Defines the Clock Divider Number for USB Device\nThe actual clock divider number is (USBDDIV+1). So,\n
bits : 16 - 20 (5 bit)
access : read-write
USBDSEL : USB Device Source Clock Select (USBD_SrcCLK)\n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB Device Clock source from HXT
#1 : 1
USB Device Clock source from PLL_FOUT
End of enumeration elements list.
USBHDIV : Defines the Clock Divider Number for USB Host\nThe actual clock divider number is (USBHDIV+1). So,\n
bits : 24 - 27 (4 bit)
access : read-write
Clock Divider Number Control Register 1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCDIV : Defines the Clock Divider Number for ADC\nThe actual clock divider number is (ADCDIV+1). So,\n
bits : 0 - 7 (8 bit)
access : read-write
STICKDIV : Defines the Clock Divider Number for SYS_TICK\nThe actual clock divider number is (STICKDIV+1). So,\n
bits : 8 - 15 (8 bit)
access : read-write
SDHDIV : Defines the Clock Divider Number for SDH\nThe actual clock divider number is (SDHDIV+1). So,\n
bits : 16 - 26 (11 bit)
access : read-write
ADCSEL : ADC Clock Select (ADC_SrcCLK)\n
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC Clock source from HXT
#1 : 1
ADC Clock source from PLL_FOUT
End of enumeration elements list.
SDHSEL : SDH Clock Select (SDH_SrcCLK)\n
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
SDH Clock source from HXT
#1 : 1
SDH Clock source from PLL_FOUT
End of enumeration elements list.
Clock Divider Number Control Register 2
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2SDIV : Defines the Clock Divider Number for I2S\nThe actual clock divider number is (I2SDIV+1). So,\n
bits : 0 - 7 (8 bit)
access : read-write
I2SSEL : I2S Clock Select (I2S_SrcCLK)\n
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
I2S Clock source from HXT
#01 : 1
I2S Clock source from PLL_FOUT
#10 : 2
Reserved
#11 : 3
I2S Clock source from APLL_FOUT
End of enumeration elements list.
SPI0SEL : SPI0 Engine Clock Select (SPI0SEL)\n
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0 Engine Clock source from HXT
#1 : 1
SPI0 Engine Clock source from PLL_FOUT
End of enumeration elements list.
SPI1SEL : SPI1 Engine Clock Select (SPI1SEL)\n
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI1 Engine Clock source from HXT
#1 : 1
SPI1 Engine Clock source from PLL_FOUT
End of enumeration elements list.
Clock Divider Number Control Register 3
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART0DIV : Defines the Clock Divider Number for UART0\nThe actual clock divider number is (UART0DIV +1). So,\n
bits : 0 - 3 (4 bit)
access : read-write
UART0SEL : UART0 Source Clock Select (UART0_SrcCLK)\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 Source Clock source from HXT
#1 : 1
UART0 Source Clock source from PLL_FOUT
End of enumeration elements list.
UART1DIV : Defines the Clock Divider Number for UART1\nThe actual clock divider number is (UART1DIV +1). So,\n
bits : 8 - 11 (4 bit)
access : read-write
UART1SEL : UART1 Source Clock Select (UART1_SrcCLK)\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 Source Clock source from HXT
#1 : 1
UART1 Source Clock source from PLL_FOUT
End of enumeration elements list.
UART2DIV : Defines the Clock Divider Number for UART2\nThe actual clock divider number is (UART2DIV +1). So,\n
bits : 16 - 19 (4 bit)
access : read-write
UART2SEL : UART2 Source Clock Select (UART2_SrcCLK)\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART2 Source Clock source from HXT
#1 : 1
UART2 Source Clock source from PLL_FOUT
End of enumeration elements list.
PLL Control Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBDIV : Feedback Divider Control (N)\nSet the feedback divider factor from 1 to 128
bits : 0 - 6 (7 bit)
access : read-write
INDIV : Reference Input Divider (M)\nSet the input reference clock divider factor from 1 to 64.
bits : 7 - 12 (6 bit)
access : read-write
OUTDIV : Output Divider Control (P) \nSet the output divider factor from 1 to 8.
bits : 13 - 15 (3 bit)
access : read-write
BP : PLL Bypass Control\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL at Normal mode
#1 : 1
Bypass Fin (i.e. Fout = XIN)
End of enumeration elements list.
PD : Power-down Mode\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL in Normal mode
#1 : 1
PLL in Power-down mode (Default)
End of enumeration elements list.
APLL Control Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDIV : Reference Input Divider Control \nSet the reference divider factor from 1 to 64. \n
bits : 0 - 5 (6 bit)
access : read-write
FBDIV : Feedback Divider Control \nSet the Feedback divider factor from 1 to 128. \n
bits : 6 - 12 (7 bit)
access : read-write
OUTDIV : Output Divider Control \nSet the Output divider factor from 1 to 8. \n
bits : 13 - 15 (3 bit)
access : read-write
PD : Power Down Enable Control\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power down Disabled
#1 : 1
Power down Enabled
End of enumeration elements list.
MODE : Mode Select \n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Integer mode
#1 : 1
Fraction mode
End of enumeration elements list.
FRAC : Sigma-delta Modulator Control Pins \nSet the fractional number of the Feedback divider.
bits : 20 - 31 (12 bit)
access : read-write
Clock Divider Number Control Register 4
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMR0DIV : Defines the Clock Divider Number for TMR0\nThe actual clock divider number is (TMR0DIV+1). So,\n
bits : 0 - 7 (8 bit)
access : read-write
TMR1DIV : Defines the Clock Divider Number for TMR1\nThe actual clock divider number is (TMR1DIV+1). So,\n
bits : 8 - 15 (8 bit)
access : read-write
TMR2DIV : Defines the Clock Divider Number for TMR2\nThe actual clock divider number is (TMR2DIV+1). So,\n
bits : 16 - 23 (8 bit)
access : read-write
TMR0SEL : Timer0 Engine Clock Select (TMR0_SrcCLK)\n
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 Engine Clock source from RTC_CLK
#1 : 1
Timer0 Engine Clock source from HXT
End of enumeration elements list.
TMR1SEL : Timer1 Engine Clock Select (TMR1_SrcCLK)\n
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 Engine Clock source from RTC_CLK
#1 : 1
Timer1 Engine Clock source from HXT
End of enumeration elements list.
TMR2SEL : Timer2 Engine Clock Select (TMR2_SrcCLK)\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 Engine Clock source from RTC_CLK
#1 : 1
Timer2 Engine Clock source from HXT
End of enumeration elements list.
Clock Divider Number Control Register 5
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMR3DIV : Define the Clock Divider Number for TMR3\nThe actual clock divider number is (TM3DIV+1). So,\n
bits : 0 - 7 (8 bit)
access : read-write
WDTDIV : Define the Clock Divider Number for WDT\nThe actual clock divider number is (WDTDIV+1). So,\n
bits : 8 - 15 (8 bit)
access : read-write
PWMDIV : Define the Clock Divider Number for PWM\nThe actual clock divider number is (PWMDIV+1). So,\n
bits : 16 - 23 (8 bit)
access : read-write
TMR3SEL : Timer3 Engine Clock Select (TMR3_SrcCLK)\n
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer3 Engine Clock source from RTC_CLK
#1 : 1
Timer3 Engine Clock source from HXT
End of enumeration elements list.
WDTSEL : WDT Engine Clock Select (WDT_SrcCLK)\n
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDT Engine Clock source from RTC_CLK
#1 : 1
WDT Engine Clock source from HXT
End of enumeration elements list.
PWMSEL : PWM Engine Clock Select (PWM_SrcCLK)\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Engine Clock source from HXT
#1 : 1
PWM Engine Clock source from PLL_FOUT
End of enumeration elements list.
AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM01CKEN : SRAM#1 Clock Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SRAM#1 Clock Disabled
#1 : 1
SRAM#1 Clock Enabled
End of enumeration elements list.
SRAM23CKEN : SRAM#2 Clock Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
SRAM#2 Clock Disabled
#1 : 1
SRAM#2 Clock Enabled
End of enumeration elements list.
ROMCKEN : ROM Clock Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
ROM Clock Disabled
#1 : 1
ROM Clock Enabled
End of enumeration elements list.
SPIMCKEN : SPIM Clock Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPIM Clock Disabled
#1 : 1
SPIM Clock Enabled
End of enumeration elements list.
SDHCKEN : SDH Clock Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
SDH Clock Disabled
#1 : 1
SDH Clock Enabled
End of enumeration elements list.
USBDCKEN : USB Device Clock Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB Device Clock Disabled
#1 : 1
USB Device Clock Enabled
End of enumeration elements list.
USBHCKEN : USB Host Clock Enable Control\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB Host Clock Disabled
#1 : 1
USB Host Clock Enabled
End of enumeration elements list.
APB Devices Clock Enable Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMR0CKEN : TIMER0 Clock Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
TIMER0 Clock Disabled
#1 : 1
TIMER0 Clock Enabled
End of enumeration elements list.
TMR1CKEN : TIMER1 Clock Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
TIMER1 Clock Disabled
#1 : 1
TIMER1 Clock Enabled
End of enumeration elements list.
TMR2CKEN : TIMER2 Clock Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
TIMER2 Clock Disabled
#1 : 1
TIMER2 Clock Enabled
End of enumeration elements list.
TMR3CKEN : TIMER3 Clock Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
TIMER3 Clock Disabled
#1 : 1
TIMER3 Clock Enabled
End of enumeration elements list.
WDTCKEN : Watchdog Timer Clock Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog Timer Clock Disabled
#1 : 1
Watchdog Timer Clock Enabled
End of enumeration elements list.
I2C0CKEN : I2C0 Clock Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C0 Clock Disabled
#1 : 1
I2C0 Clock Enabled
End of enumeration elements list.
I2C1CKEN : I2C1 Clock Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C1 Clock Disabled
#1 : 1
I2C1 Clock Enabled
End of enumeration elements list.
RTCCKEN : RTC Clock Enable Control\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC Clock Disabled
#1 : 1
RTC Clock Enabled
End of enumeration elements list.
PWMCKEN : PWM Clock Enable Control\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Clock Disabled
#1 : 1
PWM Clock Enabled
End of enumeration elements list.
SPI0CKEN : SPI0 Clock Enable Control\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0 Clock Disabled
#1 : 1
SPI0 Clock Enabled
End of enumeration elements list.
SPI1CKEN : SPI1 Clock Enable Control\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI1 Clock Disabled
#1 : 1
SPI1 Clock Enabled
End of enumeration elements list.
UART0CKEN : UART0 Clock Enable Control\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 Clock Disabled
#1 : 1
UART0 Clock Enabled
End of enumeration elements list.
UART1CKEN : UART1 Clock Enable Control\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 Clock Disabled
#1 : 1
UART1 Clock Enabled
End of enumeration elements list.
UART2CKEN : UART2 Clock Enable Control\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART2 Clock Disabled
#1 : 1
UART2 Clock Enabled
End of enumeration elements list.
I2SCKEN : I2S Clock Enable Control\n
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2S Clock Disabled
#1 : 1
I2S Clock Enabled
End of enumeration elements list.
ADCCKEN : ADC Clock Enable Control\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC Clock Disabled
#1 : 1
ADC Clock Enabled
End of enumeration elements list.
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