PA_MODE

PB_MODE

PB_PUEN

PB_DOUT

PB_PIN

PC_MODE

PC_PUEN

PC_DOUT

PC_PIN

PD_MODE

PD_PUEN

PD_DOUT

PD_PIN

PA_PUEN

GPIO_DBCTL (DBCTL)

PA_DOUT

PA_INTSRCGP

PB_INTSRCGP

PC_INTSRCGP

PD_INTSRCGP

PA_INTEN

PB_INTEN

PC_INTEN

PD_INTEN

GPIO_INTCTL (INTCTL)

PA_LATCHDAT

PB_LATCHDAT

PC_LATCHDAT

PD_LATCHDAT

GPIO_INTSTSA_B (INTSTSA_B)

GPIO_INTSTSC_D (INTSTSC_D)

PA_PIN

MODE0 : Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE1 : Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE2 : Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE3 : Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE4 : Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE5 : Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE6 : Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE7 : Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE8 : Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE9 : Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE10 : Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE11 : Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE12 : Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE13 : Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE14 : Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE15 : Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PULLSEL0 : Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PULLSEL1 : Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PULLSEL2 : Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PULLSEL3 : Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PULLSEL4 : Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PULLSEL5 : Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PULLSEL6 : Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PULLSEL7 : Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PULLSEL8 : Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PULLSEL9 : Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PULLSEL10 : Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PULLSEL11 : Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PULLSEL12 : Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PULLSEL13 : Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PULLSEL14 : Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PULLSEL15 : Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN0 : EINT (EINT0~EINT3) De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding EINT. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is regarded as the signal bounce and will not trigger the interrupt. The de- bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [7:4]).\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN1 : EINT (EINT0~EINT3) De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding EINT. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is regarded as the signal bounce and will not trigger the interrupt. The de- bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [7:4]).\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN2 : EINT (EINT0~EINT3) De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding EINT. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is regarded as the signal bounce and will not trigger the interrupt. The de- bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [7:4]).\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN3 : EINT (EINT0~EINT3) De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding EINT. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is regarded as the signal bounce and will not trigger the interrupt. The de- bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [7:4]).\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBCLKSEL : De-bounce Sampling Cycle Selection\n
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT0 : Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT1 : Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT2 : Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT3 : Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT4 : Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT5 : Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT6 : Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT7 : Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT8 : Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT9 : Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT10 : Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT11 : Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT12 : Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT13 : Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT14 : Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT15 : Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSEL0 : Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSEL1 : Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSEL2 : Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSEL3 : Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSEL4 : Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSEL5 : Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSEL6 : Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSEL7 : Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSEL8 : Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSEL9 : Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSEL10 : Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSEL11 : Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSEL12 : Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSEL13 : Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSEL14 : Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSEL15 : Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FEIEN0 : Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FEIEN1 : Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FEIEN2 : Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FEIEN3 : Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FEIEN4 : Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FEIEN5 : Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FEIEN6 : Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FEIEN7 : Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FEIEN8 : Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FEIEN9 : Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FEIEN10 : Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FEIEN11 : Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FEIEN12 : Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FEIEN13 : Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FEIEN14 : Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FEIEN15 : Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REIEN0 : Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REIEN1 : Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REIEN2 : Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REIEN3 : Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REIEN4 : Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REIEN5 : Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REIEN6 : Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REIEN7 : Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REIEN8 : Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REIEN9 : Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REIEN10 : Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REIEN11 : Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REIEN12 : Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REIEN13 : Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REIEN14 : Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REIEN15 : Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTLHEN0 : Enable Latch PA.N/PB.N/PC.N/PD.N Value When EINTn Happen\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTLHEN1 : Enable Latch PA.N/PB.N/PC.N/PD.N Value When EINTn Happen\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTLHEN2 : Enable Latch PA.N/PB.N/PC.N/PD.N Value When EINTn Happen\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTLHEN3 : Enable Latch PA.N/PB.N/PC.N/PD.N Value When EINTn Happen\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKEN0 : GPIO Interrupt Wake Up System Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKEN1 : GPIO Interrupt Wake Up System Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKEN2 : GPIO Interrupt Wake Up System Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKEN3 : GPIO Interrupt Wake Up System Enable Control\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTCTL : Interrupt Request Source Control\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DAT0 : Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
bits : 0 - 0 (1 bit)
access : read-only

DAT1 : Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
bits : 1 - 1 (1 bit)
access : read-only

DAT2 : Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
bits : 2 - 2 (1 bit)
access : read-only

DAT3 : Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
bits : 3 - 3 (1 bit)
access : read-only

DAT4 : Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
bits : 4 - 4 (1 bit)
access : read-only

DAT5 : Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
bits : 5 - 5 (1 bit)
access : read-only

DAT6 : Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
bits : 6 - 6 (1 bit)
access : read-only

DAT7 : Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
bits : 7 - 7 (1 bit)
access : read-only

DAT8 : Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
bits : 8 - 8 (1 bit)
access : read-only

DAT9 : Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
bits : 9 - 9 (1 bit)
access : read-only

DAT10 : Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
bits : 10 - 10 (1 bit)
access : read-only

DAT11 : Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
bits : 11 - 11 (1 bit)
access : read-only

DAT12 : Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
bits : 12 - 12 (1 bit)
access : read-only

DAT13 : Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
bits : 13 - 13 (1 bit)
access : read-only

DAT14 : Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
bits : 14 - 14 (1 bit)
access : read-only

DAT15 : Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
bits : 15 - 15 (1 bit)
access : read-only

PAIF0 : Port a Pin[N] Interrupt Source Flag Write Operation: When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt. Note: Write 1 to clear the correspond interrupt source
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAIF1 : Port a Pin[N] Interrupt Source Flag Write Operation: When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt. Note: Write 1 to clear the correspond interrupt source
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAIF2 : Port a Pin[N] Interrupt Source Flag Write Operation: When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt. Note: Write 1 to clear the correspond interrupt source
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAIF3 : Port a Pin[N] Interrupt Source Flag Write Operation: When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt. Note: Write 1 to clear the correspond interrupt source
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAIF4 : Port a Pin[N] Interrupt Source Flag Write Operation: When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt. Note: Write 1 to clear the correspond interrupt source
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAIF5 : Port a Pin[N] Interrupt Source Flag Write Operation: When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt. Note: Write 1 to clear the correspond interrupt source
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAIF6 : Port a Pin[N] Interrupt Source Flag Write Operation: When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt. Note: Write 1 to clear the correspond interrupt source
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAIF7 : Port a Pin[N] Interrupt Source Flag Write Operation: When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt. Note: Write 1 to clear the correspond interrupt source
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAIF8 : Port a Pin[N] Interrupt Source Flag Write Operation: When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt. Note: Write 1 to clear the correspond interrupt source
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAIF9 : Port a Pin[N] Interrupt Source Flag Write Operation: When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt. Note: Write 1 to clear the correspond interrupt source
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAIF10 : Port a Pin[N] Interrupt Source Flag Write Operation: When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt. Note: Write 1 to clear the correspond interrupt source
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAIF11 : Port a Pin[N] Interrupt Source Flag Write Operation: When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt. Note: Write 1 to clear the correspond interrupt source
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAIF12 : Port a Pin[N] Interrupt Source Flag Write Operation: When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt. Note: Write 1 to clear the correspond interrupt source
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAIF13 : Port a Pin[N] Interrupt Source Flag Write Operation: When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt. Note: Write 1 to clear the correspond interrupt source
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAIF14 : Port a Pin[N] Interrupt Source Flag Write Operation: When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt. Note: Write 1 to clear the correspond interrupt source
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAIF15 : Port a Pin[N] Interrupt Source Flag Write Operation: When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt. Note: Write 1 to clear the correspond interrupt source
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBIF0 : Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBIF1 : Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBIF2 : Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBIF3 : Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBIF4 : Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBIF5 : Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBIF6 : Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBIF7 : Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBIF8 : Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBIF9 : Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBIF10 : Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBIF11 : Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBIF12 : Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBIF13 : Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBIF14 : Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBIF15 : Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PCIF0 : Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PCIF1 : Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PCIF2 : Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PCIF3 : Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PCIF4 : Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PCIF5 : Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PCIF6 : Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
bits : 6 - 6 (1 bit)
access : read-write