\n

PWM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x40 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x50 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PWM_CLKPSC (CLKPSC)

PWM_CMPDAT0 (CMPDAT0)

PWM_CNT0 (CNT0)

PWM_PERIOD1 (PERIOD1)

PWM_CMPDAT1 (CMPDAT1)

PWM_CNT1 (CNT1)

PWM_PERIOD2 (PERIOD2)

PWM_CMPDAT2 (CMPDAT2)

PWM_CNT2 (CNT2)

PWM_PERIOD3 (PERIOD3)

PWM_CMPDAT3 (CMPDAT3)

PWM_CNT3 (CNT3)

PWM_CLKDIV (CLKDIV)

PWM_INTEN (INTEN)

PWM_INTSTS (INTSTS)

PWM_CAPCTL01 (CAPCTL01)

PWM_CAPCTL23 (CAPCTL23)

PWM_RCAPDAT0 (RCAPDAT0)

PWM_FCAPDAT0 (FCAPDAT0)

PWM_RCAPDAT1 (RCAPDAT1)

PWM_FCAPDAT1 (FCAPDAT1)

PWM_RCAPDAT2 (RCAPDAT2)

PWM_FCAPDAT2 (FCAPDAT2)

PWM_RCAPDAT3 (RCAPDAT3)

PWM_FCAPDAT3 (FCAPDAT3)

PWM_CAPINEN (CAPINEN)

PWM_POEN (POEN)

PWM_CTL (CTL)

PWM_PERIOD0 (PERIOD0)


PWM_CLKPSC (CLKPSC)

PWM Pre-scale Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CLKPSC PWM_CLKPSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKPSC01 CLKPSC23 DZCNT01 DZCNT23

CLKPSC01 : Clock Pre-scale 0 for PWM Counter 0 1 Clock input is divided by (CLKPSC01+1) before it is fed to the counter 0 1.
bits : 0 - 7 (8 bit)
access : read-write

CLKPSC23 : Clock Pre-scale 1 for PWM Counter 2 3 Clock input is divided by (CLKPSC23+1) before it is fed to the counter 2 3.
bits : 8 - 15 (8 bit)
access : read-write

DZCNT01 : Dead-time Interval Register 0\nThese 8-bit determine Dead-time length.\n
bits : 16 - 23 (8 bit)
access : read-write

DZCNT23 : Dead-time Interval Register 1\nThese 8-bit determine Dead-time length.\n
bits : 24 - 31 (8 bit)
access : read-write


PWM_CMPDAT0 (CMPDAT0)

PWM Comparator Register 0
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CMPDAT0 PWM_CMPDAT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP

CMP : PWM Compare Register\nCMP determines the PWM output duty ratio.\nNote: Any write to CMP will take effect in the next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write


PWM_CNT0 (CNT0)

PWM Data Register 0
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PWM_CNT0 PWM_CNT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : PWM Data Register\nUser can monitor CNT to know current value in 16-bit down counter.
bits : 0 - 15 (16 bit)
access : read-only


PWM_PERIOD1 (PERIOD1)

PWM Period Register 1
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_PERIOD1 PWM_PERIOD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_CMPDAT1 (CMPDAT1)

PWM Comparator Register 1
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CMPDAT1 PWM_CMPDAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_CNT1 (CNT1)

PWM Data Register 1
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CNT1 PWM_CNT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_PERIOD2 (PERIOD2)

PWM Period Register 2
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_PERIOD2 PWM_PERIOD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_CMPDAT2 (CMPDAT2)

PWM Comparator Register 2
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CMPDAT2 PWM_CMPDAT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_CNT2 (CNT2)

PWM Data Register 2
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CNT2 PWM_CNT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_PERIOD3 (PERIOD3)

PWM Period Register 3
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_PERIOD3 PWM_PERIOD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_CMPDAT3 (CMPDAT3)

PWM Comparator Register 3
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CMPDAT3 PWM_CMPDAT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_CNT3 (CNT3)

PWM Data Register 3
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CNT3 PWM_CNT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_CLKDIV (CLKDIV)

PWM Clock Select Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CLKDIV PWM_CLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKDIV0 CLKDIV1 CLKDIV2 CLKDIV3

CLKDIV0 : PWM Counter 0 Clock Source Selection\nSelect clock input for PWM Counter 0.\n(Table is the same as CLKDIV3)
bits : 0 - 2 (3 bit)
access : read-write

CLKDIV1 : PWM Counter 1 Clock Source Selection\nSelect clock input for PWM Counter 1.\n(Table is the same as CLKDIV3)
bits : 4 - 6 (3 bit)
access : read-write

CLKDIV2 : PWM Counter 2 Clock Source Selection\nSelect clock input for PWM Counter 2.\n(Table is the same as CLKDIV3)
bits : 8 - 10 (3 bit)
access : read-write

CLKDIV3 : PWM Counter 3 Clock Source Selection\nSelect clock input for timer 3.\n
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 0

PWM_CLK/2

#001 : 1

PWM_CLK/4

#010 : 2

PWM_CLK/8

#011 : 3

PWM_CLK/16

#100 : 4

PWM_CLK/1

End of enumeration elements list.


PWM_INTEN (INTEN)

PWM Interrupt Enable Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_INTEN PWM_INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIEN

PIEN : PWM Period Interrupt Enable Control\nNote: Each bit controls the corresponding PWM channel.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : 0

Period interrupt Disabled

1 : 1

Period interrupt Enabled

End of enumeration elements list.


PWM_INTSTS (INTSTS)

PWM Interrupt Indication Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_INTSTS PWM_INTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIF

PIF : PWM Timer Interrupt Flag\nNote1: Each bit controls the corresponding PWM channel.\nNote2: User can clear each interrupt flag by writing a one to corresponding bit
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : 0

Interrupt Flag OFF

1 : 1

Interrupt Flag ON

End of enumeration elements list.


PWM_CAPCTL01 (CAPCTL01)

Capture Control Register 0
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CAPCTL01 PWM_CAPCTL01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPINV0 CRLIEN0 CFLIEN0 CAPEN0 CAPIF0 CRLIF0 CFLIF0 CAPINV1 CRLIEN1 CFLIEN1 CAPEN1 CAPIF1 CRLIF1 CFLIF1

CAPINV0 : Capture 0 Inverter Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Capture source inverter Disabled

#1 : 1

Capture source inverter Enabled. Reverse the input signal from GPIO

End of enumeration elements list.

CRLIEN0 : Channel 0 Rising Interrupt Enable Control\nNote: When Enabled, if Capture detects Channel 0 has rising transition, Capture issues an Interrupt.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel 0 Rising Interrupt Enable Disabled

#1 : 1

Channel 0 Rising Interrupt Enable Enabled

End of enumeration elements list.

CFLIEN0 : Channel 0 Falling Interrupt Enable Control\nNote: When Enabled, if Capture detects Channel 0 has falling transition, Capture issues an Interrupt.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel 0 Falling Interrupt Disabled

#1 : 1

Channel 0 Falling Interrupt Enabled

End of enumeration elements list.

CAPEN0 : Capture Channel 0 Function Enable Control\nNote1: When Enabled, Capture latched the PWM-counter value and saved to PWM_RCAPDAT0 (Rising latch) and PWM_FCAPDAT0 (Falling latch).\nNote2: When Disabled, Capture does not update PWM_RCAPDAT0 and PWM_FCAPDAT0, and disable Channel 0 Interrupt.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Capture function Disabled

#1 : 1

Capture function Enabled

End of enumeration elements list.

CAPIF0 : Capture 0 Interrupt Indication Note: If this bit is 1 , PWM-counter 0 will not reload when the next capture interrupt occur. Write 1 clear.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt Flag OFF

#1 : 1

Interrupt Flag ON

End of enumeration elements list.

CRLIF0 : Capture Rising Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

No capture rising latch condition happened

#1 : 1

Capture rising latch condition happened, and this flag will be set to high

End of enumeration elements list.

CFLIF0 : Capture Falling Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

No capture falling latch condition happened

#1 : 1

Capture falling latch condition happened, and this flag will be set to high

End of enumeration elements list.

CAPINV1 : Capture 1 Inverter Enable Control\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Capture source inverter Disabled

#1 : 1

Capture source inverter Enabled

End of enumeration elements list.

CRLIEN1 : Channel 1 Rising Interrupt Enable Control\nNote: When Enabled, if Capture detects Channel 1 has rising transition, Capture issues an Interrupt.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel 1 Rising Interrupt Disabled

#1 : 1

Channel 1 Rising Interrupt Enabled

End of enumeration elements list.

CFLIEN1 : Channel1 Falling Interrupt Enable Control\nNote: When Enabled, if Capture detects Channel 1 has falling transition, Capture issues an Interrupt.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel1 Falling Interrupt Disabled

#1 : 1

Channel1 Falling Interrupt Enabled

End of enumeration elements list.

CAPEN1 : Capture Channel 1 Function Enable Control\nNote1: When Enabled, Capture latched the PMW-counter 1 and saved to PWM_RCAPDAT1 (Rising latch) and PWM_FCAPDAT1 (Falling latch).\nNote2: When Disabled, Capture does not update PWM_RCAPDAT1 and PWM_FCAPDAT1, and disable Channel 1 Interrupt.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Capture function Disabled

#1 : 1

Capture function Enabled

End of enumeration elements list.

CAPIF1 : Capture 1 Interrupt Indication Note: If this bit is 1 , PWM-counter 1 will not reload when the next capture interrupt occurs. Write 1 to clear.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt Flag OFF

#1 : 1

Interrupt Flag ON

End of enumeration elements list.

CRLIF1 : Capture Rising Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

No capture rising latch condition happened

#1 : 1

Capture rising latch condition happened, and this flag will be set to high

End of enumeration elements list.

CFLIF1 : Capture Falling Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

No capture falling latch condition happened

#1 : 1

Capture falling latch condition happened, and this flag will be set to high

End of enumeration elements list.


PWM_CAPCTL23 (CAPCTL23)

Capture Control Register 1
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CAPCTL23 PWM_CAPCTL23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPINV2 CRLIEN2 CFLIEN2 CAPEN2 CAPIF2 CRLIF2 CFLIF2 CAPINV3 CRLIEN3 CFLIEN3 CAPEN3 CAPIF3 CRLIF3 CFLIF3

CAPINV2 : Capture 2 Inverter Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Capture source inverter Disabled

#1 : 1

Capture source inverter Enabled. Reverse the input signal from GPIO

End of enumeration elements list.

CRLIEN2 : Channel 2 Rising Interrupt Enable Control\nNote: When Enabled, if Capture detects Channel 2 has rising transition, Capture issues an Interrupt.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel 2 Rising Interrupt Disabled

#1 : 1

Channel 2 Rising Interrupt Enabled

End of enumeration elements list.

CFLIEN2 : Channel 2 Falling Interrupt Enable Control\nNote: When Enabled, if Capture detects Channel 2 has falling transition, Capture issues an Interrupt.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel 2 Falling Interrupt Disabled

#1 : 1

Channel 2 Falling Interrupt Enabled

End of enumeration elements list.

CAPEN2 : Capture Channel 2 Function Enable Control\nNote: When Enabled, Capture latched the PMW-counter value and saved to PWM_RCAPDAT2 (Rising latch) and PWM_FCAPDAT2 (Falling latch). When Disabled, Capture does not update PWM_RCAPDAT2 and PWM_FCAPDAT2, and disable Channel 2 Interrupt.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Capture function Disabled

#1 : 1

Capture function Enabled

End of enumeration elements list.

CAPIF2 : Capture 2 Interrupt Indication Note: If this bit is 1 , PWM-counter 2 will not reload when next capture interrupt occur.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt Flag OFF

#1 : 1

Interrupt Flag ON

End of enumeration elements list.

CRLIF2 : Capture Rising Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

No capture rising latch condition happened

#1 : 1

Capture rising latch condition happened, this flag will be set to high

End of enumeration elements list.

CFLIF2 : Capture Falling Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

No capture falling latch condition happened

#1 : 1

Capture falling latch condition happened, this flag will be set to high

End of enumeration elements list.

CAPINV3 : Capture 3 Inverter Enable Control\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Capture source inverter Disabled

#1 : 1

Capture source inverter Enabled. Reverse the input signal from GPIO

End of enumeration elements list.

CRLIEN3 : Channel 3 Rising Interrupt Enable Control\nNote: When Enabled, if Capture detects Channel 3 has rising transition, Capture issues an Interrupt.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel 3 Rising Interrupt Disabled

#1 : 1

Channel 3 Rising Interrupt Enabled

End of enumeration elements list.

CFLIEN3 : Channel 3 Falling Interrupt Enable Control\nNote: When Enabled, if Capture detects Channel 3 has falling transition, Capture issues an Interrupt.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel 3 Falling Interrupt Disabled

#1 : 1

Channel 3 Falling Interrupt Enabled

End of enumeration elements list.

CAPEN3 : Capture Channel 3 Function Enable Control\nNote: When Enabled, Capture latched the PMW-counter and saved to PWM_RCAPDAT3 (Rising latch) and PWM_FCAPDAT3 (Falling latch). When Disabled, Capture does not update PWM_RCAPDAT3 and PWM_FCAPDAT3, and disable Channel 3 Interrupt.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Capture function Disabled

#1 : 1

Capture function Enabled

End of enumeration elements list.

CAPIF3 : Capture 3 Interrupt Indication Note: If this bit is 1 , PWM-counter 3 will not reload when next capture interrupt occur.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt Flag OFF

#1 : 1

Interrupt Flag ON

End of enumeration elements list.

CRLIF3 : Capture Rising Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

No capture rising latch condition happened

#1 : 1

Capture rising latch condition happened, this flag will be set to high

End of enumeration elements list.

CFLIF3 : Capture Falling Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

No capture falling latch condition happened

#1 : 1

Capture falling latch condition happened, this flag will be set to high

End of enumeration elements list.


PWM_RCAPDAT0 (RCAPDAT0)

Capture Rising Latch Register (Channel 0)
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_RCAPDAT0 PWM_RCAPDAT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCAPDAT

RCAPDAT : Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition.
bits : 0 - 15 (16 bit)
access : read-write


PWM_FCAPDAT0 (FCAPDAT0)

Capture Falling Latch Register (Channel 0)
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_FCAPDAT0 PWM_FCAPDAT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCAPDAT

FCAPDAT : Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition.
bits : 0 - 15 (16 bit)
access : read-write


PWM_RCAPDAT1 (RCAPDAT1)

Capture Rising Latch Register (Channel 1)
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_RCAPDAT1 PWM_RCAPDAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_FCAPDAT1 (FCAPDAT1)

Capture Falling Latch Register (Channel 1)
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_FCAPDAT1 PWM_FCAPDAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_RCAPDAT2 (RCAPDAT2)

Capture Rising Latch Register (Channel 2)
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_RCAPDAT2 PWM_RCAPDAT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_FCAPDAT2 (FCAPDAT2)

Capture Falling Latch Register (Channel 2)
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_FCAPDAT2 PWM_FCAPDAT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_RCAPDAT3 (RCAPDAT3)

Capture Rising Latch Register (Channel 3)
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_RCAPDAT3 PWM_RCAPDAT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_FCAPDAT3 (FCAPDAT3)

Capture Falling Latch Register (Channel 3)
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_FCAPDAT3 PWM_FCAPDAT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_CAPINEN (CAPINEN)

Capture Input Enable Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CAPINEN PWM_CAPINEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPINEN

CAPINEN : Capture Input Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0

#1 : 1

PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin

End of enumeration elements list.


PWM_POEN (POEN)

PWM Output Enable Register
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_POEN PWM_POEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POEN

POEN : PWM Counter Output Enable Control\nNote: Each bit controls the corresponding PWM channel.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : 0

PWM Counter Output Disabled

1 : 1

PWM Counter Output Enabled

End of enumeration elements list.


PWM_CTL (CTL)

PWM Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CTL PWM_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTEN0 PINV0 CNTMODE0 DTEN01 DTEN23 CNTEN1 PINV1 CNTMODE1 CNTEN2 PINV2 CNTMODE2 CNTEN3 PINV3 CNTMODE3

CNTEN0 : PWM Counter 0 Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM Counter and clock prescaler stops running

#1 : 1

PWM Counter and clock prescaler starts running

End of enumeration elements list.

PINV0 : PWM Counter 0 Inverter ON/OFF\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Inverter OFF

#1 : 1

Inverter ON

End of enumeration elements list.

CNTMODE0 : PWM Counter 0 Auto-reload Mode/One-shot Mode\n If there is a rising transition at this bit, it will cause PWM_PERIOD0 and PWM_CMPDAT0 be cleared.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

One-shot mode

#1 : 1

Auto-reload mode

End of enumeration elements list.

DTEN01 : Dead-time 0 Generator Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Dead-time generator stops running

#1 : 1

Dead-time generator starts running

End of enumeration elements list.

DTEN23 : Dead-time 1 Generator Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Dead-time generator stops running

#1 : 1

Dead-time generator starts running

End of enumeration elements list.

CNTEN1 : PWM Counter 1 Enable Control\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM Counter and clock prescaler stops running

#1 : 1

PWM Counter and clock prescaler starts running

End of enumeration elements list.

PINV1 : PWM Counter 1 Inverter ON/OFF\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Inverter OFF

#1 : 1

Inverter ON

End of enumeration elements list.

CNTMODE1 : PWM Counter 1 Auto-reload Mode/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause PWM_PERIOD1 and PWM_CMPDAT1 be cleared.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

One-shot mode

#1 : 1

Auto-reload mode

End of enumeration elements list.

CNTEN2 : PWM Counter 2 Enable Control\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM Counter and clock prescaler stops running

#1 : 1

PWM Counter and clock prescaler starts running

End of enumeration elements list.

PINV2 : PWM Counter 2 Inverter ON/OFF\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Inverter OFF

#1 : 1

Inverter ON

End of enumeration elements list.

CNTMODE2 : PWM Counter 2 Auto-reload Mode/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause PWM_PERIOD2 and PWM_CMPDAT2 be cleared.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

One-shot mode

#1 : 1

Auto-reload mode

End of enumeration elements list.

CNTEN3 : PWM Counter 3 Enable Control\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM Counter and clock prescaler stops running

#1 : 1

PWM Counter and clock prescaler starts running

End of enumeration elements list.

PINV3 : PWM Counter 3 Inverter ON/OFF\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Inverter OFF

#1 : 1

Inverter ON

End of enumeration elements list.

CNTMODE3 : PWM Counter 3 Auto-reload Mode/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause PWM_PERIOD3 and PWM_CMPDAT3 be cleared.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

One-Shot mode

#1 : 1

Auto-Reload mode

End of enumeration elements list.


PWM_PERIOD0 (PERIOD0)

PWM Period Register 0
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_PERIOD0 PWM_PERIOD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIOD

PERIOD : PWM Period Register\nPERIOD determines the PWM period.\nNote: Any write to PERIOD will take effect in the next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write



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