WDT_CTL (CTL)

WDT_RSTSTS (RSTSTS)

WDT_ALTCTL (ALTCTL)

RSTCNT : Clear Watchdog Timer\nNote: This bit will be automatically cleared by hardware.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTEN : Watchdog Timer Reset Enable Control \nSetting this bit will enable the Watchdog Timer time-out reset function If the Watchdog Timer counter value has not been cleared after the specific Watchdog Timer reset delay period expires.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTFC : Watchdog Timer Reset Flag Cleared\nWrite 1 to clear the RSTF (WDT_RSTSTS [2]).
bits : 2 - 2 (1 bit)
access : read-write

IF : Watchdog Timer Interrupt Flag\nThis bit will set to 1 while Watchdog Timer counter value reaches the selected Watchdog Timer time-out interval\nNote: This bit is cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKEN : Watchdog Timer Wake-up Function Enable Control \nIf this bit is set to 1, while Watchdog Timer interrupt flag IF (WDT_CTL[3]) is generated to 1 and INTEN (WDT_CTL[6] Watchdog Timer interrupt enable) is enabled, the Watchdog Timer time-out interrupt signal will generate a wake-up trigger event to chip.\nNote: Chip can be woken-up by Watchdog Timer time-out interrupt signal generated only if Watchdog Timer clock source is selected to 32 kHz oscillator.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKF : Watchdog Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of Watchdog Timer \nNote: This bit is cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN : Watchdog Timer Interrupt Enable Control \nIf this bit is enabled, the Watchdog Timer time-out interrupt signal is generated and inform to CPU. \n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTEN : Watchdog Timer Enable Control \n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOUTSEL : Watchdog Timer Time-out Interval Selection \nThese three bits select the time-out interval period for the Watchdog Timer.\n
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ICEDEBUG : ICE Debug Mode Acknowledge Disable Control \nWatchdog Timer counter will keep going no matter CPU is held by ICE or not.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTF : Watchdog Timer Reset Flag \nThis bit indicates the system has been reset by Watchdog Timer time-out reset or not.\nNote: This bit is cleared by writing 1 to RSTFC (WDT_CTL [2]).
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RSTDSEL : Watchdog Timer Reset Delay Selection\nWhen Watchdog Timer time-out happened, software has a time named Watchdog Timer reset delay period to clear Watchdog Timer counter to prevent Watchdog Timer time-out reset happened. Software can select a suitable value of Watchdog Timer reset delay period for different Watchdog Timer time-out period.\nNote: This bit will be reset to 0 if Watchdog Timer time-out reset happened.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.