\n

WWDT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

WWDT_RLDCNT (RLDCNT)

WWDT_RSTSTS (RSTSTS)

WWDT_CTL (CTL)

WWDT_STATUS (STATUS)

WWDT_CNT (CNT)


WWDT_RLDCNT (RLDCNT)

Window Watchdog Timer Reload Counter Register
address_offset : 0x0 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

WWDT_RLDCNT WWDT_RLDCNT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLDCNT

RLDCNT : WWDT Reload Counter Bits\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F. \n Software can only write RLDCNT to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If software writes RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will generate immediately.
bits : 0 - 31 (32 bit)
access : write-only


WWDT_RSTSTS (RSTSTS)

Window Watchdog Timer Reset Status Register
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WWDT_RSTSTS WWDT_RSTSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WWDTRF

WWDTRF : WWDT Timer-out Reset Flag \nThis bit indicates the system has been reset by WWDT time-out reset or not.\n This bit is cleared by writing 1 to WWDTRFC (WWDT_STATUS [1])
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

WWDT time-out reset did not occur

#1 : 1

WWDT time-out reset occurred

End of enumeration elements list.


WWDT_CTL (CTL)

Window Watchdog Timer Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WWDT_CTL WWDT_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WWDTEN INTEN PSCSEL CMPDAT ICEDEBUG

WWDTEN : WWDT Enable Control\nSet this bit to enable Window Watchdog Timer counter counting.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Window Watchdog Timer counter is stopped

#1 : 1

Window Watchdog Timer counter is starting counting

End of enumeration elements list.

INTEN : WWDT Interrupt Enable Control\nIf this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

WWDT counter compare match interrupt Disabled

#1 : 1

WWDT counter compare match interrupt Enabled

End of enumeration elements list.

PSCSEL : WWDT Counter Prescale Period Selection\n
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0000 : 0

Pre-scale is 1 Max time-out period is 1 * 64 * TWWDT

#0001 : 1

Pre-scale is 2 Max time-out period is 2 * 64 * TWWDT

#0010 : 2

Pre-scale is 4 Max time-out period is 4 * 64 * TWWDT

#0011 : 3

Pre-scale is 8 Max time-out period is 8 * 64 * TWWDT

#0100 : 4

Pre-scale is 16 Max time-out period is 16 * 64 * TWWDT

#0101 : 5

Pre-scale is 32 Max time-out period is 32 * 64 * TWWDT

#0110 : 6

Pre-scale is 64 Max time-out period is 64 * 64 * TWWDT

#0111 : 7

Pre-scale is 128 Max time-out period is 128 * 64 * TWWDT

#1000 : 8

Pre-scale is 192 Max time-out period is 192 * 64 * TWWDT

#1001 : 9

Pre-scale is 256 Max time-out period is 256 * 64 * TWWDT

#1010 : 10

Pre-scale is 384 Max time-out period is 384 * 64 * TWWDT

#1011 : 11

Pre-scale is 512 Max time-out period is 512 * 64 * TWWDT

#1100 : 12

Pre-scale is 768 Max time-out period is 768 * 64 * TWWDT

#1101 : 13

Pre-scale is 1024 Max time-out period is 1024 * 64 * TWWDT

#1110 : 14

Pre-scale is 1536 Max time-out period is 1536 * 64 * TWWDT

#1111 : 15

Pre-scale is 2048 Max time-out period is 2048 * 64 * TWWDT

End of enumeration elements list.

CMPDAT : WWDT Window Compare Bits\nSet this register to adjust the valid reload window. \nSoftware can only write RLDCNT to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If Software writes RLDCNT when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
bits : 16 - 21 (6 bit)
access : read-write

ICEDEBUG : ICE Debug Mode Acknowledge Disable Control\nWWDT down counter will keep going no matter CPU is held by ICE or not.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

ICE debug mode acknowledgement effects WWDT counting

#1 : 1

ICE debug mode acknowledgement Disabled

End of enumeration elements list.


WWDT_STATUS (STATUS)

Window Watchdog Timer Status Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WWDT_STATUS WWDT_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WWDTIF WWDTRFC

WWDTIF : WWDT Compare Match Interrupt Flag \nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT value.\n This bit is cleared by writing 1 to WWDT_STATUS[0]
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

WWDT counter value matches CMPDAT value

End of enumeration elements list.

WWDTRFC : WWDT Timer-out Reset Flag Cleared\nWhen the window watch dog reset happened, the register WWDTRF (WWDT_RSTSTS [1]) will be set to 1. Write 1 to this bit and the WWDTRF (WWDT_RSTSTS [1]) will be cleared.
bits : 1 - 1 (1 bit)
access : read-write


WWDT_CNT (CNT)

Window Watchdog Timer Counter Value Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WWDT_CNT WWDT_CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTDAT

CNTDAT : WWDT Counter Value\nThis register reflects the current WWDT counter value and is read only.
bits : 0 - 5 (6 bit)
access : read-only



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