\n
address_offset : 0x0 Bytes (0x0)
size : 0x48 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x54 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
RTC Initiation Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : RTC Active Status (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
RTC is at reset state
#1 : 1
RTC is at normal active state
End of enumeration elements list.
INIT_STS : RTC Initiation (While Writing)
When RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC exit from reset state. Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
The INIT is a write-only field and read value will be always 0 .
RTC Internal Status (While Reading)
[31:8]: INIT[31:8]
[7:5]: RTC internal state machine of key detection
[4]: Status of power key, 0:pressed and 1:released
[3]: Status of power off request pwr_key_off
[2]: Level shifter reset
[1]: Level shifter enable
bits : 1 - 31 (31 bit)
access : read-write
RTC Calendar Loading Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAY : 1-Day Calendar Digit
bits : 0 - 3 (4 bit)
access : read-write
TENDAY : 10-Day Calendar Digit
bits : 4 - 5 (2 bit)
access : read-write
MON : 1-Month Calendar Digit
bits : 8 - 11 (4 bit)
access : read-write
TENMON : 10-Month Calendar Digit
bits : 12 - 12 (1 bit)
access : read-write
YEAR : 1-Year Calendar Digit
bits : 16 - 19 (4 bit)
access : read-write
TENYEAR : 10-Year Calendar Digit
bits : 20 - 23 (4 bit)
access : read-write
RTC Time Scale Selection Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
_24HEN : 24-hour / 12-hour Mode Selection\nIndicate that RTC_TIME and RTC_TALM are in 24-hour mode or 12-hour mode.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
12-hour time scale with AM and PM indication selected
#1 : 1
24-hour time scale selected
End of enumeration elements list.
RTC Day of the Week Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WEEKDAY : Day of the Week Register \n
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : 0
Sunday
1 : 1
Monday
2 : 2
Tuesday
3 : 3
Wednesday
4 : 4
Thursday
5 : 5
Friday
6 : 6
Saturday
End of enumeration elements list.
RTC Time Alarm Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC : 1-Sec Time Digit of Alarm Setting (0-9)
bits : 0 - 3 (4 bit)
access : read-write
TENSEC : 10-Sec Time Digit of Alarm Setting (0-5)
bits : 4 - 6 (3 bit)
access : read-write
MSKSEC : Mask Alarm by Second\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Activate
#1 : 1
Mask
End of enumeration elements list.
MIN : 1-Min Time Digit of Alarm Setting (0-9)
bits : 8 - 11 (4 bit)
access : read-write
TENMIN : 10-Min Time Digit of Alarm Setting (0-5)
bits : 12 - 14 (3 bit)
access : read-write
MSKMIN : Mask Alarm by Minute\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Activate
#1 : 1
Mask
End of enumeration elements list.
HR : 1-Hour Time Digit of Alarm Setting (0-9)
bits : 16 - 19 (4 bit)
access : read-write
TENHR : 10-hour Time Digit of Alarm Setting (0-2)\nWhen RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication. (If RTC_TIME[21] is 1, it indicates PM time message.)
bits : 20 - 21 (2 bit)
access : read-write
MSKHR : Mask Alarm by Hour\n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Activate
#1 : 1
Mask
End of enumeration elements list.
RTC Calendar Alarm Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAY : 1-Day Calendar Digit of Alarm Setting (0-9)
bits : 0 - 3 (4 bit)
access : read-write
TENDAY : 10-Day Calendar Digit of Alarm Setting (0-3)
bits : 4 - 5 (2 bit)
access : read-write
MSKDAY : Mask Alarm by Day\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Activate
#1 : 1
Mask
End of enumeration elements list.
MON : 1-Month Calendar Digit of Alarm Setting (0-9)
bits : 8 - 11 (4 bit)
access : read-write
TENMON : 10-Month Calendar Digit of Alarm Setting (0-1)
bits : 12 - 12 (1 bit)
access : read-write
MSKMON : Mask Alarm by Month\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Activate
#1 : 1
Mask
End of enumeration elements list.
YEAR : 1-Year Calendar Digit of Alarm Setting (0-9)
bits : 16 - 19 (4 bit)
access : read-write
TENYEAR : 10-Year Calendar Digit of Alarm Setting (0-9)
bits : 20 - 23 (4 bit)
access : read-write
MSKYEAR : Mask Alarm by Year\n
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Activate
#1 : 1
Mask
End of enumeration elements list.
WEEKDAY : Week Day Alarm Digit
bits : 28 - 30 (3 bit)
access : read-write
MSKWEEKDAY : Mask Alarm by Week Day\n
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Activate
#1 : 1
Mask
End of enumeration elements list.
RTC Leap Year Indication Register
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LEAPYEAR : Leap Year Indication Register (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
This year is not a leap year
#1 : 1
This year is leap year
End of enumeration elements list.
RTC Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALMIEN : Alarm Interrupt Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC Alarm Interrupt Disabled
#1 : 1
RTC Alarm Interrupt Enabled
End of enumeration elements list.
TICKIEN : Time Tick Interrupt Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC Time Tick Interrupt and counter Disabled
#1 : 1
RTC Time Tick Interrupt and counter Enabled
End of enumeration elements list.
PKEYIEN : Power Switch Interrupt Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power Switch Be Pressed Interrupt Disabled
#1 : 1
Power Switch Be Pressed Interrupt Enabled
End of enumeration elements list.
RALMIEN : Relative Alarm Interrupt Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC Relative Alarm Interrupt Disabled
#1 : 1
RTC Relative Alarm Interrupt Enabled
End of enumeration elements list.
RTC Interrupt Indication Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALMIF : RTC Alarm Interrupt Flag\nWhen RTC time counters RTC_TIME and RTC_CAL match the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled ALMIEN (RTC_INTEN[0]) is set to 1. Chip will be woken up if RTC Alarm Interrupt is enabled when chip is at Power-down mode.\nNote: Write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Alarm condition is not matched
#1 : 1
Alarm condition is matched
End of enumeration elements list.
TICKIF : RTC Time Tick Interrupt Flag\nWhen RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TICKIEN (RTC_INTEN[1]) is set to 1. Chip will also be woken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.\nNote: Write 1 to clear to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tick condition does not occur
#1 : 1
Tick condition occur
End of enumeration elements list.
POWKEYIF : Power Switch Interrupt Flag\nWhen RTC detect power key (RTC_nRWAKE) is pressed , the POWKEYIF (RTC_INTSYS[2]) is set to 1\nNote: Software can also clear this bit after RTC interrupt has occurred
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The power switch interrupt never occurred
#1 : 1
The power switch has been activated
End of enumeration elements list.
RELALMIF : RTC Relative Alarm Interrupt Indication\nNote: Software can also clear this bit after RTC interrupt has occurred
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Relative alarm interrupt never occurred
#1 : 1
Relative time counter and calendar counter have counted to a specified time recorded in RTC_TALM and RTC_CALM. RTC alarm interrupt has been activated
End of enumeration elements list.
RTC Time Tick Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TICKSEL : Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. \n
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Time tick is 1 second
#001 : 1
Time tick is 1/2 second
#010 : 2
Time tick is 1/4 second
#011 : 3
Time tick is 1/8 second
#100 : 4
Time tick is 1/16 second
#101 : 5
Time tick is 1/32 second
#110 : 6
Time tick is 1/64 second
#111 : 7
Time tick is 1/28 second
End of enumeration elements list.
RTC Power Time-out Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POWEN : Power ON\nRTC_RPWR will change to high state when POWEN value change from 0 to 1.\nNote: The following conditions will make RTC_RPWR low:\nSet POWEN bit to 0\nPOWOFFEN is set to 1 and the power key is pressed over the period of POWOFFT.\nThis bit can be read back after the RTC enable is active.
bits : 0 - 0 (1 bit)
access : read-write
SWPOWOFF : Software Core Power Disable Control\nIf the power key is pressed, the RTC_RPWR pin can be cleared by setting this bit and this can be cleared to 0 when the pressed power key, RTC_RPWR is released. If the power is not pressed, it is not used to set this bit.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#1 : 1
Force the RTC_RPWR to low
End of enumeration elements list.
POWOFFEN : Hardware Power Clear Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The RTC_RPWR pin will not be influenced by the pressed time of power key
#1 : 1
The RTC_RPWR pin will be cleared to low when the power key is pressed over the POWOFFT second
End of enumeration elements list.
ALMIEN : Normal Time Alarm\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal time alarm control Disabled
#1 : 1
Normal time alarm control Enabled
End of enumeration elements list.
RALMIEN : Relative Time Alarm\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The relative time alarm control Disabled
#1 : 1
The relative time alarm control Enabled
End of enumeration elements list.
EDGE_TRIG : Power Key Trigger Mode \n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
LEVEL TRIGGER, RTC is powered on while power key is pressed longer programmed duration
#1 : 1
EDGE TRIGE, RTC is powered on while power key is pressed longer than programmed duration and then released
End of enumeration elements list.
POWKEY : Power Key Status\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The power key is pressed to low
#1 : 1
The power key status is high
End of enumeration elements list.
POWOFFT : Power Clear Period\nIndicates that the period of the power core will be cleared after the power key is pressed. Its time scalar is one second so that the default is 5 second.
bits : 16 - 19 (4 bit)
access : read-write
RALMTIME : Relative Time Alarm Period (Second Unit)\nIndicates the period of the relative time alarm. Its maximum value is 1800.\n
bits : 20 - 31 (12 bit)
access : read-write
RTC Setting Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CBEN : 32768 Hz (LXT) Crystal Control\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Crystal Disabled
#1 : 1
Crystal Enabled
End of enumeration elements list.
IOMSEL : X32_IN and X32_OUT PAD Digital Input Mode Control\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital input mode
#1 : 1
Crystal mode (default value)
End of enumeration elements list.
XININDAT : X32_IN PAD Status\n
bits : 3 - 3 (1 bit)
access : read-only
XOUTDAT : X32_OUT PAD Status\n
bits : 4 - 4 (1 bit)
access : read-only
RC Oscillator Setting Register
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKSRC : Internal RC Oscillator Control\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal RC oscillator Disabled
#1 : 1
Internal RC oscillator Enabled
End of enumeration elements list.
RTC Access Enable Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RWEN : RTC Register Access Enable Password (R/W)\n
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0xa965 : 43365
Access Password
End of enumeration elements list.
RWENF : RTC Register Access Enable Flag (Read Only)\nNote: This bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and it will be cleared when RTC_RWEN[15:0] is not 0xA965.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
RTC register access Disabled
#1 : 1
RTC register access Enabled
End of enumeration elements list.
RC Oscillator Calibration Register
address_offset : 0x40 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CALCNT : Cycle Number of PCLK During 1Hz\nThat is generated by dividing RTC Clock. This number can be used to deduct the real clock rate of RTC clock.
bits : 0 - 31 (32 bit)
access : read-only
RTC Register Write Complete
address_offset : 0x44 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYNC : Polling the Flag to Detect RTC Register Write Complete\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Register cannot be written
#1 : 1
Register can be written because write complete
End of enumeration elements list.
RTC Spare Register 0
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC_SPRn : RTC Spare Register\n
bits : 0 - 31 (32 bit)
access : read-write
RTC Spare Register 1
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 2
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 3
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 4
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 5
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 6
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 7
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Frequency Compensation Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACTION : Fraction Part\nDigit in RTC_FREQADJ must be expressed as hexadecimal number.
bits : 0 - 5 (6 bit)
access : read-write
INTEGER : Integer Part\n
bits : 8 - 23 (16 bit)
access : read-write
PKEYTIME : Minimum Duration That Power Key Must Be Pressed to Turn on Core Power\n
bits : 24 - 27 (4 bit)
access : read-write
ADJTRG : RTC Clock Calibration Control
This bit will be kept at High while the calibration is ongoing and cleared to Low automatically while the calibration is done and the content of RTC_CALCNT register is valid calibration flow as follows.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC Clock calibration mechanism Disabled
#1 : 1
RTC Clock calibration mechanism Enabled
End of enumeration elements list.
RTC Time Loading Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC : 1-Sec Time Digit
bits : 0 - 3 (4 bit)
access : read-write
TENSEC : 10-Sec Time Digit
bits : 4 - 6 (3 bit)
access : read-write
MIN : 1-Min Time Digit
bits : 8 - 11 (4 bit)
access : read-write
TENMIN : 10-Min Time Digit
bits : 12 - 14 (3 bit)
access : read-write
HR : 1-Hour Time Digit
bits : 16 - 19 (4 bit)
access : read-write
TENHR : 10-Hour Time Digit
bits : 20 - 21 (2 bit)
access : read-write
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