\n
address_offset : 0x0 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection : not protected
UART Receive/Transmit Buffer Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAT : Receiving/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD. \nRead Operation:\nBy reading this register, the UART will return an 8-bit data received from receiving FIFO.
bits : 0 - 7 (8 bit)
access : read-write
UART Modem Control Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTS : nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
nRTS signal is active
#1 : 1
nRTS signal is inactive
End of enumeration elements list.
RTSACTLV : nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1010 and Figure 6.1011 for UART function mode.\nNote2: Refer to Figure 6.1021 and Figure 6.1022 for RS-485 function mode.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
nRTS pin output is high level active
#1 : 1
nRTS pin output is low level active. (Default)
End of enumeration elements list.
RTSSTS : nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.\n
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
nRTS pin output is low level voltage logic state
#1 : 1
nRTS pin output is high level voltage logic state
End of enumeration elements list.
UART Modem Status Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTSDETF : Detect nCTS State Change Flag (Read Only)
This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
Note: This bit is read only, but can be cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
nCTS input has not change state
#1 : 1
nCTS input has change state
End of enumeration elements list.
CTSSTS : nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
nCTS pin input is low level voltage logic state
#1 : 1
nCTS pin input is high level voltage logic state
End of enumeration elements list.
CTSACTLV : nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
nCTS pin input is high level active
#1 : 1
nCTS pin input is low level active. (Default)
End of enumeration elements list.
UART FIFO Status Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXOVIF : RX Overflow Error Interrupt Flag (Read Only)
This bit is set when RX FIFO overflow.
If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16/64 bytes this bit will be set.
Note: This bit is read only, but can be cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
RX FIFO is not overflow
#1 : 1
RX FIFO is overflow
End of enumeration elements list.
ABRDIF : Auto-baud Rate Detect Interrupt (Read Only)
Note1: This bit is set to logic 1 when auto-baud rate detect function is finished.
Note2: This bit is read only, but can be cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Auto-baud rate detect function is not finished
#1 : 1
Auto-baud rate detect function is finished
End of enumeration elements list.
ABRDTOIF : Auto-baud Rate Time-out Interrupt (Read Only)
Note1: This bit is set to logic 1 in Auto-baud Rate Detect mode and the baud rate counter is overflow.
Note2: This bit is read only, but can be cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Auto-baud rate counter is underflow
#1 : 1
Auto-baud rate counter is overflow
End of enumeration elements list.
ADDRDETF : RS-485 Address Byte Detect Flag (Read Only) \nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receiver detects a data that is not an address bit (bit 9 ='0')
#1 : 1
Receiver detects a data that is an address bit (bit 9 ='1')
End of enumeration elements list.
PEF : Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit .
Note: This bit is read only, but can be cleared by writing '1' to it.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
No parity error is generated
#1 : 1
Parity error is generated
End of enumeration elements list.
FEF : Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
Note: This bit is read only, but can be cleared by writing '1' to it.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
No framing error is generated
#1 : 1
Framing error is generated
End of enumeration elements list.
BIF : Break Interrupt Flag (Read Only)
This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits).
Note: This bit is read only, but can be cleared by writing '1' to it.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Break interrupt is generated
#1 : 1
Break interrupt is generated
End of enumeration elements list.
RXPTR : RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15/63. When the using level of RX FIFO Buffer equal to 16/64, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15/63.
bits : 8 - 13 (6 bit)
access : read-only
RXEMPTY : Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
RX FIFO is not empty
#1 : 1
RX FIFO is empty
End of enumeration elements list.
RXFULL : Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16/64, otherwise is cleared by hardware.
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
RX FIFO is not full
#1 : 1
RX FIFO is full
End of enumeration elements list.
TXPTR : TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15/63. When the using level of TX FIFO Buffer equal to 16/64, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15/63.
bits : 16 - 21 (6 bit)
access : read-only
TXEMPTY : Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty).
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
#0 : 0
TX FIFO is not empty
#1 : 1
TX FIFO is empty
End of enumeration elements list.
TXFULL : Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16/64, otherwise is cleared by hardware.
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
TX FIFO is not full
#1 : 1
TX FIFO is full
End of enumeration elements list.
TXOVIF : TX Overflow Error Interrupt Flag (Read Only)
If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
Note: This bit is read only, but can be cleared by writing 1 to it.
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
TX FIFO is not overflow
#1 : 1
TX FIFO is overflow
End of enumeration elements list.
TXEMPTYF : Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
TX FIFO is not empty
#1 : 1
TX FIFO is empty
End of enumeration elements list.
UART Interrupt Status Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDAIF : Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No RDA interrupt flag is generated
#1 : 1
RDA interrupt flag is generated
End of enumeration elements list.
THREIF : Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
No THRE interrupt flag is generated
#1 : 1
THRE interrupt flag is generated
End of enumeration elements list.
RLSIF : Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
No RLS interrupt flag is generated
#1 : 1
RLS interrupt flag is generated
End of enumeration elements list.
MODEMIF : MODEM Interrupt Flag (Read Only) Channel \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Modem interrupt flag is generated
#1 : 1
Modem interrupt flag is generated
End of enumeration elements list.
RXTOIF : Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Time-out interrupt flag is generated
#1 : 1
Time-out interrupt flag is generated
End of enumeration elements list.
BUFERRIF : Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5])is set, the transfer is not correct. If BFERRIEN (UART_INTEN [8]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only. This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
No buffer error interrupt flag is generated
#1 : 1
Buffer error interrupt flag is generated
End of enumeration elements list.
WKIF : UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.\nNote: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF(UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]).
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
No DATWKIF and CTSWKIF are generated
#1 : 1
DATWKIF or CTSWKIF
End of enumeration elements list.
LINIF : LIN Bus Interrupt Flag (Read Only) (Not Available in UART0 Channel)\nNote: This bit is read only. This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]), SLVHEF(UART_LINSTS[1]) and SLVSYNCF(UART_LINSTS[3]) all are cleared.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated
#1 : 1
At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated
End of enumeration elements list.
RDAINT : Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.\n
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
No RDA interrupt is generated
#1 : 1
RDA interrupt is generated
End of enumeration elements list.
THREINT : Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1.\n
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
No DATE interrupt is generated
#1 : 1
DATE interrupt is generated
End of enumeration elements list.
RLSINT : Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.\n
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
No RLS interrupt is generated
#1 : 1
RLS interrupt is generated
End of enumeration elements list.
MODEMINT : MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3] and MODEMIF(UART_INTSTS[4]) are both set to 1\n
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Modem interrupt is generated
#1 : 1
Modem interrupt is generated.
End of enumeration elements list.
RXTOINT : Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.\n
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Tout interrupt is generated
#1 : 1
Tout interrupt is generated
End of enumeration elements list.
BUFERRINT : Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BFERRIEN(UART_INTEN[5] and BUFERRIF(UART_INTSTS[5]) are both set to 1.\n
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
No buffer error interrupt is generated
#1 : 1
Buffer error interrupt is generated
End of enumeration elements list.
WKINT : UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set when DATWKIF or CTSWKIF is set to 1.\n
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
NO data or nCTS wake-up interrupt are generated
#1 : 1
Data or nCTS wake-up interrupt are generated
End of enumeration elements list.
LININT : LIN Bus Interrupt Indicator (Read Only)(Not Available in UART0 Channel)\nThis bit is set if LINIEN (UART_INTEN[8]) and LIN IF(UART_INTSTS[7]) are both set to 1.\n
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
No LIN Bus interrupt is generated
#1 : 1
The LIN Bus interrupt is generated
End of enumeration elements list.
CTSWKIF : nCTS Wake-up Interrupt Flag (Read Only)\nNote1: If WKCTSIEN (UART_INTEN[9])is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Chip stays in Power-down state
#1 : 1
Chip wake-up from Power-down state by nCTS wake-up
End of enumeration elements list.
DATWKIF : Data Wake-up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from Power-down state by data wake-up.\nNote1: If WKDATIEN (UART_INTEN[10]) is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Chip stays in Power-down state
#1 : 1
Chip wake-up from Power-down state by data wake-up
End of enumeration elements list.
UART Time-out Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOIC : Time-out Interrupt Comparator\n
bits : 0 - 7 (8 bit)
access : read-write
DLY : TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.
bits : 8 - 15 (8 bit)
access : read-write
UART Baud Rate Divisor Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRD : Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.102.
bits : 0 - 15 (16 bit)
access : read-write
EDIVM1 : Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.102.
bits : 24 - 27 (4 bit)
access : read-write
BAUDM0 : BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.102.
bits : 28 - 28 (1 bit)
access : read-write
BAUDM1 : BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.102.\n In IrDA mode must be operated in mode 0.
bits : 29 - 29 (1 bit)
access : read-write
UART IrDA Control Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXEN : IrDA Receiver/Transmitter Selection Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#1 : 1
IrDA Transmitter Enabled and Receiver Disabled
End of enumeration elements list.
TXINV : IrDA Inverse Transmitting Output Signal \n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
None inverse transmitting signal. (Default)
#1 : 1
Inverse transmitting output signal
End of enumeration elements list.
RXINV : IrDA Inverse Receive Input Signal \n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
None inverse receiving input signal
#1 : 1
Inverse receiving input signal. (Default)
End of enumeration elements list.
UART Alternate Control/Status Register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKFL : UART LIN Break Field Length (Only Available in UART1/UART2 Channel)\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1\n
bits : 0 - 3 (4 bit)
access : read-write
LINRXEN : LIN RX Enable Control (Only Available in UART1/UART2 Channel)\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
LIN RX mode Disabled
#1 : 1
LIN RX mode Enabled
End of enumeration elements list.
LINTXEN : LIN TX Break Mode Enable Control (Only Available in UART1/UART2 Channel)\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
LIN TX Break mode Disabled
#1 : 1
LIN TX Break mode Enabled
End of enumeration elements list.
RS485NMM : RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#1 : 1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
End of enumeration elements list.
RS485AAD : RS-485 Auto Address Detection Operation Mode (AAD)\n It cannot be active with RS-485_NMM operation mode.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#1 : 1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
End of enumeration elements list.
RS485AUD : RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
RS-485 Auto Direction Operation function (AUD) Disabled
#1 : 1
RS-485 Auto Direction Operation function (AUD) Enabled
End of enumeration elements list.
ADDRDEN : RS-485 Address Detection Enable Control\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Address detection mode Disabled
#1 : 1
Address detection mode Enabled
End of enumeration elements list.
ABRIF : Auto-baud Rate Interrupt Flag (Read Only)
This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
Note: This bit is read only, but it can be cleared by writing 1 to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
bits : 17 - 17 (1 bit)
access : read-only
ABRDEN : Auto-baud Rate Detect Enable Control\nNote: This bit is cleared automatically after auto-baud detection is finished.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-baud rate detect function Disabled
#1 : 1
Auto-baud rate detect function Enabled
End of enumeration elements list.
ABRDBITS : Auto-baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit.
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
#00 : 0
1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01
#01 : 1
2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02
#10 : 2
4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08
#11 : 3
8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80
End of enumeration elements list.
ADDRMV : Address Match Value \nThis field contains the RS-485 address match values.\n This field is used for RS-485 auto address detection mode.
bits : 24 - 31 (8 bit)
access : read-write
UART Function Select Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUNCSEL : Function Select\n
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
UART function
#01 : 1
LIN function (Only Available in UART1/UART2 Channel)
#10 : 2
IrDA function
#11 : 3
RS-485 function
End of enumeration elements list.
UART LIN Control Register *
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLVEN : LIN Slave Mode Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
LIN Slave mode Disabled
#1 : 1
LIN Slave mode Enabled
End of enumeration elements list.
SLVHDEN : LIN Slave Header Detection Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
LIN slave header detection Disabled
#1 : 1
LIN slave header detection Enabled
End of enumeration elements list.
SLVAREN : LIN Slave Automatic Resynchronization Mode Enable Control\nNote2: When operating in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.10.5.9(Slave mode with automatic resynchronization).
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
LIN automatic resynchronization Disabled
#1 : 1
LIN automatic resynchronization Enabled
End of enumeration elements list.
SLVDUEN : LIN Slave Divider Update Method Enable Control\nNote2: This bit is used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in 6.10.5.9 (Slave mode with automatic resynchronization).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time)
#1 : 1
UART_BAUD is updated at the next received character. User must set the bit before checksum reception
End of enumeration elements list.
MUTE : LIN Mute Mode Enable Control\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.10.5.9 (LIN Slave mode).
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
LIN mute mode Disabled
#1 : 1
LIN mute mode Enabled
End of enumeration elements list.
SENDH : LIN TX Send Header Enable Control
The LIN TX header can be break field or break and sync field or break, sync and frame ID field , it is depend on setting HSEL (UART_LINCTL[23:22]).
Note1: These registers are shadow registers of LINTXEN (UART_ALTCTL [7]) user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]).
Note2: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Send LIN TX header Disabled
#1 : 1
Send LIN TX header Enabled
End of enumeration elements list.
IDPEN : LIN ID Parity Enable Control\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
LIN frame ID parity Disabled
#1 : 1
LIN frame ID parity Enabled
End of enumeration elements list.
BRKDETEN : LIN Break Detection Enable Control\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
LIN break detection Disabled
#1 : 1
LIN break detection Enabled
End of enumeration elements list.
RXOFF : LIN Receiver Disable Control\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
LIN receiver Enabled
#1 : 1
LIN receiver Disabled
End of enumeration elements list.
BITERREN : Bit Error Detect Enable Control\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit error detection function Disabled
#1 : 1
Bit error detection Enabled
End of enumeration elements list.
BRKFL : LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL, User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).\nNote2: This break field length is BRKFL + 1.\n
bits : 16 - 19 (4 bit)
access : read-write
BSL : LIN Break/Sync Delimiter Length \nNote: This bit is used for LIN master to send header field.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
The LIN break/sync delimiter length is 1-bit time
#01 : 1
The LIN break/sync delimiter length is 2-bit time
#10 : 2
The LIN break/sync delimiter length is 3-bit time
#11 : 3
The LIN break/sync delimiter length is 4-bit time
End of enumeration elements list.
HSEL : LIN Header Select \n
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
The LIN header includes break field
#01 : 1
The LIN header includes break field and sync field
#10 : 2
The LIN header includes break field , sync field and frame ID field
#11 : 3
Reserved
End of enumeration elements list.
PID : LIN PID Bits\nIf the parity generated by hardware, and user fills in ID0~ID5, (PID [29:24]), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must fill a frame ID and parity in this field.\nNote1: User can fill in any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\nNote2: This field can be used for LIN Master mode or Slave mode.
bits : 24 - 31 (8 bit)
access : read-write
UART LIN Status Register *
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLVHDETF : LIN Slave Header Detection Flag (Read Only)
This bit is set by hardware when a LIN header is detected in LIN Slave mode and be cleared by writing 1 to it.
Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ( break + sync + frame ID ), the SLVHDETF will be set whether the frame ID correct or not.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
LIN header not detected
#1 : 1
LIN header detected (break + sync + frame ID)
End of enumeration elements list.
SLVHEF : LIN Slave Header Error Flag (Read Only)
This bit is set by hardware when a LIN header error is detected in LIN Slave mode and be cleared by writing 1 to it. The header errors include break delimiter is too short (less than 0.5 bit time) , frame error in sync field or Identifier field , sync field data is not 0x55 in Non-Automatic Resynchronization mode , sync field deviation error with Automatic Resynchronization mode , sync field measure time-out with Automatic Resynchronization mode and LIN header reception time-out .
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
LIN header error not detected
#1 : 1
LIN header error detected
End of enumeration elements list.
SLVIDPEF : LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No active
#1 : 1
Receipted frame ID parity is not correct
End of enumeration elements list.
SLVSYNCF : LIN Slave Sync Field (Read Only)\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but it can be cleared by writing 1 to it.\nNote3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
The current character is not at LIN sync state
#1 : 1
The current character is at LIN sync state
End of enumeration elements list.
BRKDETF : LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\n
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
LIN break not detected
#1 : 1
LIN break detected
End of enumeration elements list.
BITEF : Bit Error Detect Status Flag (Read Only) \nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF (UART_LINSTS[9]) will be set.\n
bits : 9 - 9 (1 bit)
access : read-only
UART Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDAIEN : Receive Data Available Interrupt Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive data available interrupt Disabled
#1 : 1
Receive data available interrupt Enabled
End of enumeration elements list.
THREIEN : Transmit Holding Register Empty Interrupt Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit holding register empty interrupt Disabled
#1 : 1
Transmit holding register empty interrupt Enabled
End of enumeration elements list.
RLSIEN : Receive Line Status Interrupt Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive Line Status interrupt Disabled
#1 : 1
Receive Line Status interrupt Enabled
End of enumeration elements list.
MODEMIEN : Modem Status Interrupt Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Modem status interrupt Disabled
#1 : 1
Modem status interrupt Enabled
End of enumeration elements list.
RXTOIEN : RX Time-out Interrupt Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX time-out interrupt Disabled
#1 : 1
RX time-out interrupt Enabled
End of enumeration elements list.
BUFERRIEN : Buffer Error Interrupt Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Buffer error interrupt Disabled
#1 : 1
Buffer error interrupt Enabled
End of enumeration elements list.
LINIEN : LIN Bus Interrupt Enable Control (Not Available in UART1/UART2)\n This bit is used for LIN function mode.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
LIN bus interrupt Disabled
#1 : 1
LIN bus interrupt Enabled
End of enumeration elements list.
WKCTSIEN : nCTS Wake-up Interrupt Enable Control\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
nCTS wake-up system function Disabled
#1 : 1
Wake-up system function Enabled. When the system is in Power-down mode, an external nCTS change will wake up system from Power-down mode
End of enumeration elements list.
WKDATIEN : Incoming Data Wake-up Interrupt Enable Control
Hardware will clear this bit when the incoming data wake-up operation finishes and system clock work stable.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Incoming data wake-up system function Disabled
#1 : 1
Incoming data wake-up system function Enabled. When the system is in Power-down mode, incoming data will wake up system from Power-down mode.
End of enumeration elements list.
TOCNTEN : Time-out Counter Enable Control\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time-out counter Disabled
#1 : 1
Time-out counter Enabled
End of enumeration elements list.
ATORTSEN : nRTS Auto-flow Control Enable Control\n When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
nRTS auto-flow control Disabled
#1 : 1
nRTS auto-flow control Enabled
End of enumeration elements list.
ATOCTSEN : nCTS Auto-flow Control Enable Control\n When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
nCTS auto-flow control Disabled
#1 : 1
nCTS auto-flow control Enabled
End of enumeration elements list.
ABRIEN : Auto-baud Rate Interrupt Enable Control\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-baud rate interrupt Disabled
#1 : 1
Auto-baud rate interrupt Enabled
End of enumeration elements list.
UART FIFO Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXRST : RX Field Software Reset Control\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the RX internal state machine and pointers
End of enumeration elements list.
TXRST : TX Field Software Reset Control\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the TX internal state machine and pointers
End of enumeration elements list.
RFITL : RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).\n
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
RX FIFO Interrupt Trigger Level is 1 byte
#0001 : 1
RX FIFO Interrupt Trigger Level is 4 bytes
#0010 : 2
RX FIFO Interrupt Trigger Level is 8 bytes
#0011 : 3
RX FIFO Interrupt Trigger Level is 14 bytes
#0100 : 4
RX FIFO Interrupt Trigger Level is 30/14 (64 FIFO/16 FIFO)
#0101 : 5
RX FIFO Interrupt Trigger Level is 46/14 (64 FIFO/16 FIFO)
#0110 : 6
RX FIFO Interrupt Trigger Level is 62/14 (64 FIFO/16 FIFO)
End of enumeration elements list.
RXOFF : Receiver Disable Control\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver Enabled
#1 : 1
Receiver Disabled
End of enumeration elements list.
RTSTRGLV : nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for automatic nRTS flow control.
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
nRTS Trigger Level is 1 bytes
#0001 : 1
nRTS Trigger Level is 4bytes
#0010 : 2
nRTS Trigger Level is 8 bytes
#0011 : 3
nRTS Trigger Level is 14 bytes
#0100 : 4
nRTS Trigger Level is 30/14 (64 FIFO/16 FIFO)
#0101 : 5
nRTS Trigger Level is 46/14 (64 FIFO/16 FIFO)
#0110 : 6
nRTS Trigger Level is 62/14 (64 FIFO/16 FIFO)
End of enumeration elements list.
UART Line Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WLS : Word Length Selection\nThis field sets UART word length.\n
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
5 bits
#01 : 1
6 bits
#10 : 2
7 bits
#11 : 3
8 bits
End of enumeration elements list.
NSB : Number of STOP Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
One STOP bit is generated in the transmitted data
#1 : 1
When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 STOP bit is generated in the transmitted data
End of enumeration elements list.
PBE : Parity Bit Enable Control\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No parity bit generated Disabled
#1 : 1
Parity bit generated Enabled
End of enumeration elements list.
EPE : Even Parity Enable Control\nNote: This bit is effective only when PBE (UART_LINE[3]) is set.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Odd number of logic 1's is transmitted and checked in each word
#1 : 1
Even number of logic 1's is transmitted and checked in each word
End of enumeration elements list.
SPE : Stick Parity Enable Control\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stick parity Disabled
#1 : 1
Stick parity Enabled
End of enumeration elements list.
BCB : Break Control\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Break Control Disabled
#1 : 1
Break Control Enabled
End of enumeration elements list.
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