Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
SPI Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIEN : SPI Transfer Control Enable Bit\nNote1: In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1. \nNote2: The byte reorder function is not supported when the Quad or Dual I/O mode is enabled.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transfer control bit Disabled
#1 : 1
Transfer control bit Enabled
End of enumeration elements list.
RXNEG : Receive on Negative Edge\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Received data input signal is latched on the rising edge of SPICLK
#1 : 1
Received data input signal is latched on the falling edge of SPICLK
End of enumeration elements list.
TXNEG : Transmit on Negative Edge\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitted data output signal is changed on the rising edge of SPICLK
#1 : 1
Transmitted data output signal is changed on the falling edge of SPICLK
End of enumeration elements list.
CLKPOL : Clock Polarity\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPICLK is idle low
#1 : 1
SPICLK is idle high
End of enumeration elements list.
SUSPITV : Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0]+0.5) * period of SPICLK clock cycle\nExample:\n
bits : 4 - 7 (4 bit)
access : read-write
DWIDTH : Data Transmit Bit Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
bits : 8 - 12 (5 bit)
access : read-write
LSB : Send LSB First\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first
#1 : 1
The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX)
End of enumeration elements list.
UNITIEN : Unit Transfer Interrupt Enable Control\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI unit transfer interrupt Disabled
#1 : 1
SPI unit transfer interrupt Enabled
End of enumeration elements list.
SLAVE : Slave Mode Enable Control\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master mode
#1 : 1
Slave mode
End of enumeration elements list.
REORDER : Byte Reorder Function Enable Control\nNote: Byte reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Byte reorder function Disabled
#1 : 1
Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4])
End of enumeration elements list.
SPI FIFO Control Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXRST : Clear Receive FIFO Control\nNote: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear receive FIFO control. The RXFULL (SPI_STATUS[9]) will be cleared to 0 and the RXEMPTY (SPI_STATUS[8]) will be set to 1. This bit will be cleared to 0 by hardware about 3 system clocks+3 SPI engine clock after it is set to 1
End of enumeration elements list.
TXRST : Clear Transmit FIFO Control\nNote: If there is slave receive time-out event, the TXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear transmit FIFO control. The TXFULL (SPI_STATUS[17]) will be cleared to 0 and the TXEMPTY (SPI_STATUS[16]) will be set to 1. This bit will be cleared to 0 by hardware about 3 system clocks+3 SPI engine clock after it is set to 1
End of enumeration elements list.
RXTHIEN : Receive FIFO Threshold Interrupt Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX FIFO threshold interrupt Disabled
#1 : 1
RX FIFO threshold interrupt Enabled
End of enumeration elements list.
TXTHIEN : Transmit FIFO Threshold Interrupt Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
TX FIFO threshold interrupt Disabled
#1 : 1
TX FIFO threshold interrupt Enabled
End of enumeration elements list.
RXTOIEN : Slave Receive Time-out Interrupt Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive time-out interrupt Disabled
#1 : 1
Receive time-out interrupt Enabled
End of enumeration elements list.
RXOVIEN : Receive FIFO Overrun Interrupt Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive FIFO overrun interrupt Disabled
#1 : 1
Receive FIFO overrun interrupt Enabled
End of enumeration elements list.
TXUFPOL : Transmit Under-run Data Out\nNote1: The under run event is active after the serial clock input and the hardware synchronous, so that the first 1~3 bit (depending on the relation between system clock and the engine clock) data out will be the last transaction data.\nNote2: If the frequency of system clock approach to engine clock, they may need 3-bit time to report the transmit under-run data out.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The SPI data out is keep 0 if there is transmit under-run event in Slave mode
#1 : 1
The SPI data out is keep 1 if there is transmit under-run event in Slave mode
End of enumeration elements list.
TXUFIEN : Slave Transmit Under Run Interrupt Enable Control\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave Transmit FIFO under-run interrupt Disabled
#1 : 1
Slave Transmit FIFO under-run interrupt Enabled
End of enumeration elements list.
RXFBCLR : Clear Receive FIFO\n Note: Auto cleared by Hardware.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear receive FIFO only
End of enumeration elements list.
TXFBCLR : Clear Transmit FIFO\n Note: Auto cleared by Hardware.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear transmit FIFO only
End of enumeration elements list.
RXTH : Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF (SPI_STATUS[10]) will be set to 1, else the RXTHIF (SPI_STATUS[10]) will be cleared to 0.
bits : 24 - 26 (3 bit)
access : read-write
TXTH : Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF (SPI_STATUS[18]) will be set to 1, else the TXTHIF (SPI_STATUS[18]) will be cleared to 0.
bits : 28 - 30 (3 bit)
access : read-write
SPI Status Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSY : SPI Unit Bus Status (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No transaction in the SPI bus
#1 : 1
SPI controller unit in busy state
End of enumeration elements list.
UNITIF : Unit Transfer Interrupt Status\nNote: This bit will be cleared by writing 1 to itself.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No transaction has been finished since this bit was cleared to 0
#1 : 1
SPI controller has finished one unit transfer
End of enumeration elements list.
SSACTIF : Slave Select Active Interrupt Status\nNote: This bit will be cleared by writing 1 to itself.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select active interrupt is cleared or did not occur
#1 : 1
Slave select active interrupt event has occurred
End of enumeration elements list.
SSINAIF : Slave Select Inactive Interrupt Status\nNote: This bit will be cleared by writing 1 to itself.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select inactive interrupt is cleared or did not occur
#1 : 1
Slave select inactive interrupt event has occurred
End of enumeration elements list.
SSLINE : Slave Select Line Bus Status (Read Only)\nNote: If SSACTPOL (SPI_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicates the slave select line bus status is 0
#1 : 1
Indicates the slave select line bus status is 1
End of enumeration elements list.
SLVTOIF : Slave Time-out Interrupt Status (Read Only)\nWhen the Slave Select is active and the value of SLVTOCNT (SPI_SSCTL[31:16]) is not 0 and the serial clock input, the slave time-out counter in SPI controller logic will be start. When the value of time-out counter greater or equal than the value of SLVTOCNT (SPI_SSCTL[31:16]) during before one transaction done, the slave time-out interrupt event will active.\nNote: If the DWIDTH (SPI_CTL[12:8]) is set 0x10, one transaction is equal 16 bits serial clock period.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Slave time-out is not active
#1 : 1
Slave time-out is active
End of enumeration elements list.
SLVBEIF : Slave Mode Error 0 Interrupt Status (Read Only)\nIn Slave mode, there is bit counter mismatch with DWIDTH (SPI_CTL[12:8]) when the slave select line goes to inactive state.\nNote: If the slave select active but there is no any serial clock input, the SLVBEIF (SPI_STATUS[6]) also active when the slave select goes to inactive state.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Slave mode error 0 event
#1 : 1
Slave mode error 0 occurs
End of enumeration elements list.
SLVURIF : Slave Mode Error 1 Interrupt Status (Read Only)\nIn Slave mode, transmit under-run occurs when the slave select line goes to inactive state.\n
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Slave mode error 1 event
#1 : 1
Slave mode error 1 occurs
End of enumeration elements list.
RXEMPTY : Receive FIFO Buffer Empty Indicator (Read Only)\n
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO buffer is not empty
#1 : 1
Receive FIFO buffer is empty
End of enumeration elements list.
RXFULL : Receive FIFO Buffer Empty Indicator (Read Only)\n
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO buffer is not empty
#1 : 1
Receive FIFO buffer is empty
End of enumeration elements list.
RXTHIF : Receive FIFO Threshold Interrupt Status (Read Only)\n
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the RX FIFO buffer is smaller than or equal to the setting value of RXTH (SPI_FIFOCTL[26:24])
#1 : 1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH (SPI_FIFOCTL[26:24])
End of enumeration elements list.
RXOVIF : Receive FIFO Overrun Status\nNote: This bit will be cleared by writing 1 to itself.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No receiver FIFO overrun status
#1 : 1
Receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1
End of enumeration elements list.
RXTOIF : Receive Time-out Interrupt Status\nNote: This bit will be cleared by writing 1 to itself.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No receive FIFO time-out event
#1 : 1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
End of enumeration elements list.
SPIENSTS : SPI Enable Bit Status (Read Only)\nThe clock source of SPI controller logic is engine clock, it is asynchronous with the system clock. In order to make sure the function is disabled in SPI controller logic, this bit indicates the real status of SPIEN (SPI_CTL[0]) in SPI controller logic for user.
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicate the transmit control bit is disabled
#1 : 1
Indicate the transfer control bit is active
End of enumeration elements list.
TXEMPTY : Transmit FIFO Buffer Empty Indicator (Read Only)\n
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO buffer is not empty
#1 : 1
Transmit FIFO buffer is empty
End of enumeration elements list.
TXFULL : Transmit FIFO Buffer Full Indicator (Read Only)\n
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO buffer is not full
#1 : 1
Transmit FIFO buffer is full
End of enumeration elements list.
TXTHIF : Transmit FIFO Threshold Interrupt Status (Read Only)\n
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH (SPI_FIFOCTL[30:28])
#1 : 1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH (SPI_FIFOCTL[30:28])
End of enumeration elements list.
TXUFIF : TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 3 system clock cycles + 2 peripheral clock cycles since the reset operation is done.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
No data in Transmit FIFO and TX shift register when the slave selection signal is active
End of enumeration elements list.
TXRXRST : FIFO CLR Status (Read Only)\nNote: Both the TXRST (SPI_FIFOCTL[1]), RXRST (SPI_FIFOCTL[0]), need 3 system clock+3 engine clock , the status of this bit support the user to monitor the clear function is doing or done.
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
Done the FIFO buffer clear function of TXRST (SPI_FIFOCTL[1]) or RXRST (SPI_FIFOCTL[0])
#1 : 1
Doing the FIFO buffer clear function of TXRST (SPI_FIFOCTL[1])or RXRST (SPI_FIFOCTL[0])
End of enumeration elements list.
RXCNT : Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
bits : 24 - 27 (4 bit)
access : read-only
TXCNT : Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
bits : 28 - 31 (4 bit)
access : read-only
SPI Data Transmit Register
address_offset : 0x20 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TX : Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffer. The number of valid bits depends on the setting of transmit bit width field of the SPI_CTL register.\nFor example, if DWIDTH (SPI_CTL[12:8]) is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH (SPI_CTL[12:8]) is set to 0x00, the SPI controller will perform a 32-bit transfer.
bits : 0 - 31 (32 bit)
access : write-only
SPI Data Receive Register
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX : Data Receive Register\nThere is 8-level FIFO buffer in this controller. The data receive register holds the earliest datum received from SPI data input pin. If the RXEMPTY (SPI_STATUS[8]) is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register.
bits : 0 - 31 (32 bit)
access : read-only
SPI Clock Divider Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDER : Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI engine clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \n\nwhere \n is the SPI engine clock source, which is defined in the clock control, clock control register.
bits : 0 - 7 (8 bit)
access : read-write
SPI Slave Select Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SS : Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0,\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
set the SPIn_SS line to inactive state.\nKeep the SPIn_SS line at inactive state
#1 : 1
set the SPIn_SS line to active state.\nSPIn_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIn_SS is specified in SSACTPOL (SPI_SSCTL[2])
End of enumeration elements list.
SSACTPOL : Slave Select Active Level\nThis bit defines the active status of slave select signal (SS).\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The slave select signal SS is active on low-level
#1 : 1
The slave select signal SS is active on high-level
End of enumeration elements list.
AUTOSS : Automatic Slave Select Function Enable (Master Only)\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bit of SPI_SSCTL[0]
#1 : 1
If this bit is set, SS signal will be generated automatically. It means that device/slave select signal, which is set in SPI_SSCTL[0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
End of enumeration elements list.
SLV3WIRE : Slave 3-wire Mode Enable Control\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI.\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
2-wire bi-direction interface
#1 : 1
3-wire bi-direction interface
End of enumeration elements list.
SLVTOIEN : Slave Mode Time-out Interrupt Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave mode time-out interrupt Disabled
#1 : 1
Slave mode time-out interrupt Enabled
End of enumeration elements list.
SLVTORST : Slave Mode Time-out FIFO Clear\nNote: Both the FIFO clear function, TX_CLK and RXRST, active automatically when there is a slave mode time-out event.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave mode Time-out FIFO Clear Disable
#1 : 1
Slave mode Time-out FIFO Clear Enable
End of enumeration elements list.
SLVBEIEN : Slave Mode Error 0 Interrupt Enable Control\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave mode error 0 interrupt Disable
#1 : 1
Slave mode error 0 interrupt Enable
End of enumeration elements list.
SLVURIEN : Slave Mode Error 1 Interrupt Enable Control\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave mode error 1 interrupt Disable
#1 : 1
Slave mode error 1 interrupt Enable
End of enumeration elements list.
SSACTIEN : Slave Select Active Interrupt Enable Control\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select active interrupt Disable
#1 : 1
Slave select active interrupt Enable
End of enumeration elements list.
SSINAIEN : Slave Select Inactive Interrupt Enable Control\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select inactive interrupt Disable
#1 : 1
Slave select inactive interrupt Enable
End of enumeration elements list.
SLVTOCNT : Slave Mode Time-out Period \nIn Slave mode, these bits indicate the time-out period when there is serial clock input during slave select active. The clock source of the time-out counter is Slave engine clock. If the value is 0, it indicates the slave mode time-out function is disabled.
bits : 16 - 31 (16 bit)
access : read-write
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