SPIM_CTL0 (CTL0)

SPIM_RX0 (RX0)

SPIM_RX1 (RX1)

SPIM_RX2 (RX2)

SPIM_RX3 (RX3)

SPIM_TX0 (TX0)

SPIM_TX1 (TX1)

SPIM_TX2 (TX2)

SPIM_TX3 (TX3)

SPIM_SRAMADDR (SRAMADDR)

SPIM_DMATBCNT (DMATBCNT)

SPIM_FADDR (FADDR)

SPIM_CTL1 (CTL1)

SPIM_VALIDCTL (VALIDCTL)

SPIM_RXCLKDLY (RXCLKDLY)

CIPHOFF : Cipher Disable Control\nNote1: Cipher function only can be disabled. If user wants to enable cipher function after disabled processing, the chip must be reset again.\nNote2: If there is not any key in the chip, the cipher will be disabled automatically.\nNote3: In ICE mode, the cipher will be disabled automatically.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BALEN : Balance the AHB Control Time Between Cipher Enable and Disable Control\nWhen cipher is enabled, the AHB control signal will delay some time caused by the encoding or decoding calculation. Therefore, if set BALEN to 1, it will make the AHB signal processing time with cipher disabled be equal to that with cipher enabled.\nNote: Only useful when cipher is disabled.
bits : 2 - 2 (1 bit)
access : read-write

B4ADDREN : 4-byte Address Mode Enable Control\nNote: Used for DMA Write/DMA Read/DMM mode.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IEN : Interrupt Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IF : Interrupt Flag\nWrite Operation:\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DWIDTH : Transmit/Receive Bit Length\nThis field specifies how many bits are transmitted/received in one transmit/receive transaction.\nNote1: Only used for I/O mode.\nNote2: Only 8-, 16-, 24-, and 32-bit are allowed. Other bit length will result in incorrect transfer.
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BURSTNUM : Transmit/Receive Burst Number\nThis field specifies how many transmit/receive transactions should be executed continuously in one transfer.\nNote: Only used for I/O Mode.
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

QDIODIR : SPI Interface Direction Select for Quad/Dual Mode\nNote: Only used for I/O mode.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SUSPITV : Suspend Interval\nNote: Only used for I/O mode.
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BITMODE : SPI Interface Bit Mode\nNote: Only used for I/O mode.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE : SPI Function Operation Mode\nNote: In DMA Write mode, hardware will send just one page program command per operation. Users must take care of cross-page cases.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMDCODE : Page Program Command Code\nNote1: Quad mode of SPI Flash must be enabled first by I/O mode before using quad page program/quad read commands.\nNote2: See support list for SPI Flash which support these command codes.\nNote3: For TYPE_1, TYPE_2, and TYPE_3 program flows, refer to Figure 6.133, Figure 6.134, and Figure 6.135.
bits : 24 - 31 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX : Data Receive Register The Data Receive Registers hold the received data of the last executed transfer. Number of valid RX registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM 0, received data are held in the most significant RX register first. Number of valid-bit is specified in SPIM_CTL0[DWIDTH]. If DWIDTH is 16, 24, or 32, received data are held in the least significant byte of RX register first. In a byte, received data are held in the most significant bit of RX register first.
bits : 0 - 31 (32 bit)
access : read-only

TX : Data Transmit Register The Data Transmit Registers hold the data to be transmitted in next transfer. Number of valid TX registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM 0, data are transmitted in the most significant TX register first. Number of valid-bit is specified in SPIM_CTL0[DWIDTH]. If DWIDTH is 16, 24, or 32, data are transmitted in the least significant byte of TX register first. In a byte, data are transmitted in the most significant bit of TX register first.
bits : 0 - 31 (32 bit)
access : read-write

ADDR : SRAM Memory Address\nFor DMA Read mode, this is the destination address for DMA transfer.\nFor DMA Write mode, this is the source address for DMA transfer.\nNote: This address must be word-aligned.
bits : 0 - 31 (32 bit)
access : read-write

CNT : DMA Transfer Byte Count Register\nIt indicates the transfer length for DMA process. \nNote: The unit for counting is byte.\nNote2: The number must be the multiple of 4.
bits : 0 - 23 (24 bit)
access : read-write

ADDR : SPI Flash Address Register\nFor DMA Read mode, this is the source address for DMA transfer.\nFor DMA Write mode, this is the destination address for DMA transfer.\nNote: This address must be word-aligned.
bits : 0 - 31 (32 bit)
access : read-write

SPIMEN : Go and Busy Status\nWrite Operation:\nNote: All registers should be set before writing 1 to the SPIMEN bit. When a transfer is in progress, you should not write to any register of this peripheral.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SS : Slave Select Active Enable Control\nNote: This interface can only drive one device/slave at a given time. Therefore, the slave selects of the selected device must be set to its active level before starting any read or write transfer.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SSACTPOL : Slave Select Active Level\nIt defines the active level of device/slave select signal (SPIM_SS).\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IFSEL : Device/Slave Interface Select\nNote: MCP and MCP64 only can be referenced by MCP SPI Flash pad location.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IDLECNT : Idle Interval\nIn DMM mode, IDLECNT is set to control the minimum idle time between two SPI Flash accesses. \nNote: Only used for DMM mode.
bits : 8 - 11 (4 bit)
access : read-write

DIVIDER : Clock Divider Register\nThe value in this field is the frequency divider of the system clock to generate the serial clock on the output SPIM_CLK pin. The desired frequency is obtained according to the following equation:\n\nNote: When set DIVIDER to zero, the frequency of SPIM_CLK will be equal to the frequency of SYS_CLK.
bits : 16 - 31 (16 bit)
access : read-write

VALIDSTS : Validation Status Bit\nThis bit will be updated when the VALIDEN bit changes.\nNote: Write 0 to clear it to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VALIDEN : Validation Enable Bit\nSetting this bit to enable the validation function. The function can check whether the code in SPI Flash is valid or not.\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DLYSEL : Rx Sample Clock Source Delay Chain Select\n
bits : 29 - 31 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.