I2S_CTL (CTL)

I2S_TX (TX)

I2S_RX (RX)

I2S_CODECCTL (CODECCTL)

I2S_TXSTADDR (TXSTADDR)

I2S_TXTHADDR (TXTHADDR)

I2S_TXEADDR (TXEADDR)

I2S_TXCADDR (TXCADDR)

I2S_RXSTADDR (RXSTADDR)

I2S_RXTHADDR (RXTHADDR)

I2S_RXEADDR (RXEADDR)

I2S_RXCADDR (RXCADDR)

I2S_CLKDIV (CLKDIV)

I2S_RXAVGCTL (RXAVGCTL)

I2S_RXLCHAVG (RXLCHAVG)

I2S_RXRCHAVG (RXRCHAVG)

I2S_IEN (IEN)

I2S_STATUS (STATUS)

I2SEN : I2S Controller Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXEN : Transmit Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

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RXEN : Receive Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MUTE : Transmit Mute Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

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WDWIDTH : Word Width\n
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

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MONO : Monaural Data\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

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FORMAT : Data Format Selection\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXTH : Transmit FIFO Threshold Level\nIf remain data word (32 bits) in transmit FIFO is the same or less than threshold level then TXTHIF flag is set.\n
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

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RXTH : Receive FIFO Threshold Level\nWhen received data word(s) in buffer is equal to or higher than threshold level then RXTHIF flag is set.\n
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

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RZCEN : Right Channel Zero-cross Detection Enable Control\nIf this bit is set to 1, when right channel data sign bit change or next shift data bits are all zero then RZCIF flag in I2S_STATUS register is set to 1.\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LZCEN : Left Channel Zero-cross Detect Enable Control\nIf this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCIF flag in I2S_STATUS register is set to 1.\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

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TXCLR : Clear Transmit FIFO\nNote: This bit will be cleared to 0 automatically.\nNote2: If clearing the transmit FIFO, TXCNT (I2S_STATUS[31:28]) returns to 0x0 and transmit FIFO becomes empty.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

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RXCLR : Clear Receive FIFO\nNote: This bit will be cleared to 0 automatically.\nNote2: If clearing the receiver FIFO, RXCNT (I2S_STATUS[27:24]) returns to 0x0 and receiver FIFO becomes empty.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

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TXDMAEN : TX DMA Enable Control (Transmit Path)\nNote: The I2S_TXSTADDR will be updated to new setting only when TXDMAEN is from low to high. Therefore, if you want to change I2S_TXSTADDR, you should confirm TXDMAEN is disabled.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

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RXDMAEN : RX DMA Enable Control (Record Path)\nNote: The I2S_RXSTADDR will be updated to new setting only when RXDMAEN is from low to high. Therefore, if you want to change I2S_RXSTADDR, you should confirm RXDMAEN is disabled.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

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RXLCH : Receive Left Channel Enable Control\n
bits : 23 - 23 (1 bit)
access : read-write

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PCMEN : PCM Interface Enable Control\n
bits : 24 - 24 (1 bit)
access : read-write

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MCLKEN : Master Clock Enable Control\nNote1: I2S_MCLK is always output.\nNote2: I2S_MCLK frequency is controlled by MCLKDIV[5:0].
bits : 25 - 25 (1 bit)
access : read-write

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SLAVE : Slave Mode I2S can operate as master or slave. For Master mode, I2S_BCLK and I2S_LRCLK signals are output to CODEC. In Slave mode, I2S_BCLK and I2S_LRCLK pins are received from CODEC. Note: If using internal CODEC, the I2S must be master mode.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

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CODECSEL : Internal CODEC or External CODEC Selection\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

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CODECRST : Internal CODEC Hardware Reset Control\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

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TX : Transmit FIFO Register\nI2S contains 16 words (16x32 bit) data FIFO for data transmssion. Write data to this register to prepare data for transmission. The remaining word number is indicated by TXCNT[3:0] in I2S_STATUS.
bits : 0 - 31 (32 bit)
access : write-only

RX : Receive FIFO Register\nI2S contains 16 words (16x32 bit) data FIFO for data receiving. Read this register to get data in FIFO. The remaining data word number is indicated by RXCNT[3:0] in I2S_STATUS register.
bits : 0 - 31 (32 bit)
access : read-only

DAT : Data Information\nThis parameter is used to read from the internal audio CODEC or write to the internal audio CODEC.
bits : 0 - 7 (8 bit)
access : read-write

ADDR : Address Information\nThis parameter is used to read from the internal audio CODEC or write to the internal audio CODEC.
bits : 8 - 15 (8 bit)
access : read-write

RW : Read or Write Command\nControl this command to read data from the internal audio CODEC or write data to.\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

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DEVID : Internal Audio CODEC Device ID\nThis parameter should be set to 40H.
bits : 17 - 23 (7 bit)
access : read-write

I2CCKDIV : SCK Clock Divider\nControl the SCK Timing Parameter.\nThe SCK frequency is (F_I2SCLK / (I2CCKDIV * 16)).\nNote: Cannot be zero.\nNote2: F_SCK must be lower than or equal to F_MCLK / 16.
bits : 24 - 30 (7 bit)
access : read-write

BUSY : Busy Flag\nIf the register 'I2S_CODECCTL' has been written, the HW would change the command to the I2C format because the internal audio CODEC interface is I2C. However, the speed of the I2C is slow. Thus, this bit is used to indicate the end of the I2C command.\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

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ADDR : TX DMA Start Address Register\nNote1: The address is word boundary.\nNote2: The address can't be set smaller than 0x2000_0000.
bits : 0 - 31 (32 bit)
access : read-write

ADDR : TX DMA Threshold Address Register\nNote1: The address is word boundary.\nNote2: The address can't be set smaller than 0x2000_0000.
bits : 0 - 31 (32 bit)
access : read-write

ADDR : TX DMA End Address Register\nNote1: The address is word boundary.\nNote2: If WDWIDTH[1:0] is equal to 0x2 or 0x3, user must set the correct end address to avoid the swap between right channel and left channel in stereo mode.\nNote2: The address can't be set smaller than 0x2000_0000.
bits : 0 - 31 (32 bit)
access : read-write

ADDR : TX DMA Current Address Register
bits : 0 - 31 (32 bit)
access : read-only

ADDR : RX DMA Start Address Register\nNote1: The address is word boundary.\nNote2: The address can't be set smaller than 0x2000_0000.
bits : 0 - 31 (32 bit)
access : read-write

ADDR : RX DMA Threshold Address Register\nNote1: The address is word boundary.\nNote2: The address can't be set smaller than 0x2000_0000.
bits : 0 - 31 (32 bit)
access : read-write

ADDR : RX DMA End Address Register\nNote1: The address is word boundary.\nNote2: If WDWIDTH[1:0] is equal to 0x2 or 0x3, user must set the correct end address to avoid the swap between right channel and left channel in stereo mode.\nNote3: The address can't be set smaller than 0x2000_0000.
bits : 0 - 31 (32 bit)
access : read-write

ADDR : RX DMA Current Address Register
bits : 0 - 31 (32 bit)
access : read-only

MCLKDIV : Master Clock Divider\nIf F_I2SCLK is (2*MCLKDIV)*256*F_LRCLK then software can program these bits to generate 256*F_LRCLK clock frequency as master clock to audio CODEC. But if MCLKDIV is set to 0, MCLK is the same as I2SCLK input.\n
bits : 0 - 5 (6 bit)
access : read-write

BCLKDIV : Bit Clock Divider\nUser can program these bits to generate the frequency of BCLK, when I2S operates in master mode. In Slave mode, the frequency of BCLK is controlled by master device.\n
bits : 8 - 16 (9 bit)
access : read-write

WINSEL : RX Data Average Window Select\nNote: Every window size samples will generate one average result.
bits : 0 - 3 (4 bit)
access : read-write

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RESULT : RX Left Channel Data Average Result\nThe average result of left channel received data.\n
bits : 0 - 31 (32 bit)
access : read-only

RESULT : RX Right Channel Data Average Result\nThe average result of left channel received data.\nNote: If MONO (I2S_CTL[6]), this register will be useless.
bits : 0 - 31 (32 bit)
access : read-only

RXUDIEN : Receive FIFO Underflow Interrupt Enable Control\nIf software reads receive FIFO when it is empty the RXUDIF flag in I2S_STATUS register is set to 1.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOVIEN : Receive FIFO Overflow Interrupt Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXTHIEN : Receive FIFO Threshold Level Interrupt Enable Control\nWhen data word in receive FIFO is equal to or higher then RXTH[3:0] and the RXTHIF bit is set to 1. If RXTHIEN bit is enabled, interrupt will occur.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDMAEIEN : RX DMA End Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and DMA current address is equal to I2S_RXEADDR register\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDMATIEN : RX DMA Threshold Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and DMA current address is equal to I2S_RXTHADDR register\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDMAEIEN : TX DMA End Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and DMA current address is equal to I2S_TXEADDR register\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDMATIEN : TX DMA Threshold Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and DMA current address is equal to I2S_TXTHADDR register\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXUDIEN : Transmit FIFO Underflow Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and transmit FIFO underflow flag is set to 1.\n
bits : 8 - 8 (1 bit)
access : read-write

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TXOVIEN : Transmit FIFO Overflow Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and transmit FIFO overflow flag is set to 1.\n
bits : 9 - 9 (1 bit)
access : read-write

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End of enumeration elements list.

TXTHIEN : Transmit FIFO Threshold Level Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH[3:0].\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RZCIEN : Right Channel Zero-cross Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and right channel zero-cross is detected.\n
bits : 11 - 11 (1 bit)
access : read-write

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LZCIEN : Left Channel Zero-cross Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and left channel zero-cross is detected.\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2SIF : I2S Interrupt Flag\nNote1: This flag is triggered if any of TXIF and RXIF bits are enabled.\nNote2: This bit is read only.
bits : 0 - 0 (1 bit)
access : read-write

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End of enumeration elements list.

RXIF : I2S Receive Interrupt\nNote1: This flag is triggered if any of RXTHIF, RXOVIF, RXUDIF, RDMATIF, and RDMAEIF occurs.\nNote2: This bit is read only.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXIF : I2S Transmit Interrupt\nNote1: This flag is triggered if any of LZCIF, RZCIF, TXTHIF, TXOIF, TXUDIF, TDMATIF, and TDMAEIF occurs.\nNote2: This bit is read only.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

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RIGHT : Right Channel\nIndicates that the current transmit data belongs to right channel\nNote: This bit is read only,
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDMAEIF : RX DMA Equal End Address Interrupt Flag\nIf RX DMA current address is equal to I2S_RXEADDR register, this interrupt flag will be set. If the RDMAEIEN is set, an interrupt to NVIC will occur.\nNote: Write 1 to clear this bit to zero
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDMATIF : RX DMA Equal Threshold Address Interrupt Flag\nIf RX DMA current address is equal to I2S_RXTHADDR register, this interrupt flag will be set. If the RDMATIEN is set, an interrupt to NVIC will occur.\nNote: Write 1 to clear this bit to zero
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDMAEIF : TX DMA Equal End Address Interrupt Flag\nIf TX DMA current address is equal to I2S_TXEADDR register, this interrupt flag will be set. If the TDMAEIEN is set, an interrupt to NVIC will occur.\nNote: Write 1 to clear this bit to zero
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDMATIF : TX DMA Equal Threshold Address Interrupt Flag\nIf TX DMA current address is equal to I2S_TXTHADDR register, this interrupt flag will be set. If the TDMATIEN is set, an interrupt to NVIC will occur.\nNote: Write 1 to clear this bit to zero
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXUDIF : Receive FIFO Underflow Flag\nRead receive FIFO when it is empty. Setting this bit to 1 indicates underflow occurred.\nNote: Write 1 to clear this bit to zero
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOVIF : Receive FIFO Overflow Flag\nWhen receive FIFO is full and receive hardware attempt write to data into receive FIFO this bit is set to 1, and data in 1st buffer is overwritten.\nNote: Write 1 to clear this bit to 0.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXTHIF : Receive FIFO Threshold Flag\nWhen data word(s) in receive FIFO is equal to or higher than the threshold value set in RXTH[3:0] the RXTHIF bit becomes to 1. It keeps at 1 till RXCNT[3:0] is less than RXTH[3:0] after software reads the I2S_RX register.\nNote: This bit is read only.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXFULL : Receive FIFO Full\nThis bit reflect data words number in receive FIFO is 16\nNote: This bit is read only.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXEMPTY : Receive FIFO Empty\nThis bit reflects data words number in receive FIFO is zero\nNote: This bit is read only.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXUDIF : Transmit FIFO Underflow Flag\nWhen transmit FIFO is empty and shift logic hardware read data from data FIFO causes this set to 1.\nNote: Write 1 to clear this bit to 0.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXOVIF : Transmit FIFO Overflow Flag\nWrite data to transmit FIFO when it is full and this bit set to 1\nNote: Write 1 to clear this bit to 0.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXTHIF : Transmit FIFO Threshold Flag\nWhen data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH[3:0] the TXTHIF bit becomes to 1. It keeps at 1 till TXCNT[3:0] is higher than TXTH[3:0] after software write I2S_TX register.\nNote: This bit is read only.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXFULL : Transmit FIFO Full\nThis bit reflect data word number in transmit FIFO is 16\nNote: This bit is read only.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXEMPTY : Transmit FIFO Empty\nThis bit reflect data word number in transmit FIFO is zero\nNote: This bit is read only.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXBUSY : Transmit Busy\nThis bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out. This bit is set to 1 when the first data is loaded to shift buffer. \nNote: This bit is read only.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RZCIF : Right Channel Zero-cross Flag\nIt indicates right channel next sample data sign bit is changed or all data bits are zero.\nNote: Write 1 to clear this bit to 0.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LZCIF : Left Channel Zero-cross Flag\nIt indicates left channel next sample data sign bit is changed or all data bits are zero.\nNote: Write 1 to clear this bit to 0.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXCNT : Receive FIFO Level\nThese bits indicate word number in receive FIFO\n
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXCNT : Transmit FIFO Level\nThese bits indicate word number in transmit FIFO\n
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.