SDH_FB_N (FB_N)

SDH_DMACTL (DMACTL)

SDH_DMASA (DMASA)

SDH_DMABCNT (DMABCNT)

SDH_DMAINTEN (DMAINTEN)

SDH_DMAINTSTS (DMAINTSTS)

SDH_GCTL (GCTL)

SDH_GINTEN (GINTEN)

SDH_GINTSTS (GINTSTS)

SDH_CTL (CTL)

SDH_CMDARG (CMDARG)

SDH_INTEN (INTEN)

SDH_INTSTS (INTSTS)

SDH_RESP0 (RESP0)

SDH_RESP1 (RESP1)

SDH_BLEN (BLEN)

SDH_TOUT (TOUT)

DATA : SDH Receiving/Transmit Flash Buffer\nThis buffer is used to receive/transmit data. It can be accessed by CPU or DMAC.
bits : 0 - 31 (32 bit)
access : read-write

DMAEN : DMAC Engine Enable Control\nNote1: If this bit is cleared, DMAC will ignore all DMA request and force Bus Master into IDLE state.\nNote2: If a target abort occurs, DMAEN will be cleared.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMARST : Software Engine Reset\nNote: Software resets DMA region.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SGEN : Scatter-gather Function Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMABUSY : DMA Transfer in Progress\nThis bit indicates that the DMA is transferred or not.\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ORDER : Determined to the PAD Table Fetching in Order or Out of Order\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMASA : DMA Transfer Starting Address \nThis field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMAC to retrieve or fill in data.\nIf DMAC is not in Normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table.\nNote: The address can't be set smaller than 0x2000_0000.
bits : 1 - 31 (31 bit)
access : read-write

BCNT : DMA Transfer Byte Count (Read Only) This field indicates the remained byte count of DMAC transfer. The value of this field is valid only when DMAC is busy otherwise, it is 0.
bits : 0 - 25 (26 bit)
access : read-only

ABORTIEN : DMA Read/Write Target Abort Interrupt Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WEOTIEN : Wrong EOT Encountered Interrupt Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABORTIF : DMA Read/Write Target Abort Interrupt Flag\nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WEOTIF : Wrong EOT Encountered Interrupt Flag\nWhen DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of DMAC), this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GCTLRST : Software Engine Reset\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SDEN : Secure-digital Functionality Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTAIEN : DMAC READ/WRITE Target Abort Interrupt Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTAIF : DMAC READ/WRITE Target Abort Interrupt Flag (Read Only)\nThis bit indicates DMAC received an ERROR response from internal AHB bus during DMA read/write operation. When Target Abort is occurred, please reset all engines.\nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

COEN : Command Output Enable Control\nNote: When operation is finished, this bit will be cleared automatically. Thus, don't write 0 to this bit (the controller will be abnormal).
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RIEN : Response Input Enable Control\nNote: When operation is finished, this bit will be cleared automatically. Thus, don't write 0 to this bit (the controller will be abnormal).
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIEN : Data Input Enable Control\nNote: When operation is finished, this bit will be cleared automatically. Thus, don't write 0 to this bit (the controller will be abnormal).
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOEN : Data Output Enable Control\nNote: When operation is finished, this bit will be cleared automatically. Thus, don't write 0 to this bit (the controller will be abnormal).
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

R2EN : Response R2 Input Enable Control\nNote: When operation is finished, this bit will be cleared automatically. Thus, don't write 0 to this bit (the controller will be abnormal).
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLK74OEN : Generating 74 Clock Cycles Output Enable Control\nNote: When operation is finished, this bit will be cleared automatically. Thus, don't write 0 to this bit (the controller will be abnormal).
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLK8OEN : Generating 8 Clock Cycles Output Enable Control\nNote: When operation is finished, this bit will be cleared automatically. Thus, don't write 0 to this bit (the controller will be abnormal).
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKKEEP0 : SD Clock Enable Control for Port 0\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMDCODE : SD Command Code\nThis register contains the SD command code (0x00 - 0x3F).
bits : 8 - 13 (6 bit)
access : read-write

CTLRST : Software Engine Reset\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBW : SD Data Bus Width (for 1-bit / 4-bit Selection)\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BLKCNT : Block Counts to Be Transferred or Received\nThis field contains the block counts for data-in and data-out transfer. For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance. Don't fill 0x0 to this field.\nFor READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1).
bits : 16 - 23 (8 bit)
access : read-write

SDNWR : NWR Parameter for Block Write Operation\nThis value indicates the NWR parameter for data block write operation in SD clock counts. The actual clock cycle will be SDNWR+1.
bits : 24 - 27 (4 bit)
access : read-write

ARGUMENT : SD Command Argument\nThis register contains a 32-bit value specifies the argument of SD command from host controller to SD card. Before triggering SDH_CTL [COEN], software should fill argument in this field.
bits : 0 - 31 (32 bit)
access : read-write

BLKDIEN : Block Transfer Done Interrupt Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRCIEN : CRC7, CRC16 and CRC Status Error Interrupt Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDIEN0 : SD0 Card Detection Interrupt Enable Control\nEnable/Disable interrupt generation of SD controller when card 0 is inserted or removed.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SDHIEN0 : SDH Interrupt Enable Control for Port 0\nEnable/Disable interrupt generation of SD host when SDH card 0 issues an interrupt via DAT [1] to host.\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTOIEN : Response Time-out Interrupt Enable Control\nEnable/Disable interrupt generation of SD controller when receiving response or R2 time-out. Time-out value is specified at TOUT.\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DITOIEN : Data Input Time-out Interrupt Enable Control\nEnable/Disable interrupt generation of SD controller when data input time-out. Time-out value is specified at TOUT.\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDSRC0 : SD0 Card Detect Source Selection\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BLKDIF : Block Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that SD host has finished all data-in or data-out block transfer. If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set.\nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CRCIF : CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only) This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer. When CRC error occurred, software should reset SD engine. Some responses (e.g. R3) do not have CRC-7 information with it the SD host will still calculate CRC-7, get CRC error and set this flag. In this condition, software should ignore CRC error and clear this bit manually. Note: This bit is read only, but can be cleared by writing '1' to it.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CRC7 : CRC-7 Check Status (Read Only)\nSD host will check CRC-7 correctness during each response in. If that response does not contain CRC-7 information (e.g. R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit.\n
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CRC16 : CRC-16 Check Status of Data-in Transfer (Read Only)\nSD host will check CRC-16 correctness after data-in transfer.\n
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CRCSTS : CRC Status Value of Data-out Transfer (Read Only)\nSD host will record CRC status of data-out transfer. Software could use this value to identify what type of error is during data-out transfer.\n
bits : 4 - 6 (3 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DAT0STS : DAT0 Pin Status of Current Selected SD Port (Read Only)\nThis bit is the DAT0 pin status of current selected SD port.
bits : 7 - 7 (1 bit)
access : read-only

CDIF0 : SD0 Card Detection Interrupt Flag (Read Only)\nThis bit indicates that SD card 0 is inserted or removed. Only when CDIEN0 (SDH_INTEN[8]) is set to 1, this bit is active.\nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SDHIF0 : SDH 0 Interrupt Flag (Read Only)\nThis bit indicates that SDH card 0 issues an interrupt to host. This interrupt is designed to level sensitive. Before clearing it, turn off SDHIEN0 (SDH_INTEN[10]) first.\nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RTOIF : Response Time-out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).\nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DITOIF : Data Input Time-out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving data (waiting start bit).\nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CDSTS0 : Card Detect Status of SD0 (Read Only)\nThis bit indicates the card detect pin status of SD0, and is used for card detection. When there is a card inserted in or removed from SD0, software should check this bit to confirm if there is really a card insertion or removal.\n
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DAT1STS : DAT1 Pin Status of SD Port (Read Only)\nThis bit indicates the DAT1 pin status of SD port.
bits : 18 - 18 (1 bit)
access : read-only

RESPTK0 : SD Receiving Response Token 0\nSD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set. This field contains response bit 47-16 of the response token.
bits : 0 - 31 (32 bit)
access : read-only

RESPTK1 : SD Receiving Response Token 1\nSD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set. This register contains the bit 15-8 of the response token.
bits : 0 - 7 (8 bit)
access : read-only

BLKLEN : SD BLOCK LENGTH in Byte Unit\nAn 11-bit value specifies the SD transfer byte count of a block. The actual byte count is equal to BLKLEN +1.\nNote: The default SD block length is 512 bytes.
bits : 0 - 10 (11 bit)
access : read-write

TOUT : SD Response/Data-in Time-out Value\nA 24-bit value specifies the time-out count of response and data input. SD host controller will wait the start bit of response or data-in until this value reached. The time period depends on SD engine clock frequency. Do not write a small number into this field, or you may never get response or data due to time-out.\nNote: Filling 0x0 into this field will disable hardware time-out function.
bits : 0 - 23 (24 bit)
access : read-write