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HDIV

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x80 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x40 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

HDIV_DIVIDEND0 (DIVIDEND0)

HDIV_STATUS (STATUS)

HDIV_DIVIDEND1 (DIVIDEND1)

HDIV_DIVISOR1 (DIVISOR1)

HDIV_QUOTIENT1 (QUOTIENT1)

HDIV_REM1 (REM1)

HDIV_DIVISOR0 (DIVISOR0)

HDIV_DIVIDEND2 (DIVIDEND2)

HDIV_DIVISOR2 (DIVISOR2)

HDIV_QUOTIENT2 (QUOTIENT2)

HDIV_REM2 (REM2)

HDIV_QUOTIENT0 (QUOTIENT0)

CRC16_CTL

CRC16_DIN

CRC16_OUT

HDIV_REM0 (REM0)


HDIV_DIVIDEND0 (DIVIDEND0)

Dividend Source Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDIV_DIVIDEND0 HDIV_DIVIDEND0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVIDEND

DIVIDEND : Dividend Source\nThis register is given the dividend of divider before calculation is started.
bits : 0 - 31 (32 bit)
access : read-write


HDIV_STATUS (STATUS)

Divider Status Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HDIV_STATUS HDIV_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVBYZERO

DIVBYZERO : Divisor Zero Warning (Read Only)\nNote: The DIVBYZERO flag is used to indicate divide-by-zero situation and updated whenever HDIV_DIVISOR is written. This bit is read only.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

The divisor is not 0

#1 : 1

The divisor is 0

End of enumeration elements list.


HDIV_DIVIDEND1 (DIVIDEND1)

Dividend Source Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDIV_DIVIDEND1 HDIV_DIVIDEND1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HDIV_DIVISOR1 (DIVISOR1)

Divisor Source Resister
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDIV_DIVISOR1 HDIV_DIVISOR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HDIV_QUOTIENT1 (QUOTIENT1)

Quotient Result Resister
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDIV_QUOTIENT1 HDIV_QUOTIENT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HDIV_REM1 (REM1)

Remainder Result Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDIV_REM1 HDIV_REM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HDIV_DIVISOR0 (DIVISOR0)

Divisor Source Resister
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDIV_DIVISOR0 HDIV_DIVISOR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVISOR

DIVISOR : Divisor Source\nThis register is given the divisor of divider before calculation starts.\nNote: When this register is written, hardware divider will start calculation.
bits : 0 - 15 (16 bit)
access : read-write


HDIV_DIVIDEND2 (DIVIDEND2)

Dividend Source Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDIV_DIVIDEND2 HDIV_DIVIDEND2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HDIV_DIVISOR2 (DIVISOR2)

Divisor Source Resister
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDIV_DIVISOR2 HDIV_DIVISOR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HDIV_QUOTIENT2 (QUOTIENT2)

Quotient Result Resister
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDIV_QUOTIENT2 HDIV_QUOTIENT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HDIV_REM2 (REM2)

Remainder Result Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDIV_REM2 HDIV_REM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HDIV_QUOTIENT0 (QUOTIENT0)

Quotient Result Resister
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDIV_QUOTIENT0 HDIV_QUOTIENT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QUOTIENT

QUOTIENT : Quotient Result\nThis register holds the quotient result of divider after calculation is completed.
bits : 0 - 31 (32 bit)
access : read-write


CRC16_CTL

CRC16 Control Register
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC16_CTL CRC16_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEED CNT BITORD BYTEORD

SEED : CRC Seed Data\nThis register was provided to be the initial value for CRC operation.\nWrite data to this register before CRC operation.\nWrite this register will also clear CRC16 register.
bits : 0 - 15 (16 bit)
access : read-write

CNT : CRC Byte Length
bits : 16 - 25 (10 bit)
access : read-write

BITORD : Bit order\n0: [0:7]\n1: [7:0]
bits : 30 - 30 (1 bit)
access : read-write

BYTEORD : Byte order\n0: Big endian\n1: Little endian
bits : 31 - 31 (1 bit)
access : read-write


CRC16_DIN

CRC16 Data in Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC16_DIN CRC16_DIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIN

DIN : CRC Data in\nThis register was provided to be the initial value for CRC operation.\nWrite data to this register before CRC operation.\nRead data from this register after CRC read operation.
bits : 0 - 31 (32 bit)
access : read-write


CRC16_OUT

CRC16 Result Value Register
address_offset : 0x88 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CRC16_OUT CRC16_OUT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT

RESULT : CRC Result Value\nThis register provided current value of CRC durning calculation.
bits : 0 - 15 (16 bit)
access : read-only


HDIV_REM0 (REM0)

Remainder Result Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDIV_REM0 HDIV_REM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REM

REM : Remainder Result\nThe remainder of hardware divider is 16-bit sign integer (REM[15:0]) with sign extension (REM[31:16]) to 32-bit integer.
bits : 0 - 31 (32 bit)
access : read-write



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