\n

ACMP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ACMP_CTL0 (CTL0)

ACMP_TRGDLY (TRGDLY)

ACMP_DAC (DAC)

ACMP_CTL1 (CTL1)

ACMP_STATUS (STATUS)

ACMP_VREF (VREF)


ACMP_CTL0 (CTL0)

Analog Comparator0 Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACMP_CTL0 ACMP_CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACMPEN ACMPIE ACMPHYSEN EDGESEL PBRKSEL DLYTRGSEL DLYTRGSOR DLYTRGEN DLYTRGIE DLYEDGESEL POLARITY NFCLKS NFDIS CPNSEL CPPSEL PRESET

ACMPEN : Comparator Enable Control\nNote: Comparator output needs to wait 2 us stable time after ACMPEN is set.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Comparator Disabled

#1 : 1

Comparator Enabled

End of enumeration elements list.

ACMPIE : Comparator Interrupt Enable Control\nNote1: Interrupt is generated if ACMPIE bit is set to '1' after ACMP conversion is finished.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

ACMP interrupt function Disabled

#1 : 1

ACMP interrupt function Enabled

End of enumeration elements list.

ACMPHYSEN : Comparator0 Hysteresis Enable Control
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

ACMP0 Hysteresis function Disabled (Default)

#01 : 1

ACMP0 Hysteresis function at comparator0 that the typical range is 10mV

#10 : 2

ACMP0 Hysteresis function at comparator0 that the typical range is 90mV

#11 : 3

ACMP0 Hysteresis function at comparator0 that the typical range is 150mV

End of enumeration elements list.

EDGESEL : Interrupt Flag Trigger Edge Detection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

Interrupt Flag Trigger Edge Disabled

#01 : 1

Rising

#10 : 2

Falling

#11 : 3

Rising/Falling

End of enumeration elements list.

PBRKSEL : ACMP to EPWM Brake Selection
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

ACMP Result direct output

#1 : 1

ACMP Delay Trigger Result output

End of enumeration elements list.

DLYTRGSEL : Analog Comparator Delay Trigger Mode Trigger Level Selection
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 0

Analog Comparator Delay Trigger Mode Trigger Disabled

#01 : 1

Rising

#10 : 2

Falling

#11 : 3

Rising/Falling

End of enumeration elements list.

DLYTRGSOR : Analog Comparator Delay Trigger Mode Trigger Source Selection
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 0

EPWM_CH0

#01 : 1

EPWM_CH2

#10 : 2

EPWM_CH4

#11 : 3

TMR3_MATCH

End of enumeration elements list.

DLYTRGEN : Analog Comparator Delay Trigger Mode Enable Control
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Analog Comparator Delay Trigger Mode Disabled

#1 : 1

Analog Comparator Delay Trigger Mode Enabled

End of enumeration elements list.

DLYTRGIE : Analog Comparator Delay Trigger Mode Interrupt Enable Control
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Analog Comparator Delay Trigger Mode Interrupt Disabled

#1 : 1

Analog Comparator Delay Trigger Mode Interrupt Enabled

End of enumeration elements list.

DLYEDGESEL : PWM Delay Trigger Interrupt Flag Trigger Edge Detection
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 0

Interrupt Flag Trigger Edge Disabled

#01 : 1

Rising

#10 : 2

Falling

#11 : 3

Rising/Falling

End of enumeration elements list.

POLARITY : Analog Comparator Polarity Control
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Analog Comparator normal output

#1 : 1

Analog Comparator invert output

End of enumeration elements list.

NFCLKS : Noise Filter Clock Pre-divided Selection\nTo determine the sampling frequency of the Noise Filter clock
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#000 : 0

PCLK.\nPCLK/ 16

#001 : 1

PCLK / 2.\nPCLK / 32

#010 : 2

PCLK / 4.\nPCLK / 64

#011 : 3

PCLK / 8.\nPCLK / 256

End of enumeration elements list.

NFDIS : Disable Comparator Noise Filter
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Noise filter Enabled

#1 : 1

Noise filter Disabled

End of enumeration elements list.

CPNSEL : Comparator Negative Input Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

ACMP0_N (PB.4)

#01 : 1

Band_Gap

#10 : 2

CRV(DAC2)

#11 : 3

DAC0

End of enumeration elements list.

CPPSEL : Comparator Positive Input Select
bits : 28 - 30 (3 bit)
access : read-write

Enumeration:

#000 : 0

ACMP0_P0 (PB.0)

#001 : 1

ACMP0_P1 (PB.1)

#010 : 2

ACMP0_P2 (PB.2)

#011 : 3

ACMP0_P3 (PC.1)

#100 : 4

PGA_CMP

End of enumeration elements list.

PRESET : Comparator Result Preset Value
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

0 for ACMP0 preset value

#1 : 1

1 for ACMP0 preset value

End of enumeration elements list.


ACMP_TRGDLY (TRGDLY)

Analog Comparator Delay Trigger Mode Dleay Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACMP_TRGDLY ACMP_TRGDLY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DELAY

DELAY : Analog Comparator Delay Trigger Mode Dleay cycle(PCLK*cycle)
bits : 0 - 8 (9 bit)
access : read-write


ACMP_DAC (DAC)

DAC Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACMP_DAC ACMP_DAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC0 DAC1

DAC0 : None
bits : 4 - 15 (12 bit)
access : read-write

DAC1 : None
bits : 20 - 31 (12 bit)
access : read-write


ACMP_CTL1 (CTL1)

Analog Comparator1 Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACMP_CTL1 ACMP_CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACMPEN ACMPIE ACMPHYSEN EDGESEL PBRKSEL DLYTRGSEL DLYTRGSOR DLYTRGEN DLYTRGIE DLYEDGESEL POLARITY NFCLKS NFDIS CPNSEL CPPSEL PRESET

ACMPEN : Comparator Enable Control\nNote: Comparator output needs to wait 2 us stable time after ACMPEN is set.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Comparator Disabled

#1 : 1

Comparator Enabled

End of enumeration elements list.

ACMPIE : Comparator Interrupt Enable Control\nNote1: Interrupt is generated if ACMPIE bit is set to '1' after ACMP conversion is finished.\nNote2: ACMP interrupt will wake CPU up in Power-down mode.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

ACMP interrupt function Disabled

#1 : 1

ACMP interrupt function Enabled

End of enumeration elements list.

ACMPHYSEN : Comparator1 Hysteresis Enable Control
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

ACMP0 Hysteresis function Disabled (Default)

#01 : 1

ACMP0 Hysteresis function at comparator1 that the typical range is 10mV

#10 : 2

ACMP0 Hysteresis function at comparator1 that the typical range is 90mV

#11 : 3

ACMP0 Hysteresis function at comparator1 that the typical range is 150mV

End of enumeration elements list.

EDGESEL : Interrupt Flag Trigger Edge Detection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

Interrupt Flag Trigger Edge Detection Disable

#01 : 1

Rising

#10 : 2

Falling

#11 : 3

Rising/Falling

End of enumeration elements list.

PBRKSEL : ACMP to EPWM Brake Selection
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

ACMP Result direct output

#1 : 1

ACMP Delay Trigger Result output

End of enumeration elements list.

DLYTRGSEL : Analog Comparator Delay Trigger Mode Trigger Level Selection
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 0

Analog Comparator Delay Trigger Mode Trigger Disabled

#01 : 1

Rising

#10 : 2

Falling

#11 : 3

Rising/Falling

End of enumeration elements list.

DLYTRGSOR : Analog Comparator Delay Trigger Mode Trigger Source Selection
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 0

EPWM_CH0

#01 : 1

EPWM_CH2

#10 : 2

EPWM_CH4

#11 : 3

TMR4_MATCH

End of enumeration elements list.

DLYTRGEN : Analog Comparator Delay Trigger Mode Enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Analog Comparator Delay Trigger Mode Disabled

#1 : 1

Analog Comparator Delay Trigger Mode Enabled

End of enumeration elements list.

DLYTRGIE : Analog Comparator Delay Trigger Mode Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Analog Comparator Delay Trigger Mode Interrupt Disabled

#1 : 1

Analog Comparator Delay Trigger Mode Interrupt Enabled

End of enumeration elements list.

DLYEDGESEL : Interrupt Delay Trigger Flag Trigger Edge Detection
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 0

Interrupt Flag Trigger Edge Detection Disable

#01 : 1

Rising

#10 : 2

Falling

#11 : 3

Rising/Falling

End of enumeration elements list.

POLARITY : Analog Comparator Polarity Control
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Analog Comparator normal output

#1 : 1

Analog Comparator invert output

End of enumeration elements list.

NFCLKS : Noise Filter Clock Pre-divided Selection\nTo determine the sampling frequency of the Noise Filter clock
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#000 : 0

PCLK.\nPCLK/ 16

#001 : 1

PCLK / 2.\nPCLK / 32

#010 : 2

PCLK / 4.\nPCLK / 64

#011 : 3

PCLK / 8.\nPCLK / 256

End of enumeration elements list.

NFDIS : Disable Comparator Noise Filter
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Noise filter Enable

#1 : 1

Noise filter Disable

End of enumeration elements list.

CPNSEL : Comparator Negative Input Selection
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

ACMP1_N (PB.3)

#01 : 1

Band_Gap

#10 : 2

CRV(DAC2)

#11 : 3

DAC1

End of enumeration elements list.

CPPSEL : Comparator Positive Input Selection
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

#00 : 0

ACMP1_P0 (PC.0)

#01 : 1

ACMP1_P1 (PC.1)

#10 : 2

ACMP1_P2 (PD.1)

#11 : 3

PGA_CMP

End of enumeration elements list.

PRESET : Comparator Result Preset Value
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

0 for ACMP1 preset value

#1 : 1

1 for ACMP1 preset value

End of enumeration elements list.


ACMP_STATUS (STATUS)

Analog Comparator Status Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACMP_STATUS ACMP_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACMPF0 ACMPF1 ACMPO0 ACMPO1 DLYTRGF0 DLYTRGF1 DLYTRGO0 DLYTRGO1

ACMPF0 : Comparator0 Flag\nThis bit is set by hardware whenever the comparator0 output changes state. This will cause an interrupt if ACMPIE set.\nWrite '1' to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

ACMPF1 : Comparator1 Flag\nThis bit is set by hardware whenever the comparator1 output changes state. This will cause an interrupt if ACMPIE set.\nWrite '1' to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

ACMPO0 : Comparator0 Output
bits : 2 - 2 (1 bit)
access : read-write

ACMPO1 : Comparator1 Output
bits : 3 - 3 (1 bit)
access : read-write

DLYTRGF0 : Comparator0 Flag\nThis bit is set by hardware whenever the comparator0 output changes state. This will cause an interrupt if DLYTRGIEN set.\nWrite '1' to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

DLYTRGF1 : Comparator1 Flag\nThis bit is set by hardware whenever the comparator1 output changes state. This will cause an interrupt if DLYTRGIEN set.\nWrite '1' to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write

DLYTRGO0 : Analog Comparator0 Delay Trigger Mode Comparator Output
bits : 6 - 6 (1 bit)
access : read-write

DLYTRGO1 : Analog Comparator1 Delay Trigger Mode Comparator Output
bits : 7 - 7 (1 bit)
access : read-write


ACMP_VREF (VREF)

Analog Comparator Reference Voltage Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACMP_VREF ACMP_VREF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRVCTL DAC2 DACMODE

CRVCTL : Comparator Reference Voltage Setting
bits : 0 - 3 (4 bit)
access : read-write

DAC2 : None
bits : 4 - 15 (12 bit)
access : read-write

DACMODE : When DAC mode enable, CRV will follow setting value of DAC2.
bits : 31 - 31 (1 bit)
access : read-write



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