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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CSR

CCR

CDR


CSR

ADC Common status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD1 EOC1 JEOC1 JSTRT1 STRT1 OVR1 AWD2 EOC2 JEOC2 JSTRT2 STRT2 OVR2 AWD3 EOC3 JEOC3 JSTRT3 STRT3 OVR3

AWD1 : Analog watchdog flag of ADC 1
bits : 0 - 0 (1 bit)

EOC1 : End of conversion of ADC 1
bits : 1 - 1 (1 bit)

JEOC1 : Injected channel end of conversion of ADC 1
bits : 2 - 2 (1 bit)

JSTRT1 : Injected channel Start flag of ADC 1
bits : 3 - 3 (1 bit)

STRT1 : Regular channel Start flag of ADC 1
bits : 4 - 4 (1 bit)

OVR1 : Overrun flag of ADC 1
bits : 5 - 5 (1 bit)

AWD2 : Analog watchdog flag of ADC 2
bits : 8 - 8 (1 bit)

EOC2 : End of conversion of ADC 2
bits : 9 - 9 (1 bit)

JEOC2 : Injected channel end of conversion of ADC 2
bits : 10 - 10 (1 bit)

JSTRT2 : Injected channel Start flag of ADC 2
bits : 11 - 11 (1 bit)

STRT2 : Regular channel Start flag of ADC 2
bits : 12 - 12 (1 bit)

OVR2 : Overrun flag of ADC 2
bits : 13 - 13 (1 bit)

AWD3 : Analog watchdog flag of ADC 3
bits : 16 - 16 (1 bit)

EOC3 : End of conversion of ADC 3
bits : 17 - 17 (1 bit)

JEOC3 : Injected channel end of conversion of ADC 3
bits : 18 - 18 (1 bit)

JSTRT3 : Injected channel Start flag of ADC 3
bits : 19 - 19 (1 bit)

STRT3 : Regular channel Start flag of ADC 3
bits : 20 - 20 (1 bit)

OVR3 : Overrun flag of ADC3
bits : 21 - 21 (1 bit)


CCR

ADC common control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MULT DELAY DDS DMA ADCPRE VBATE TSVREFE

MULT : Multi ADC mode selection
bits : 0 - 4 (5 bit)

DELAY : Delay between 2 sampling phases
bits : 8 - 11 (4 bit)

DDS : DMA disable selection for multi-ADC mode
bits : 13 - 13 (1 bit)

DMA : Direct memory access mode for multi ADC mode
bits : 14 - 15 (2 bit)

ADCPRE : ADC prescaler
bits : 16 - 17 (2 bit)

VBATE : VBAT enable
bits : 22 - 22 (1 bit)

TSVREFE : Temperature sensor and VREFINT enable
bits : 23 - 23 (1 bit)


CDR

ADC common regular data register for dual and triple modes
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR CDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA1 DATA2

DATA1 : 1st data item of a pair of regular conversions
bits : 0 - 15 (16 bit)

DATA2 : 2nd data item of a pair of regular conversions
bits : 16 - 31 (16 bit)



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