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DMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ISR

CPAR1

CM0AR1

CM1AR1

CCR2

CNDTR2

CPAR2

CM0AR2

CM1AR2

CCR3

CNDTR3

CPAR3

CM0AR3

IFCR

CM1AR3

CCR4

CNDTR4

CPAR4

CM0AR4

CM1AR4

CCR5

CNDTR5

CPAR5

CM0AR5

CM1AR5

CCR6

CNDTR6

CPAR6

CM0AR6

CM1AR6

CCR1

CCR7

CNDTR7

CPAR7

CM0AR7

CM1AR7

CCR8

CNDTR8

CPAR8

CM0AR8

CM1AR8

CSELR

CNDTR1


ISR

interrupt status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GIF1 TCIF1 HTIF1 TEIF1 GIF2 TCIF2 HTIF2 TEIF2 GIF3 TCIF3 HTIF3 TEIF3 GIF4 TCIF4 HTIF4 TEIF4 GIF5 TCIF5 HTIF5 TEIF5 GIF6 TCIF6 HTIF6 TEIF6 GIF7 TCIF7 HTIF7 TEIF7 GIF8 TCIF8 HTIF8 TEIF8

GIF1 : Channel x global interrupt flag (x = 1 ..7)
bits : 0 - 0 (1 bit)

TCIF1 : Channel x transfer complete flag (x = 1 ..7)
bits : 1 - 1 (1 bit)

HTIF1 : Channel x half transfer flag (x = 1 ..7)
bits : 2 - 2 (1 bit)

TEIF1 : Channel x transfer error flag (x = 1 ..7)
bits : 3 - 3 (1 bit)

GIF2 : Channel x global interrupt flag (x = 1 ..7)
bits : 4 - 4 (1 bit)

TCIF2 : Channel x transfer complete flag (x = 1 ..7)
bits : 5 - 5 (1 bit)

HTIF2 : Channel x half transfer flag (x = 1 ..7)
bits : 6 - 6 (1 bit)

TEIF2 : Channel x transfer error flag (x = 1 ..7)
bits : 7 - 7 (1 bit)

GIF3 : Channel x global interrupt flag (x = 1 ..7)
bits : 8 - 8 (1 bit)

TCIF3 : Channel x transfer complete flag (x = 1 ..7)
bits : 9 - 9 (1 bit)

HTIF3 : Channel x half transfer flag (x = 1 ..7)
bits : 10 - 10 (1 bit)

TEIF3 : Channel x transfer error flag (x = 1 ..7)
bits : 11 - 11 (1 bit)

GIF4 : Channel x global interrupt flag (x = 1 ..7)
bits : 12 - 12 (1 bit)

TCIF4 : Channel x transfer complete flag (x = 1 ..7)
bits : 13 - 13 (1 bit)

HTIF4 : Channel x half transfer flag (x = 1 ..7)
bits : 14 - 14 (1 bit)

TEIF4 : Channel x transfer error flag (x = 1 ..7)
bits : 15 - 15 (1 bit)

GIF5 : Channel x global interrupt flag (x = 1 ..7)
bits : 16 - 16 (1 bit)

TCIF5 : Channel x transfer complete flag (x = 1 ..7)
bits : 17 - 17 (1 bit)

HTIF5 : Channel x half transfer flag (x = 1 ..7)
bits : 18 - 18 (1 bit)

TEIF5 : Channel x transfer error flag (x = 1 ..7)
bits : 19 - 19 (1 bit)

GIF6 : Channel x global interrupt flag (x = 1 ..7)
bits : 20 - 20 (1 bit)

TCIF6 : Channel x transfer complete flag (x = 1 ..7)
bits : 21 - 21 (1 bit)

HTIF6 : Channel x half transfer flag (x = 1 ..7)
bits : 22 - 22 (1 bit)

TEIF6 : Channel x transfer error flag (x = 1 ..7)
bits : 23 - 23 (1 bit)

GIF7 : Channel x global interrupt flag (x = 1 ..7)
bits : 24 - 24 (1 bit)

TCIF7 : Channel x transfer complete flag (x = 1 ..7)
bits : 25 - 25 (1 bit)

HTIF7 : Channel x half transfer flag (x = 1 ..7)
bits : 26 - 26 (1 bit)

TEIF7 : Channel x transfer error flag (x = 1 ..7)
bits : 27 - 27 (1 bit)

GIF8 : global interrupt flag for channel 8
bits : 28 - 28 (1 bit)

TCIF8 : transfer complete (TC) flag for channel 8
bits : 29 - 29 (1 bit)

HTIF8 : half transfer (HT) flag for channel 8
bits : 30 - 30 (1 bit)

TEIF8 : transfer error (TE) flag for channel 8
bits : 31 - 31 (1 bit)


CPAR1

channel x peripheral address register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR1 CPAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CM0AR1

channel x memory address register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CM0AR1 CM0AR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


CM1AR1

channel x memory address register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CM1AR1 CM1AR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM DBM CT SECM SSEC DSEC PRIV

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)

DBM : double-buffer mode
bits : 15 - 15 (1 bit)

CT : current target memory of DMA transfer in double-buffer mode
bits : 16 - 16 (1 bit)

SECM : secure mode
bits : 17 - 17 (1 bit)

SSEC : security of the DMA transfer from the source
bits : 18 - 18 (1 bit)

DSEC : security of the DMA transfer to the destination
bits : 19 - 19 (1 bit)

PRIV : privileged mode
bits : 20 - 20 (1 bit)


CCR2

channel x configuration register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR2 CCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 17 (18 bit)


CNDTR2

channel x number of data register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR2 CNDTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CPAR2

channel x peripheral address register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR2 CPAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


CM0AR2

channel x memory address register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CM0AR2 CM0AR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM DBM CT SECM SSEC DSEC PRIV

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)

DBM : double-buffer mode
bits : 15 - 15 (1 bit)

CT : current target memory of DMA transfer in double-buffer mode
bits : 16 - 16 (1 bit)

SECM : secure mode
bits : 17 - 17 (1 bit)

SSEC : security of the DMA transfer from the source
bits : 18 - 18 (1 bit)

DSEC : security of the DMA transfer to the destination
bits : 19 - 19 (1 bit)

PRIV : privileged mode
bits : 20 - 20 (1 bit)


CM1AR2

channel x memory address register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CM1AR2 CM1AR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 17 (18 bit)


CCR3

channel x configuration register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR3 CCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CNDTR3

channel x number of data register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR3 CNDTR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


CPAR3

channel x peripheral address register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR3 CPAR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM DBM CT SECM SSEC DSEC PRIV

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)

DBM : double-buffer mode
bits : 15 - 15 (1 bit)

CT : current target memory of DMA transfer in double-buffer mode
bits : 16 - 16 (1 bit)

SECM : secure mode
bits : 17 - 17 (1 bit)

SSEC : security of the DMA transfer from the source
bits : 18 - 18 (1 bit)

DSEC : security of the DMA transfer to the destination
bits : 19 - 19 (1 bit)

PRIV : privileged mode
bits : 20 - 20 (1 bit)


CM0AR3

channel x memory address register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CM0AR3 CM0AR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 17 (18 bit)


IFCR

interrupt flag clear register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFCR IFCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CGIF1 CTCIF1 CHTIF1 CTEIF1 CGIF2 CTCIF2 CHTIF2 CTEIF2 CGIF3 CTCIF3 CHTIF3 CTEIF3 CGIF4 CTCIF4 CHTIF4 CTEIF4 CGIF5 CTCIF5 CHTIF5 CTEIF5 CGIF6 CTCIF6 CHTIF6 CTEIF6 CGIF7 CTCIF7 CHTIF7 CTEIF7 CGIF8 CTCIF8 CHTIF8 CTEIF8

CGIF1 : Channel x global interrupt clear (x = 1 ..7)
bits : 0 - 0 (1 bit)

CTCIF1 : Channel x transfer complete clear (x = 1 ..7)
bits : 1 - 1 (1 bit)

CHTIF1 : Channel x half transfer clear (x = 1 ..7)
bits : 2 - 2 (1 bit)

CTEIF1 : Channel x transfer error clear (x = 1 ..7)
bits : 3 - 3 (1 bit)

CGIF2 : Channel x global interrupt clear (x = 1 ..7)
bits : 4 - 4 (1 bit)

CTCIF2 : Channel x transfer complete clear (x = 1 ..7)
bits : 5 - 5 (1 bit)

CHTIF2 : Channel x half transfer clear (x = 1 ..7)
bits : 6 - 6 (1 bit)

CTEIF2 : Channel x transfer error clear (x = 1 ..7)
bits : 7 - 7 (1 bit)

CGIF3 : Channel x global interrupt clear (x = 1 ..7)
bits : 8 - 8 (1 bit)

CTCIF3 : Channel x transfer complete clear (x = 1 ..7)
bits : 9 - 9 (1 bit)

CHTIF3 : Channel x half transfer clear (x = 1 ..7)
bits : 10 - 10 (1 bit)

CTEIF3 : Channel x transfer error clear (x = 1 ..7)
bits : 11 - 11 (1 bit)

CGIF4 : Channel x global interrupt clear (x = 1 ..7)
bits : 12 - 12 (1 bit)

CTCIF4 : Channel x transfer complete clear (x = 1 ..7)
bits : 13 - 13 (1 bit)

CHTIF4 : Channel x half transfer clear (x = 1 ..7)
bits : 14 - 14 (1 bit)

CTEIF4 : Channel x transfer error clear (x = 1 ..7)
bits : 15 - 15 (1 bit)

CGIF5 : Channel x global interrupt clear (x = 1 ..7)
bits : 16 - 16 (1 bit)

CTCIF5 : Channel x transfer complete clear (x = 1 ..7)
bits : 17 - 17 (1 bit)

CHTIF5 : Channel x half transfer clear (x = 1 ..7)
bits : 18 - 18 (1 bit)

CTEIF5 : Channel x transfer error clear (x = 1 ..7)
bits : 19 - 19 (1 bit)

CGIF6 : Channel x global interrupt clear (x = 1 ..7)
bits : 20 - 20 (1 bit)

CTCIF6 : Channel x transfer complete clear (x = 1 ..7)
bits : 21 - 21 (1 bit)

CHTIF6 : Channel x half transfer clear (x = 1 ..7)
bits : 22 - 22 (1 bit)

CTEIF6 : Channel x transfer error clear (x = 1 ..7)
bits : 23 - 23 (1 bit)

CGIF7 : Channel x global interrupt clear (x = 1 ..7)
bits : 24 - 24 (1 bit)

CTCIF7 : Channel x transfer complete clear (x = 1 ..7)
bits : 25 - 25 (1 bit)

CHTIF7 : Channel x half transfer clear (x = 1 ..7)
bits : 26 - 26 (1 bit)

CTEIF7 : Channel x transfer error clear (x = 1 ..7)
bits : 27 - 27 (1 bit)

CGIF8 : global interrupt flag clear for channel 8
bits : 28 - 28 (1 bit)

CTCIF8 : transfer complete flag clear for channel 8
bits : 29 - 29 (1 bit)

CHTIF8 : half transfer flag clear for channel 8
bits : 30 - 30 (1 bit)

CTEIF8 : transfer error flag clear for channel 8
bits : 31 - 31 (1 bit)


CM1AR3

channel x memory address register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CM1AR3 CM1AR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CCR4

channel x configuration register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR4 CCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


CNDTR4

channel x number of data register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR4 CNDTR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM DBM CT SECM SSEC DSEC PRIV

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)

DBM : double-buffer mode
bits : 15 - 15 (1 bit)

CT : current target memory of DMA transfer in double-buffer mode
bits : 16 - 16 (1 bit)

SECM : secure mode
bits : 17 - 17 (1 bit)

SSEC : security of the DMA transfer from the source
bits : 18 - 18 (1 bit)

DSEC : security of the DMA transfer to the destination
bits : 19 - 19 (1 bit)

PRIV : privileged mode
bits : 20 - 20 (1 bit)


CPAR4

channel x peripheral address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR4 CPAR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 17 (18 bit)


CM0AR4

channel x memory address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CM0AR4 CM0AR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CM1AR4

channel x memory address register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CM1AR4 CM1AR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


CCR5

channel x configuration register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR5 CCR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM DBM CT SECM SSEC DSEC PRIV

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)

DBM : double-buffer mode
bits : 15 - 15 (1 bit)

CT : current target memory of DMA transfer in double-buffer mode
bits : 16 - 16 (1 bit)

SECM : secure mode
bits : 17 - 17 (1 bit)

SSEC : security of the DMA transfer from the source
bits : 18 - 18 (1 bit)

DSEC : security of the DMA transfer to the destination
bits : 19 - 19 (1 bit)

PRIV : privileged mode
bits : 20 - 20 (1 bit)


CNDTR5

channel x number of data register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR5 CNDTR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 17 (18 bit)


CPAR5

channel x peripheral address register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR5 CPAR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CM0AR5

channel x memory address register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CM0AR5 CM0AR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


CM1AR5

channel x memory address register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CM1AR5 CM1AR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM DBM CT SECM SSEC DSEC PRIV

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)

DBM : double-buffer mode
bits : 15 - 15 (1 bit)

CT : current target memory of DMA transfer in double-buffer mode
bits : 16 - 16 (1 bit)

SECM : secure mode
bits : 17 - 17 (1 bit)

SSEC : security of the DMA transfer from the source
bits : 18 - 18 (1 bit)

DSEC : security of the DMA transfer to the destination
bits : 19 - 19 (1 bit)

PRIV : privileged mode
bits : 20 - 20 (1 bit)


CCR6

channel x configuration register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR6 CCR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 17 (18 bit)


CNDTR6

channel x number of data register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR6 CNDTR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CPAR6

channel x peripheral address register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR6 CPAR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


CM0AR6

channel x memory address register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CM0AR6 CM0AR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C1S C2S C3S C4S C5S C6S C7S

C1S : DMA channel 1 selection
bits : 0 - 3 (4 bit)

C2S : DMA channel 2 selection
bits : 4 - 7 (4 bit)

C3S : DMA channel 3 selection
bits : 8 - 11 (4 bit)

C4S : DMA channel 4 selection
bits : 12 - 15 (4 bit)

C5S : DMA channel 5 selection
bits : 16 - 19 (4 bit)

C6S : DMA channel 6 selection
bits : 20 - 23 (4 bit)

C7S : DMA channel 7 selection
bits : 24 - 27 (4 bit)


CM1AR6

channel x memory address register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CM1AR6 CM1AR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : peripheral address
bits : 0 - 31 (32 bit)


CCR1

channel x configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR1 CCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM DBM CT SECM SSEC DSEC PRIV

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)

DBM : double-buffer mode
bits : 15 - 15 (1 bit)

CT : current target memory of DMA transfer in double-buffer mode
bits : 16 - 16 (1 bit)

SECM : secure mode
bits : 17 - 17 (1 bit)

SSEC : security of the DMA transfer from the source
bits : 18 - 18 (1 bit)

DSEC : security of the DMA transfer to the destination
bits : 19 - 19 (1 bit)

PRIV : privileged mode
bits : 20 - 20 (1 bit)


CCR7

channel x configuration register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR7 CCR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : peripheral address
bits : 0 - 31 (32 bit)


CNDTR7

channel x number of data register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR7 CNDTR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : peripheral address
bits : 0 - 31 (32 bit)


CPAR7

channel x peripheral address register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR7 CPAR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : peripheral address
bits : 0 - 31 (32 bit)


CM0AR7

channel x memory address register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CM0AR7 CM0AR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : peripheral address
bits : 0 - 31 (32 bit)


CM1AR7

channel x memory address register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CM1AR7 CM1AR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : peripheral address
bits : 0 - 31 (32 bit)


CCR8

channel x configuration register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR8 CCR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : peripheral address
bits : 0 - 31 (32 bit)


CNDTR8

channel x number of data register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR8 CNDTR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM DBM CT SECM SSEC DSEC PRIV

EN : channel enable
bits : 0 - 0 (1 bit)

TCIE : transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : half transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : data transfer direction
bits : 4 - 4 (1 bit)

CIRC : circular mode
bits : 5 - 5 (1 bit)

PINC : peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : peripheral size
bits : 8 - 9 (2 bit)

MSIZE : memory size
bits : 10 - 11 (2 bit)

PL : priority level
bits : 12 - 13 (2 bit)

MEM2MEM : memory-to-memory mode
bits : 14 - 14 (1 bit)

DBM : double-buffer mode
bits : 15 - 15 (1 bit)

CT : current target memory of DMA transfer in double-buffer mode
bits : 16 - 16 (1 bit)

SECM : secure mode
bits : 17 - 17 (1 bit)

SSEC : security of the DMA transfer from the source
bits : 18 - 18 (1 bit)

DSEC : security of the DMA transfer to the destination
bits : 19 - 19 (1 bit)

PRIV : privileged mode
bits : 20 - 20 (1 bit)


CPAR8

channel x peripheral address register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR8 CPAR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : number of data to transfer
bits : 0 - 17 (18 bit)


CM0AR8

channel x peripheral address register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CM0AR8 CM0AR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : peripheral address
bits : 0 - 31 (32 bit)


CM1AR8

channel x peripheral address register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CM1AR8 CM1AR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : peripheral address
bits : 0 - 31 (32 bit)


CSELR

channel selection register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSELR CSELR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : peripheral address
bits : 0 - 31 (32 bit)


CNDTR1

channel x number of data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR1 CNDTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 17 (18 bit)



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