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TIM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x3851 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TIM1_ISR (ISR)

TIM1_MISSR (MISSR)

TIM1_CR1 (CR1)

TIM1_CR2 (CR2)

TIM1_SMCR (SMCR)

TIM1_EGR (EGR)

TIM1_CCMR1_Input (CCMR1_Input)

TIM1_CCMR1_Output (CCMR1_Output)

TIM1_CCMR2_Input (CCMR2_Input)

TIM1_CCMR2_Output (CCMR2_Output)

TIM1_CCER (CCER)

TIM1_CNT (CNT)

TIM1_PSC (PSC)

TIM1_ARR (ARR)

TIM1_CCR1 (CCR1)

TIM1_CCR2 (CCR2)

TIM1_CCR3 (CCR3)

TIM1_CCR4 (CCR4)

TIM1_OR (OR)

TIM1_IER (IER)


TIM1_ISR (ISR)

TIM Interrupt Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM1_ISR TIM1_ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIF CC1IF CC2IF CC3IF CC4IF TIF RSVD

UIF : UIF
bits : 0 - 0 (1 bit)
access : read-write

CC1IF : CC1IF
bits : 1 - 1 (1 bit)
access : read-write

CC2IF : CC2IF
bits : 2 - 2 (1 bit)
access : read-write

CC3IF : CC3IF
bits : 3 - 3 (1 bit)
access : read-write

CC4IF : CC4IF
bits : 4 - 4 (1 bit)
access : read-write

TIF : TIF
bits : 6 - 6 (1 bit)
access : read-write

RSVD : RSVD
bits : 8 - 12 (5 bit)
access : read-only


TIM1_MISSR (MISSR)

TIM interrupt missed register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM1_MISSR TIM1_MISSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD CC1IM CC2IM CC3IM CC4IM

RSVD : RSVD
bits : 0 - 6 (7 bit)
access : read-only

CC1IM : CC1IM
bits : 9 - 9 (1 bit)
access : read-write

CC2IM : CC2IM
bits : 10 - 10 (1 bit)
access : read-write

CC3IM : CC3IM
bits : 11 - 11 (1 bit)
access : read-write

CC4IM : CC4IM
bits : 12 - 12 (1 bit)
access : read-write


TIM1_CR1 (CR1)

control register 1
address_offset : 0x3800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM1_CR1 TIM1_CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN UDIS URS OPM DIR CMS ARBE

CEN : CEN
bits : 0 - 0 (1 bit)

UDIS : UDIS
bits : 1 - 1 (1 bit)

URS : URS
bits : 2 - 2 (1 bit)

OPM : OPM
bits : 3 - 3 (1 bit)

DIR : DIR
bits : 4 - 4 (1 bit)

CMS : CMS
bits : 5 - 6 (2 bit)

ARBE : ARBE
bits : 7 - 7 (1 bit)


TIM1_CR2 (CR2)

control register 2
address_offset : 0x3804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM1_CR2 TIM1_CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMS TI1S

MMS : MMS
bits : 4 - 6 (3 bit)

TI1S : TI1S
bits : 7 - 7 (1 bit)


TIM1_SMCR (SMCR)

slave Mode Control register
address_offset : 0x3808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM1_SMCR TIM1_SMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMS TS MSM ETF ETPS ECE ETP

SMS : SMS
bits : 0 - 2 (3 bit)

TS : TS
bits : 4 - 6 (3 bit)

MSM : MSM
bits : 7 - 7 (1 bit)

ETF : ETF
bits : 8 - 11 (4 bit)

ETPS : ETPS
bits : 12 - 13 (2 bit)

ECE : ECE
bits : 14 - 14 (1 bit)

ETP : ETP
bits : 15 - 15 (1 bit)


TIM1_EGR (EGR)

TIM event generation register
address_offset : 0x3814 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TIM1_EGR TIM1_EGR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UG CC1G CC2G CC3G CC4G TG

UG : UG
bits : 0 - 0 (1 bit)

CC1G : CC1G
bits : 1 - 1 (1 bit)

CC2G : CC2G
bits : 2 - 2 (1 bit)

CC3G : CC3G
bits : 3 - 3 (1 bit)

CC4G : CC4G
bits : 4 - 4 (1 bit)

TG : TG
bits : 6 - 6 (1 bit)


TIM1_CCMR1_Input (CCMR1_Input)

capture/compare mode register 1 (Input mode)
address_offset : 0x3818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM1_CCMR1_Input TIM1_CCMR1_Input read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1S IC1PSC IC1F CC2S IC2PSC IC2F

CC1S : CC1S
bits : 0 - 1 (2 bit)

IC1PSC : IC1PSC
bits : 2 - 3 (2 bit)

IC1F : IC1F
bits : 4 - 7 (4 bit)

CC2S : CC2S
bits : 8 - 9 (2 bit)

IC2PSC : IC2PSC
bits : 10 - 11 (2 bit)

IC2F : IC2F
bits : 12 - 15 (4 bit)


TIM1_CCMR1_Output (CCMR1_Output)

capture/compare mode register 1 (output mode)
address_offset : 0x3818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TIM1_CCMR1_Input
reset_Mask : 0x0

TIM1_CCMR1_Output TIM1_CCMR1_Output read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1S OC1FE OC1PE OC1M CC2S OC2FE OC2PE OC2M

CC1S : CC1S
bits : 0 - 1 (2 bit)

OC1FE : OC1FE
bits : 2 - 2 (1 bit)

OC1PE : OC1PE
bits : 3 - 3 (1 bit)

OC1M : OC1M
bits : 4 - 6 (3 bit)

CC2S : CC2S
bits : 8 - 9 (2 bit)

OC2FE : OC2FE
bits : 10 - 10 (1 bit)

OC2PE : OC2PE
bits : 11 - 11 (1 bit)

OC2M : OC2M
bits : 12 - 14 (3 bit)


TIM1_CCMR2_Input (CCMR2_Input)

capture/compare mode register 2 (input mode)
address_offset : 0x381C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM1_CCMR2_Input TIM1_CCMR2_Input read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC3S IC3PSC IC3F CC4S IC4PSC IC4F

CC3S : CC3S
bits : 0 - 1 (2 bit)

IC3PSC : IC3PSC
bits : 2 - 3 (2 bit)

IC3F : IC3F
bits : 4 - 7 (4 bit)

CC4S : CC4S
bits : 8 - 9 (2 bit)

IC4PSC : IC4PSC
bits : 10 - 11 (2 bit)

IC4F : IC4F
bits : 12 - 15 (4 bit)


TIM1_CCMR2_Output (CCMR2_Output)

capture/compare mode register 2 (output mode)
address_offset : 0x381C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TIM1_CCMR2_Input
reset_Mask : 0x0

TIM1_CCMR2_Output TIM1_CCMR2_Output read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC3S OC3FE OC3PE OC3M CC4S OC4FE OC4PE OC4M

CC3S : CC3S
bits : 0 - 1 (2 bit)

OC3FE : OC3FE
bits : 2 - 2 (1 bit)

OC3PE : OC3PE
bits : 3 - 3 (1 bit)

OC3M : OC3M
bits : 4 - 6 (3 bit)

CC4S : CC4S
bits : 8 - 9 (2 bit)

OC4FE : OC4FE
bits : 10 - 10 (1 bit)

OC4PE : OC4PE
bits : 11 - 11 (1 bit)

OC4M : OC4M
bits : 12 - 14 (3 bit)


TIM1_CCER (CCER)

TIM capture/compare enable register
address_offset : 0x3820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM1_CCER TIM1_CCER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1E CC1P CC2E CC2P CC3E CC3P CC4E CC4P

CC1E : CC1E
bits : 0 - 0 (1 bit)

CC1P : CC1P
bits : 1 - 1 (1 bit)

CC2E : CC2E
bits : 4 - 4 (1 bit)

CC2P : CC2P
bits : 5 - 5 (1 bit)

CC3E : CC3E
bits : 8 - 8 (1 bit)

CC3P : CC3P
bits : 9 - 9 (1 bit)

CC4E : CC4E
bits : 12 - 12 (1 bit)

CC4P : CC4P
bits : 13 - 13 (1 bit)


TIM1_CNT (CNT)

TIM counter register
address_offset : 0x3824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM1_CNT TIM1_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : CNT
bits : 0 - 15 (16 bit)


TIM1_PSC (PSC)

TIM prescaler register
address_offset : 0x3828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM1_PSC TIM1_PSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC

PSC : PSC
bits : 0 - 15 (16 bit)


TIM1_ARR (ARR)

TIM auto-reload register
address_offset : 0x382C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM1_ARR TIM1_ARR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR

ARR : ARR
bits : 0 - 15 (16 bit)


TIM1_CCR1 (CCR1)

IM capture/compare register 1
address_offset : 0x3834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM1_CCR1 TIM1_CCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR

CCR : CCR
bits : 0 - 15 (16 bit)


TIM1_CCR2 (CCR2)

TIM capture/compare register 2
address_offset : 0x3838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM1_CCR2 TIM1_CCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR

CCR : CCR
bits : 0 - 15 (16 bit)


TIM1_CCR3 (CCR3)

TIM capture/compare register 3
address_offset : 0x383C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM1_CCR3 TIM1_CCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR

CCR : CCR
bits : 0 - 15 (16 bit)


TIM1_CCR4 (CCR4)

TIM capture/compare register 4
address_offset : 0x3840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM1_CCR4 TIM1_CCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR

CCR : CCR
bits : 0 - 15 (16 bit)


TIM1_OR (OR)

TIM option register
address_offset : 0x3850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM1_OR TIM1_OR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTRIGSEL CLKMSKEN ORRSVD

EXTRIGSEL : EXTRIGSEL
bits : 0 - 1 (2 bit)

CLKMSKEN : CLKMSKEN
bits : 2 - 2 (1 bit)

ORRSVD : ORRSVD
bits : 3 - 3 (1 bit)


TIM1_IER (IER)

TIM Interrupt Enable Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM1_IER TIM1_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIE CC1IE CC2IE CC3IE CC4IE TIE

UIE : UIE
bits : 0 - 0 (1 bit)

CC1IE : CC1IE
bits : 1 - 1 (1 bit)

CC2IE : CC2IE
bits : 2 - 2 (1 bit)

CC3IE : CC3IE
bits : 3 - 3 (1 bit)

CC4IE : CC4IE
bits : 4 - 4 (1 bit)

TIE : TIE
bits : 6 - 6 (1 bit)



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