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SerialControll

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1859 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SC2_ISR (ISR)

SC2_DR (DR)

SC2_CR (CR)

SC2_CRR1 (CRR1)

SC2_CRR2 (CRR2)

SC2_IER (IER)

SC2_ICR (ICR)


SC2_ISR (ISR)

Serial controller interrupt status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC2_ISR SC2_ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXNE TXE IDLE OVR UDR BRF BTF CMDFIN NACK RXULODA RXULODB TXULODA TXULODB FE PE

RXNE : RXNE
bits : 0 - 0 (1 bit)

TXE : TXE
bits : 1 - 1 (1 bit)

IDLE : IDLE
bits : 2 - 2 (1 bit)

OVR : OVR
bits : 3 - 3 (1 bit)

UDR : UDR
bits : 4 - 4 (1 bit)

BRF : BRF
bits : 5 - 5 (1 bit)

BTF : BTF
bits : 6 - 6 (1 bit)

CMDFIN : CMDFIN
bits : 7 - 7 (1 bit)

NACK : NACK
bits : 8 - 8 (1 bit)

RXULODA : RXULODA
bits : 9 - 9 (1 bit)

RXULODB : RXULODB
bits : 10 - 10 (1 bit)

TXULODA : TXULODA
bits : 11 - 11 (1 bit)

TXULODB : TXULODB
bits : 12 - 12 (1 bit)

FE : FE
bits : 13 - 13 (1 bit)

PE : PE
bits : 14 - 14 (1 bit)


SC2_DR (DR)

Serial controller data register
address_offset : 0x1830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC2_DR SC2_DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DR

DR : DR
bits : 0 - 7 (8 bit)


SC2_CR (CR)

Serial controller control register
address_offset : 0x1848 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC2_CR SC2_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE

MODE : MODE
bits : 0 - 1 (2 bit)


SC2_CRR1 (CRR1)

Serial controller clock rate register 1
address_offset : 0x1854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC2_CRR1 SC2_CRR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIN

LIN : LIN
bits : 0 - 3 (4 bit)


SC2_CRR2 (CRR2)

Serial controller clock rate register 2
address_offset : 0x1858 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC2_CRR2 SC2_CRR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXP

EXP : EXP
bits : 0 - 3 (4 bit)


SC2_IER (IER)

Serial controller interrupt enable register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC2_IER SC2_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXNEIE TXEIE IDLEIE OVRIE UDRIE BRFIE BTFIE CMDFINIE NACKIE RXULODAIE RXULODBIE TXULODAIE TXULODBIE FEIE PEIE

RXNEIE : RXNEIE
bits : 0 - 0 (1 bit)

TXEIE : TXEIE
bits : 1 - 1 (1 bit)

IDLEIE : IDLEIE
bits : 2 - 2 (1 bit)

OVRIE : OVRIE
bits : 3 - 3 (1 bit)

UDRIE : UDRIE
bits : 4 - 4 (1 bit)

BRFIE : BRFIE
bits : 5 - 5 (1 bit)

BTFIE : BTFIE
bits : 6 - 6 (1 bit)

CMDFINIE : CMDFINIE
bits : 7 - 7 (1 bit)

NACKIE : NACKIE
bits : 8 - 8 (1 bit)

RXULODAIE : RXULODAIE
bits : 9 - 9 (1 bit)

RXULODBIE : RXULODBIE
bits : 10 - 10 (1 bit)

TXULODAIE : TXULODAIE
bits : 11 - 11 (1 bit)

TXULODBIE : TXULODBIE
bits : 12 - 12 (1 bit)

FEIE : FEIE
bits : 13 - 13 (1 bit)

PEIE : PEIE
bits : 14 - 14 (1 bit)


SC2_ICR (ICR)

Serial controller interrupt control register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC2_ICR SC2_ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXNELEVEL TXELEVEL IDLELEVEL

RXNELEVEL : RXNELEVEL
bits : 0 - 0 (1 bit)

TXELEVEL : TXELEVEL
bits : 1 - 1 (1 bit)

IDLELEVEL : IDLELEVEL
bits : 2 - 2 (1 bit)



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