\n

ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2815 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ADC_ISR (ISR)

ADC_CR (CR)

ADC_OFFSETR (OFFSETR)

ADC_GAINR (GAINR)

ADC_DMACR (DMACR)

ADC_DMASR (DMASR)

ADC_DMAMSAR (DMAMSAR)

ADC_DMANDTR (DMANDTR)

ADC_DMAMNAR (DMAMNAR)

ADC_DMACNDTR (DMACNDTR)

ADC_IER (IER)


ADC_ISR (ISR)

ADC interrupt status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_ISR ADC_ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMABHF DMABF SAT DMAOVF

DMABHF : DMABHF
bits : 1 - 1 (1 bit)

DMABF : DMABF
bits : 2 - 2 (1 bit)

SAT : SAT
bits : 3 - 3 (1 bit)

DMAOVF : DMAOVF
bits : 4 - 4 (1 bit)


ADC_CR (CR)

ADC control register
address_offset : 0x27F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CR ADC_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADON CLK CHSELN CHSELP HVSELN HVSELP SMP

ADON : ADON
bits : 0 - 0 (1 bit)

CLK : CLK
bits : 2 - 2 (1 bit)

CHSELN : CHSELN
bits : 3 - 6 (4 bit)

CHSELP : CHSELP
bits : 7 - 10 (4 bit)

HVSELN : HVSELN
bits : 11 - 11 (1 bit)

HVSELP : HVSELP
bits : 12 - 12 (1 bit)

SMP : SMP
bits : 13 - 15 (3 bit)


ADC_OFFSETR (OFFSETR)

ADC offset register
address_offset : 0x27F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFFSETR ADC_OFFSETR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET

OFFSET : OFFSET
bits : 0 - 15 (16 bit)


ADC_GAINR (GAINR)

ADC gain register
address_offset : 0x27FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_GAINR ADC_GAINR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GAIN

GAIN : GAIN
bits : 0 - 15 (16 bit)


ADC_DMACR (DMACR)

ADC DMA control register
address_offset : 0x2800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DMACR ADC_DMACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOAD AUTOWRAP RST

LOAD : Loads the DMA buffer
bits : 0 - 0 (1 bit)
access : read-write

AUTOWRAP : Selects DMA mode
bits : 1 - 1 (1 bit)
access : read-write

RST : Write 1 to reset the ADC DMA
bits : 4 - 4 (1 bit)
access : write-only


ADC_DMASR (DMASR)

ADC DMA status register
address_offset : 0x2804 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADC_DMASR ADC_DMASR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT AOVF

ACT : ACT
bits : 0 - 0 (1 bit)

AOVF : AOVF
bits : 1 - 1 (1 bit)


ADC_DMAMSAR (DMAMSAR)

ADC DMA memory start address register
address_offset : 0x2808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DMAMSAR ADC_DMAMSAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSA

MSA : MSA
bits : 0 - 12 (13 bit)


ADC_DMANDTR (DMANDTR)

ADC DMA number of data to transfer register
address_offset : 0x280C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DMANDTR ADC_DMANDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : NDT
bits : 0 - 12 (13 bit)


ADC_DMAMNAR (DMAMNAR)

ADC DMA memory next address register
address_offset : 0x2810 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADC_DMAMNAR ADC_DMAMNAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MNA

MNA : MNA
bits : 1 - 13 (13 bit)


ADC_DMACNDTR (DMACNDTR)

ADC DMA count number of data transferred register
address_offset : 0x2814 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADC_DMACNDTR ADC_DMACNDTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNDT

CNDT : CNDT
bits : 0 - 12 (13 bit)


ADC_IER (IER)

ADC interrupt enable register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_IER ADC_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMABHFIE DMABFIE SATIE DMAOVFIE

DMABHFIE : DMABHFIE
bits : 1 - 1 (1 bit)

DMABFIE : DMABFIE
bits : 2 - 2 (1 bit)

SATIE : SATIE
bits : 3 - 3 (1 bit)

DMAOVFIE : DMAOVFIE
bits : 4 - 4 (1 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.