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EXTI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1405 byte (0x0)
mem_usage : registers
protection : not protected

Registers

EXTI_PR (PR)

EXTIC_CR

EXTID_CR

EXTIA_TSR

EXTIB_TSR

EXTIC_TSR

EXTID_TSR


EXTI_PR (PR)

EXTI pending register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTI_PR EXTI_PR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTIC_CR

EXTIC configuration register
address_offset : 0x1400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTIC_CR EXTIC_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_SEL

GPIO_SEL : GPIO_SEL
bits : 0 - 4 (5 bit)


EXTID_CR

EXTID configuration register
address_offset : 0x1404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTID_CR EXTID_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_SEL

GPIO_SEL : GPIO_SEL
bits : 0 - 4 (5 bit)


EXTIA_TSR

EXTIA trigger source register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTIA_TSR EXTIA_TSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTMOD FILTEN

INTMOD : INTMOD
bits : 5 - 7 (3 bit)

FILTEN : FILTEN
bits : 8 - 8 (1 bit)


EXTIB_TSR

EXTIB trigger source register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTIB_TSR EXTIB_TSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTMOD FILTEN

INTMOD : INTMOD
bits : 5 - 7 (3 bit)

FILTEN : FILTEN
bits : 8 - 8 (1 bit)


EXTIC_TSR

EXTIC trigger source register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTIC_TSR EXTIC_TSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTMOD FILTEN

INTMOD : INTMOD
bits : 5 - 7 (3 bit)

FILTEN : FILTEN
bits : 8 - 8 (1 bit)


EXTID_TSR

EXTID trigger source register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTID_TSR EXTID_TSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTMOD FILTEN

INTMOD : INTMOD
bits : 5 - 7 (3 bit)

FILTEN : FILTEN
bits : 8 - 8 (1 bit)



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