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GPIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

GPIOA_CRL (CRL)

GPIOA_BSR (BSR)

GPIOA_BRR (BRR)

GPIOA_CRH (CRH)

GPIOA_IDR (IDR)

GPIOA_ODR (ODR)


GPIOA_CRL (CRL)

Port A configuration register (Low)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_CRL GPIOA_CRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNFMODE0 CNFMODE1 CNFMODE2 CNFMODE3

CNFMODE0 : CNFMODE0
bits : 0 - 3 (4 bit)

CNFMODE1 : CNFMODE1
bits : 4 - 7 (4 bit)

CNFMODE2 : CNFMODE2
bits : 8 - 11 (4 bit)

CNFMODE3 : CNFMODE3
bits : 12 - 15 (4 bit)


GPIOA_BSR (BSR)

Port A bit set register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_BSR GPIOA_BSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BS0 BS1 BS2 BS3 BS4 BS5 BS6 BS7

BS0 : BS0
bits : 0 - 0 (1 bit)

BS1 : BS1
bits : 1 - 1 (1 bit)

BS2 : BS2
bits : 2 - 2 (1 bit)

BS3 : BS3
bits : 3 - 3 (1 bit)

BS4 : BS4
bits : 4 - 4 (1 bit)

BS5 : BS5
bits : 5 - 5 (1 bit)

BS6 : BS6
bits : 6 - 6 (1 bit)

BS7 : BS7
bits : 7 - 7 (1 bit)


GPIOA_BRR (BRR)

Port A output clear register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GPIOA_BRR GPIOA_BRR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BR0 BR1 BR2 BR3 BR4 BR5 BR6 BR7

BR0 : BR0
bits : 0 - 0 (1 bit)

BR1 : BR1
bits : 1 - 1 (1 bit)

BR2 : BR2
bits : 2 - 2 (1 bit)

BR3 : BR3
bits : 3 - 3 (1 bit)

BR4 : BR4
bits : 4 - 4 (1 bit)

BR5 : BR5
bits : 5 - 5 (1 bit)

BR6 : BR6
bits : 6 - 6 (1 bit)

BR7 : BR7
bits : 7 - 7 (1 bit)


GPIOA_CRH (CRH)

Port A configuration register (High)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_CRH GPIOA_CRH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNFMODE4 CNFMODE5 CNFMODE6 CNFMODE7

CNFMODE4 : CNFMODE4
bits : 0 - 3 (4 bit)

CNFMODE5 : CNFMODE5
bits : 4 - 7 (4 bit)

CNFMODE6 : CNFMODE6
bits : 8 - 11 (4 bit)

CNFMODE7 : CNFMODE7
bits : 12 - 15 (4 bit)


GPIOA_IDR (IDR)

Port A input data register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_IDR GPIOA_IDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDR0 IDR1 IDR2 IDR3 IDR4 IDR5 IDR6 IDR7

IDR0 : IDR0
bits : 0 - 0 (1 bit)

IDR1 : IDR1
bits : 1 - 1 (1 bit)

IDR2 : IDR2
bits : 2 - 2 (1 bit)

IDR3 : IDR3
bits : 3 - 3 (1 bit)

IDR4 : IDR4
bits : 4 - 4 (1 bit)

IDR5 : IDR5
bits : 5 - 5 (1 bit)

IDR6 : IDR6
bits : 6 - 6 (1 bit)

IDR7 : IDR7
bits : 7 - 7 (1 bit)


GPIOA_ODR (ODR)

Port A output data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_ODR GPIOA_ODR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODR0 ODR1 ODR2 ODR3 ODR4 ODR5 ODR6 ODR7

ODR0 : ODR0
bits : 0 - 0 (1 bit)

ODR1 : ODR1
bits : 1 - 1 (1 bit)

ODR2 : ODR2
bits : 2 - 2 (1 bit)

ODR3 : ODR3
bits : 3 - 3 (1 bit)

ODR4 : ODR4
bits : 4 - 4 (1 bit)

ODR5 : ODR5
bits : 5 - 5 (1 bit)

ODR6 : ODR6
bits : 6 - 6 (1 bit)

ODR7 : ODR7
bits : 7 - 7 (1 bit)



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