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WDG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x9 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x0 Bytes (0x0)
size : 0x9 byte (0x0)
mem_usage : registers
protection :

Registers

WDG_CR (CR)

WDG_KR (KR)

WDG_KICKSR (KICKSR)


WDG_CR (CR)

WDG configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDG_CR WDG_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDGEN WDGDIS

WDGEN : WDGEN
bits : 0 - 0 (1 bit)

WDGDIS : WDGDIS
bits : 1 - 1 (1 bit)


WDG_KR (KR)

WDG key register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

WDG_KR WDG_KR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : KEY
bits : 0 - 15 (16 bit)


WDG_KICKSR (KICKSR)

WDG kick-start register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

WDG_KICKSR WDG_KICKSR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KS

KS : KS
bits : 0 - 15 (16 bit)



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