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CLK

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4025 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CLK_SLEEPCR (SLEEPCR)

CLK_HSECR1 (HSECR1)

CLK_LSI10KCR (LSI10KCR)

CLK_HSICR (HSICR)

CLK_PERIODCR (PERIODCR)

CLK_PERIODSR (PERIODSR)

CLK_DITHERCR (DITHERCR)

CLK_HSECR2 (HSECR2)

CLK_CPUCR (CPUCR)

CLK_LSI1KCR (LSI1KCR)


CLK_SLEEPCR (SLEEPCR)

Sleep timer control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_SLEEPCR CLK_SLEEPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSEEN LSI10KEN

LSEEN : Enables 32kHz external XTAL
bits : 0 - 0 (1 bit)

LSI10KEN : Enables 10kHz internal RC during deep
bits : 1 - 1 (1 bit)


CLK_HSECR1 (HSECR1)

HSE Clock (24MHz) control register 1
address_offset : 0x3FFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_HSECR1 CLK_HSECR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIASTRIM

BIASTRIM : Bias trim setting for 24MHz oscillator
bits : 0 - 3 (4 bit)


CLK_LSI10KCR (LSI10KCR)

LSI Clock (10KHz) control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_LSI10KCR CLK_LSI10KCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TUNE

TUNE : Tune value for clkrc
bits : 0 - 3 (4 bit)


CLK_HSICR (HSICR)

HSI Clock (12MHz) trim register
address_offset : 0x4000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_HSICR CLK_HSICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TUNE

TUNE : Frequency trim setting for HF RC oscillator
bits : 0 - 4 (5 bit)


CLK_PERIODCR (PERIODCR)

Clock period control register
address_offset : 0x4008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PERIODCR CLK_PERIODCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE

MODE : Sets clock to be measured by CLK_PERIOD
bits : 0 - 1 (2 bit)


CLK_PERIODSR (PERIODSR)

Clock period status register
address_offset : 0x400C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CLK_PERIODSR CLK_PERIODSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIOD

PERIOD : Clock period measurement
bits : 0 - 15 (16 bit)


CLK_DITHERCR (DITHERCR)

Clock dither control register
address_offset : 0x4010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_DITHERCR CLK_DITHERCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIS

DIS : Dither disable
bits : 0 - 0 (1 bit)


CLK_HSECR2 (HSECR2)

HSE Clock (24MHz) control register 2
address_offset : 0x4014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_HSECR2 CLK_HSECR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW1 EN

SW1 : OSCHF/XTAL is selected
bits : 0 - 0 (1 bit)

EN : MHz crystal oscillator is main clock
bits : 1 - 1 (1 bit)


CLK_CPUCR (CPUCR)

Clock source select register
address_offset : 0x4018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CPUCR CLK_CPUCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW2

SW2 : 12MHz/24MHz is selected
bits : 0 - 0 (1 bit)


CLK_LSI1KCR (LSI1KCR)

LSI Clock (1KHz) control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_LSI1KCR CLK_LSI1KCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKFRAC CALINT

CLKFRAC : Divider value fractional portion
bits : 0 - 10 (11 bit)

CALINT : Divider value integer portion
bits : 11 - 25 (15 bit)



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