\n
address_offset : 0x0 Bytes (0x0)
size : 0x4025 byte (0x0)
mem_usage : registers
protection : not protected
Sleep timer control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSEEN : Enables 32kHz external XTAL
bits : 0 - 0 (1 bit)
LSI10KEN : Enables 10kHz internal RC during deep
bits : 1 - 1 (1 bit)
HSE Clock (24MHz) control register 1
address_offset : 0x3FFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BIASTRIM : Bias trim setting for 24MHz oscillator
bits : 0 - 3 (4 bit)
LSI Clock (10KHz) control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNE : Tune value for clkrc
bits : 0 - 3 (4 bit)
HSI Clock (12MHz) trim register
address_offset : 0x4000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNE : Frequency trim setting for HF RC oscillator
bits : 0 - 4 (5 bit)
Clock period control register
address_offset : 0x4008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Sets clock to be measured by CLK_PERIOD
bits : 0 - 1 (2 bit)
Clock period status register
address_offset : 0x400C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Clock period measurement
bits : 0 - 15 (16 bit)
Clock dither control register
address_offset : 0x4010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIS : Dither disable
bits : 0 - 0 (1 bit)
HSE Clock (24MHz) control register 2
address_offset : 0x4014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW1 : OSCHF/XTAL is selected
bits : 0 - 0 (1 bit)
EN : MHz crystal oscillator is main clock
bits : 1 - 1 (1 bit)
Clock source select register
address_offset : 0x4018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW2 : 12MHz/24MHz is selected
bits : 0 - 0 (1 bit)
LSI Clock (1KHz) control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKFRAC : Divider value fractional portion
bits : 0 - 10 (11 bit)
CALINT : Divider value integer portion
bits : 11 - 25 (15 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.