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FLASH

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x43D4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

FLASH_CLKER (CLKER)

FLASH_ACR (ACR)

FLASH_KEYR (KEYR)

FLASH_OPTKEYR (OPTKEYR)

FLASH_SR (SR)

FLASH_CR (CR)

FLASH_AR (AR)

FLASH_OBR (OBR)

FLASH_WRPR (WRPR)

FLASH_CLKSR (CLKSR)


FLASH_CLKER (CLKER)

FLASH controller clock enable register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLASH_CLKER FLASH_CLKER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : EN
bits : 0 - 0 (1 bit)


FLASH_ACR (ACR)

FLASH access control register
address_offset : 0x3FD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLASH_ACR FLASH_ACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LATENCY HLFCYA PRFTBE PRFTBS

LATENCY : LATENCY
bits : 0 - 2 (3 bit)
access : read-write

HLFCYA : HLFCYA
bits : 3 - 3 (1 bit)
access : read-write

PRFTBE : PRFTBE
bits : 4 - 4 (1 bit)
access : read-write

PRFTBS : Prefetch Status
bits : 5 - 5 (1 bit)
access : read-only


FLASH_KEYR (KEYR)

FLASH key register
address_offset : 0x3FD8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FLASH_KEYR FLASH_KEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FKEYR

FKEYR : FKEYR
bits : 0 - 31 (32 bit)


FLASH_OPTKEYR (OPTKEYR)

FLASH OPT key register
address_offset : 0x3FDC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FLASH_OPTKEYR FLASH_OPTKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPTKEYR

OPTKEYR : OPTKEYR
bits : 0 - 31 (32 bit)


FLASH_SR (SR)

FLASH status register
address_offset : 0x3FE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLASH_SR FLASH_SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BSY PGERR WRPRTERR EOP

BSY : BSY
bits : 0 - 0 (1 bit)
access : write-only

PGERR : PGERR
bits : 2 - 2 (1 bit)
access : read-write

WRPRTERR : WRPRTERR
bits : 4 - 4 (1 bit)
access : read-write

EOP : EOP
bits : 5 - 5 (1 bit)
access : read-write


FLASH_CR (CR)

FLASH control register
address_offset : 0x3FE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLASH_CR FLASH_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PG PER MER OPTPG OPTER STRT LOCK OPTWRE ERRIE EOPIE

PG : PG
bits : 0 - 0 (1 bit)

PER : PER
bits : 1 - 1 (1 bit)

MER : MER
bits : 2 - 2 (1 bit)

OPTPG : OPTPG
bits : 4 - 4 (1 bit)

OPTER : OPTER
bits : 5 - 5 (1 bit)

STRT : STRT
bits : 6 - 6 (1 bit)

LOCK : LOCK
bits : 7 - 7 (1 bit)

OPTWRE : OPTWRE
bits : 9 - 9 (1 bit)

ERRIE : ERRIE
bits : 10 - 10 (1 bit)

EOPIE : EOPIE
bits : 12 - 12 (1 bit)


FLASH_AR (AR)

FLASH address register
address_offset : 0x3FE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLASH_AR FLASH_AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAR

FAR : FAR
bits : 0 - 31 (32 bit)


FLASH_OBR (OBR)

FLASH option bytes register
address_offset : 0x3FF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FLASH_OBR FLASH_OBR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPTERR RDPRT

OPTERR : OPTERR
bits : 0 - 0 (1 bit)

RDPRT : RDPRT
bits : 1 - 1 (1 bit)


FLASH_WRPR (WRPR)

FLASH write protection register
address_offset : 0x3FF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FLASH_WRPR FLASH_WRPR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRP

WRP : WRP
bits : 0 - 31 (32 bit)


FLASH_CLKSR (CLKSR)

FLASH controller clock status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLASH_CLKSR FLASH_CLKSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACK BSY

ACK : ACK
bits : 0 - 0 (1 bit)

BSY : BSY
bits : 1 - 1 (1 bit)



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