\n
address_offset : 0x0 Bytes (0x0)
size : 0x43D4 byte (0x0)
mem_usage : registers
protection : not protected
FLASH controller clock enable register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
FLASH access control register
address_offset : 0x3FD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LATENCY : LATENCY
bits : 0 - 2 (3 bit)
access : read-write
HLFCYA : HLFCYA
bits : 3 - 3 (1 bit)
access : read-write
PRFTBE : PRFTBE
bits : 4 - 4 (1 bit)
access : read-write
PRFTBS : Prefetch Status
bits : 5 - 5 (1 bit)
access : read-only
FLASH key register
address_offset : 0x3FD8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FKEYR : FKEYR
bits : 0 - 31 (32 bit)
FLASH OPT key register
address_offset : 0x3FDC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OPTKEYR : OPTKEYR
bits : 0 - 31 (32 bit)
FLASH status register
address_offset : 0x3FE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSY : BSY
bits : 0 - 0 (1 bit)
access : write-only
PGERR : PGERR
bits : 2 - 2 (1 bit)
access : read-write
WRPRTERR : WRPRTERR
bits : 4 - 4 (1 bit)
access : read-write
EOP : EOP
bits : 5 - 5 (1 bit)
access : read-write
FLASH control register
address_offset : 0x3FE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG : PG
bits : 0 - 0 (1 bit)
PER : PER
bits : 1 - 1 (1 bit)
MER : MER
bits : 2 - 2 (1 bit)
OPTPG : OPTPG
bits : 4 - 4 (1 bit)
OPTER : OPTER
bits : 5 - 5 (1 bit)
STRT : STRT
bits : 6 - 6 (1 bit)
LOCK : LOCK
bits : 7 - 7 (1 bit)
OPTWRE : OPTWRE
bits : 9 - 9 (1 bit)
ERRIE : ERRIE
bits : 10 - 10 (1 bit)
EOPIE : EOPIE
bits : 12 - 12 (1 bit)
FLASH address register
address_offset : 0x3FE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAR : FAR
bits : 0 - 31 (32 bit)
FLASH option bytes register
address_offset : 0x3FF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OPTERR : OPTERR
bits : 0 - 0 (1 bit)
RDPRT : RDPRT
bits : 1 - 1 (1 bit)
FLASH write protection register
address_offset : 0x3FF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WRP : WRP
bits : 0 - 31 (32 bit)
FLASH controller clock status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACK : ACK
bits : 0 - 0 (1 bit)
BSY : BSY
bits : 1 - 1 (1 bit)
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