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SLPTMR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4049 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SLPTMR_CR (CR)

SLPTMR_CMPAL (CMPAL)

SLPTMR_CMPBH (CMPBH)

SLPTMR_CMPBL (CMPBL)

SLPTMR_CNTH (CNTH)

SLPTMR_ISR (ISR)

SLPTMR_IFR (IFR)

SLPTMR_IER (IER)

SLPTMR_CNTL (CNTL)

SLPTMR_CMPAH (CMPAH)


SLPTMR_CR (CR)

SLPTMR configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLPTMR_CR SLPTMR_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKSEL PSC DBGP EN REVERSE

CLKSEL : CLKSEL
bits : 0 - 0 (1 bit)

PSC : PSC
bits : 4 - 7 (4 bit)

DBGP : DBGP
bits : 10 - 10 (1 bit)

EN : EN
bits : 11 - 11 (1 bit)

REVERSE : REVERSE
bits : 12 - 12 (1 bit)


SLPTMR_CMPAL (CMPAL)

SLPTMR compare A low register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLPTMR_CMPAL SLPTMR_CMPAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPAL

CMPAL : CMPAL
bits : 0 - 15 (16 bit)


SLPTMR_CMPBH (CMPBH)

SLPTMR compare B high register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLPTMR_CMPBH SLPTMR_CMPBH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPBH

CMPBH : CMPBH
bits : 0 - 15 (16 bit)


SLPTMR_CMPBL (CMPBL)

SLPTMR compare B low register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLPTMR_CMPBL SLPTMR_CMPBL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPBL

CMPBL : CMPBL
bits : 0 - 15 (16 bit)


SLPTMR_CNTH (CNTH)

SLPTMR counter high register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SLPTMR_CNTH SLPTMR_CNTH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTH

CNTH : CNTH
bits : 0 - 15 (16 bit)


SLPTMR_ISR (ISR)

SLPTMR interrupt status register
address_offset : 0x4008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLPTMR_ISR SLPTMR_ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OW CMPA CMPB

OW : OW
bits : 0 - 0 (1 bit)

CMPA : CMPA
bits : 1 - 1 (1 bit)

CMPB : CMPB
bits : 2 - 2 (1 bit)


SLPTMR_IFR (IFR)

SLPTMR force interrupts register
address_offset : 0x4014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLPTMR_IFR SLPTMR_IFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OW CMPA CMPB

OW : OW
bits : 0 - 0 (1 bit)

CMPA : CMPA
bits : 1 - 1 (1 bit)

CMPB : CMPB
bits : 2 - 2 (1 bit)


SLPTMR_IER (IER)

SLPTMR interrupt enable register
address_offset : 0x4048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLPTMR_IER SLPTMR_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRAP CMPA CMPB

WRAP : WRAP
bits : 0 - 0 (1 bit)

CMPA : CMPA
bits : 1 - 1 (1 bit)

CMPB : CMPB
bits : 2 - 2 (1 bit)


SLPTMR_CNTL (CNTL)

SLPTMR counter high register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SLPTMR_CNTL SLPTMR_CNTL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTL

CNTL : CNTL
bits : 0 - 15 (16 bit)


SLPTMR_CMPAH (CMPAH)

SLPTMR compare A high register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLPTMR_CMPAH SLPTMR_CMPAH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPAH

CMPAH : CMPAH
bits : 0 - 15 (16 bit)



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