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address_offset : 0x0 Bytes (0x0)
size : 0xBC19 byte (0x0)
mem_usage : registers
protection : not protected
PWR_CSYSPWRUPREQSR (CSYSPWRUPREQSR)
PWR_CSYSPWRUPACKSR (CSYSPWRUPACKSR)
PWR_CSYSPWRUPACKCR (CSYSPWRUPACKCR)
PWR_DSLEEPCR1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_CSYSPWRUPACKCR : PWR_CSYSPWRUPACKCR
bits : 1 - 1 (1 bit)
PWR_DSLEEPCR2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : MODE
bits : 0 - 0 (1 bit)
Voltage regulator Control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_VREGCR_1V2TRIM : 1V2 regulator trim value
bits : 0 - 2 (3 bit)
PWR_VREGCR_1V2EN : 1V2 direct controle of regulator on/off
bits : 4 - 4 (1 bit)
PWR_VREGCR_1V8TRIM : 1V8 regulator trim value
bits : 7 - 9 (3 bit)
PWR_VREGCR_1V8EN : 1V8 direct controle of regulator on/off
bits : 11 - 11 (1 bit)
PWR_VREGCR_VREFEN : VREF on/off
bits : 15 - 15 (1 bit)
PWR_WAKECR1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAKEEN : WAKEEN
bits : 0 - 0 (1 bit)
SC1 : SC1
bits : 1 - 1 (1 bit)
SC2 : SC2
bits : 2 - 2 (1 bit)
IRQD : IRQD
bits : 3 - 3 (1 bit)
COMPA : COMPA
bits : 4 - 4 (1 bit)
COMPB : COMPB
bits : 5 - 5 (1 bit)
WRAP : WRAP
bits : 6 - 6 (1 bit)
CORE : CORE
bits : 7 - 7 (1 bit)
CPWRRUPREQ : CPWRRUPREQ
bits : 8 - 8 (1 bit)
CSYSPWRUPREQ : CSYSPWRUPREQ
bits : 9 - 9 (1 bit)
PWR_WAKECR2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COREWAKE : COREWAKE
bits : 5 - 5 (1 bit)
PWR_WAKESR
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOPIN : GPIOPIN
bits : 0 - 0 (1 bit)
SC1 : SC1
bits : 1 - 1 (1 bit)
SC2 : SC2
bits : 2 - 2 (1 bit)
IRQD : IRQD
bits : 3 - 3 (1 bit)
ARQD : ARQD
bits : 3 - 3 (1 bit)
COMPA : COMPA
bits : 4 - 4 (1 bit)
COMPB : COMPB
bits : 5 - 5 (1 bit)
WRAP : WRAP
bits : 6 - 6 (1 bit)
CORE : CORE
bits : 7 - 7 (1 bit)
CPWRRUPREQ : CPWRRUPREQ
bits : 8 - 8 (1 bit)
CSYSPWRUPREQ : CSYSPWRUPREQ
bits : 9 - 9 (1 bit)
PWR_CPWRUPREQSR
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REQ : REQ
bits : 0 - 0 (1 bit)
PWR_CSYSPWRUPREQSR
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REQ : REQ
bits : 0 - 0 (1 bit)
PWR_CSYSPWRUPACKSR
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACK : ACK
bits : 0 - 0 (1 bit)
PWR_CSYSPWRUPACKCR
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INHIBIT : INHIBIT
bits : 0 - 0 (1 bit)
Wake GPIO Port A register
address_offset : 0xBC04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA0 : PA0
bits : 0 - 0 (1 bit)
PA1 : PA1
bits : 1 - 1 (1 bit)
PA2 : PA2
bits : 2 - 2 (1 bit)
PA3 : PA3
bits : 3 - 3 (1 bit)
PA4 : PA4
bits : 4 - 4 (1 bit)
PA5 : PA5
bits : 5 - 5 (1 bit)
PA6 : PA6
bits : 6 - 6 (1 bit)
PA7 : PA7
bits : 7 - 7 (1 bit)
Wake GPIO Port B register
address_offset : 0xBC08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB0 : PB0
bits : 0 - 0 (1 bit)
PB1 : PB1
bits : 1 - 1 (1 bit)
PB2 : PB2
bits : 2 - 2 (1 bit)
PB3 : PB3
bits : 3 - 3 (1 bit)
PB4 : PB4
bits : 4 - 4 (1 bit)
PB5 : PB5
bits : 5 - 5 (1 bit)
PB6 : PB6
bits : 6 - 6 (1 bit)
PB7 : PB7
bits : 7 - 7 (1 bit)
Wake GPIO Port C register
address_offset : 0xBC0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC0 : PC0
bits : 0 - 0 (1 bit)
PC1 : PC1
bits : 1 - 1 (1 bit)
PC2 : PC2
bits : 2 - 2 (1 bit)
PC3 : PC3
bits : 3 - 3 (1 bit)
PC4 : PC4
bits : 4 - 4 (1 bit)
PC5 : PC5
bits : 5 - 5 (1 bit)
PC6 : PC6
bits : 6 - 6 (1 bit)
PC7 : PC7
bits : 7 - 7 (1 bit)
Wake filter register
address_offset : 0xBC18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO : Enable filter on GPIO wakeup sources enabled by the PWR_WAKEPxR registers
bits : 0 - 0 (1 bit)
SC1 : Enable filter on GPIO wakeup source SC1 (PB2)
bits : 1 - 1 (1 bit)
SC2 : Enable filter on GPIO wakeup source SC2 (PA2)
bits : 2 - 2 (1 bit)
IRQD : Enable filter on GPIO wakeup source EXTI D
bits : 3 - 3 (1 bit)
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