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PWR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xBC19 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PWR_DSLEEPCR1 (DSLEEPCR1)

PWR_DSLEEPCR2 (DSLEEPCR2)

PWR_VREGCR (VREGCR)

PWR_WAKECR1 (WAKECR1)

PWR_WAKECR2 (WAKECR2)

PWR_WAKESR (WAKESR)

PWR_CPWRUPREQSR (CPWRUPREQSR)

PWR_CSYSPWRUPREQSR (CSYSPWRUPREQSR)

PWR_CSYSPWRUPACKSR (CSYSPWRUPACKSR)

PWR_CSYSPWRUPACKCR (CSYSPWRUPACKCR)

PWR_WAKEPAR (WAKEPAR)

PWR_WAKEPBR (WAKEPBR)

PWR_WAKEPCR (WAKEPCR)

PWR_WAKEFILTR (WAKEFILTR)


PWR_DSLEEPCR1 (DSLEEPCR1)

PWR_DSLEEPCR1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR_DSLEEPCR1 PWR_DSLEEPCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWR_CSYSPWRUPACKCR

PWR_CSYSPWRUPACKCR : PWR_CSYSPWRUPACKCR
bits : 1 - 1 (1 bit)


PWR_DSLEEPCR2 (DSLEEPCR2)

PWR_DSLEEPCR2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR_DSLEEPCR2 PWR_DSLEEPCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE

MODE : MODE
bits : 0 - 0 (1 bit)


PWR_VREGCR (VREGCR)

Voltage regulator Control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR_VREGCR PWR_VREGCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWR_VREGCR_1V2TRIM PWR_VREGCR_1V2EN PWR_VREGCR_1V8TRIM PWR_VREGCR_1V8EN PWR_VREGCR_VREFEN

PWR_VREGCR_1V2TRIM : 1V2 regulator trim value
bits : 0 - 2 (3 bit)

PWR_VREGCR_1V2EN : 1V2 direct controle of regulator on/off
bits : 4 - 4 (1 bit)

PWR_VREGCR_1V8TRIM : 1V8 regulator trim value
bits : 7 - 9 (3 bit)

PWR_VREGCR_1V8EN : 1V8 direct controle of regulator on/off
bits : 11 - 11 (1 bit)

PWR_VREGCR_VREFEN : VREF on/off
bits : 15 - 15 (1 bit)


PWR_WAKECR1 (WAKECR1)

PWR_WAKECR1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR_WAKECR1 PWR_WAKECR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAKEEN SC1 SC2 IRQD COMPA COMPB WRAP CORE CPWRRUPREQ CSYSPWRUPREQ

WAKEEN : WAKEEN
bits : 0 - 0 (1 bit)

SC1 : SC1
bits : 1 - 1 (1 bit)

SC2 : SC2
bits : 2 - 2 (1 bit)

IRQD : IRQD
bits : 3 - 3 (1 bit)

COMPA : COMPA
bits : 4 - 4 (1 bit)

COMPB : COMPB
bits : 5 - 5 (1 bit)

WRAP : WRAP
bits : 6 - 6 (1 bit)

CORE : CORE
bits : 7 - 7 (1 bit)

CPWRRUPREQ : CPWRRUPREQ
bits : 8 - 8 (1 bit)

CSYSPWRUPREQ : CSYSPWRUPREQ
bits : 9 - 9 (1 bit)


PWR_WAKECR2 (WAKECR2)

PWR_WAKECR2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PWR_WAKECR2 PWR_WAKECR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COREWAKE

COREWAKE : COREWAKE
bits : 5 - 5 (1 bit)


PWR_WAKESR (WAKESR)

PWR_WAKESR
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR_WAKESR PWR_WAKESR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOPIN SC1 SC2 IRQD ARQD COMPA COMPB WRAP CORE CPWRRUPREQ CSYSPWRUPREQ

GPIOPIN : GPIOPIN
bits : 0 - 0 (1 bit)

SC1 : SC1
bits : 1 - 1 (1 bit)

SC2 : SC2
bits : 2 - 2 (1 bit)

IRQD : IRQD
bits : 3 - 3 (1 bit)

ARQD : ARQD
bits : 3 - 3 (1 bit)

COMPA : COMPA
bits : 4 - 4 (1 bit)

COMPB : COMPB
bits : 5 - 5 (1 bit)

WRAP : WRAP
bits : 6 - 6 (1 bit)

CORE : CORE
bits : 7 - 7 (1 bit)

CPWRRUPREQ : CPWRRUPREQ
bits : 8 - 8 (1 bit)

CSYSPWRUPREQ : CSYSPWRUPREQ
bits : 9 - 9 (1 bit)


PWR_CPWRUPREQSR (CPWRUPREQSR)

PWR_CPWRUPREQSR
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PWR_CPWRUPREQSR PWR_CPWRUPREQSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REQ

REQ : REQ
bits : 0 - 0 (1 bit)


PWR_CSYSPWRUPREQSR (CSYSPWRUPREQSR)

PWR_CSYSPWRUPREQSR
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PWR_CSYSPWRUPREQSR PWR_CSYSPWRUPREQSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REQ

REQ : REQ
bits : 0 - 0 (1 bit)


PWR_CSYSPWRUPACKSR (CSYSPWRUPACKSR)

PWR_CSYSPWRUPACKSR
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PWR_CSYSPWRUPACKSR PWR_CSYSPWRUPACKSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACK

ACK : ACK
bits : 0 - 0 (1 bit)


PWR_CSYSPWRUPACKCR (CSYSPWRUPACKCR)

PWR_CSYSPWRUPACKCR
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PWR_CSYSPWRUPACKCR PWR_CSYSPWRUPACKCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INHIBIT

INHIBIT : INHIBIT
bits : 0 - 0 (1 bit)


PWR_WAKEPAR (WAKEPAR)

Wake GPIO Port A register
address_offset : 0xBC04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR_WAKEPAR PWR_WAKEPAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7

PA0 : PA0
bits : 0 - 0 (1 bit)

PA1 : PA1
bits : 1 - 1 (1 bit)

PA2 : PA2
bits : 2 - 2 (1 bit)

PA3 : PA3
bits : 3 - 3 (1 bit)

PA4 : PA4
bits : 4 - 4 (1 bit)

PA5 : PA5
bits : 5 - 5 (1 bit)

PA6 : PA6
bits : 6 - 6 (1 bit)

PA7 : PA7
bits : 7 - 7 (1 bit)


PWR_WAKEPBR (WAKEPBR)

Wake GPIO Port B register
address_offset : 0xBC08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR_WAKEPBR PWR_WAKEPBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7

PB0 : PB0
bits : 0 - 0 (1 bit)

PB1 : PB1
bits : 1 - 1 (1 bit)

PB2 : PB2
bits : 2 - 2 (1 bit)

PB3 : PB3
bits : 3 - 3 (1 bit)

PB4 : PB4
bits : 4 - 4 (1 bit)

PB5 : PB5
bits : 5 - 5 (1 bit)

PB6 : PB6
bits : 6 - 6 (1 bit)

PB7 : PB7
bits : 7 - 7 (1 bit)


PWR_WAKEPCR (WAKEPCR)

Wake GPIO Port C register
address_offset : 0xBC0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR_WAKEPCR PWR_WAKEPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7

PC0 : PC0
bits : 0 - 0 (1 bit)

PC1 : PC1
bits : 1 - 1 (1 bit)

PC2 : PC2
bits : 2 - 2 (1 bit)

PC3 : PC3
bits : 3 - 3 (1 bit)

PC4 : PC4
bits : 4 - 4 (1 bit)

PC5 : PC5
bits : 5 - 5 (1 bit)

PC6 : PC6
bits : 6 - 6 (1 bit)

PC7 : PC7
bits : 7 - 7 (1 bit)


PWR_WAKEFILTR (WAKEFILTR)

Wake filter register
address_offset : 0xBC18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR_WAKEFILTR PWR_WAKEFILTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO SC1 SC2 IRQD

GPIO : Enable filter on GPIO wakeup sources enabled by the PWR_WAKEPxR registers
bits : 0 - 0 (1 bit)

SC1 : Enable filter on GPIO wakeup source SC1 (PB2)
bits : 1 - 1 (1 bit)

SC2 : Enable filter on GPIO wakeup source SC2 (PA2)
bits : 2 - 2 (1 bit)

IRQD : Enable filter on GPIO wakeup source EXTI D
bits : 3 - 3 (1 bit)



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