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NVIC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1001 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ISER0

ICER0

ISPR0

ICPR0

IABR0

ICTR

IPR0

IPR1

IPR2

IPR3

IPR4

STIR


ISER0

Interrupt Set-Enable Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER0 ISER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : SETENA
bits : 0 - 31 (32 bit)


ICER0

Interrupt Clear-Enable Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER0 ICER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : CLRENA
bits : 0 - 31 (32 bit)


ISPR0

Interrupt Set-Pending Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR0 ISPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : SETPEND
bits : 0 - 31 (32 bit)


ICPR0

Interrupt Clear-Pending Register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR0 ICPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : CLRPEND
bits : 0 - 31 (32 bit)


IABR0

Interrupt Active Bit Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IABR0 IABR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : ACTIVE
bits : 0 - 31 (32 bit)


ICTR

Interrupt Controller Type Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ICTR ICTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTLINESNUM

INTLINESNUM : Total number of interrupt lines in groups
bits : 0 - 3 (4 bit)


IPR0

Interrupt Priority Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR0 IPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR_N0 IPR_N1 IPR_N2 IPR_N3

IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)

IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)

IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)

IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)


IPR1

Interrupt Priority Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR1 IPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR_N0 IPR_N1 IPR_N2 IPR_N3

IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)

IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)

IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)

IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)


IPR2

Interrupt Priority Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR2 IPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR_N0 IPR_N1 IPR_N2 IPR_N3

IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)

IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)

IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)

IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)


IPR3

Interrupt Priority Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR3 IPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR_N0 IPR_N1 IPR_N2 IPR_N3

IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)

IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)

IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)

IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)


IPR4

Interrupt Priority Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR4 IPR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR_N0 IPR_N1 IPR_N2 IPR_N3

IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)

IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)

IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)

IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)


STIR

Software Triggered Interrupt Register
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

STIR STIR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTID

INTID : interrupt to be triggered
bits : 0 - 8 (9 bit)



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