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SerialControll

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x71 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SC2_DMARXBEGADDAR

SC2_DMATXBEGADDAR

SC2_DMATXENDADDAR

SC2_DMATXBEGADDBR

SC2_DMATXENDADDBR

SC2_DMARXCNTAR

SC2_DMARXCNTBR

SC2_DMATXCNTR

SC2_DMASR

SC2_DMACR

SC2_DMARXERRAR

SC2_DMARXERRBR

SC2_DMARXENDADDAR

SC2_DMARXCNTSAVEDR

SC2_DMARXBEGADDBR

SC2_DMARXENDADDBR


SC2_DMARXBEGADDAR

Serial controller receive DMA begin address channel A register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC2_DMARXBEGADDAR SC2_DMARXBEGADDAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD

ADD : ADD
bits : 0 - 12 (13 bit)


SC2_DMATXBEGADDAR

Serial controller transmit DMA begin address channel A register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC2_DMATXBEGADDAR SC2_DMATXBEGADDAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD

ADD : ADD
bits : 0 - 12 (13 bit)


SC2_DMATXENDADDAR

Serial controller transmit DMA end address channel A register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC2_DMATXENDADDAR SC2_DMATXENDADDAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD

ADD : ADD
bits : 0 - 12 (13 bit)


SC2_DMATXBEGADDBR

Serial controller transmit DMA begin address channel B register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC2_DMATXBEGADDBR SC2_DMATXBEGADDBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD

ADD : ADD
bits : 0 - 12 (13 bit)


SC2_DMATXENDADDBR

Serial controller transmit DMA end address channel B register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC2_DMATXENDADDBR SC2_DMATXENDADDBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD

ADD : ADD
bits : 0 - 12 (13 bit)


SC2_DMARXCNTAR

Serial controller receive DMA counter channel A register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC2_DMARXCNTAR SC2_DMARXCNTAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : CNT
bits : 0 - 12 (13 bit)


SC2_DMARXCNTBR

Serial controller receive DMA count channel B register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC2_DMARXCNTBR SC2_DMARXCNTBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : CNT
bits : 0 - 12 (13 bit)


SC2_DMATXCNTR

Serial controller transmit DMA counter register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SC2_DMATXCNTR SC2_DMATXCNTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : CNT
bits : 0 - 12 (13 bit)


SC2_DMASR

Serial controller DMA status register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SC2_DMASR SC2_DMASR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXAACK RXBACK TXAACK TXBACK OVRA OVRB PEA PEB FEA FEB NSSS

RXAACK : RXAACK
bits : 0 - 0 (1 bit)

RXBACK : RXBACK
bits : 1 - 1 (1 bit)

TXAACK : TXAACK
bits : 2 - 2 (1 bit)

TXBACK : TXBACK
bits : 3 - 3 (1 bit)

OVRA : OVRA
bits : 4 - 4 (1 bit)

OVRB : OVRB
bits : 5 - 5 (1 bit)

PEA : PEA
bits : 6 - 6 (1 bit)

PEB : PEB
bits : 7 - 7 (1 bit)

FEA : FEA
bits : 8 - 8 (1 bit)

FEB : FEB
bits : 9 - 9 (1 bit)

NSSS : NSSS
bits : 10 - 12 (3 bit)


SC2_DMACR

Serial controller DMA control register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC2_DMACR SC2_DMACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXLODA RXLODB TXLODA TXLODB RXRST TXRST

RXLODA : RXLODA
bits : 0 - 0 (1 bit)
access : read-write

RXLODB : RXLODB
bits : 1 - 1 (1 bit)
access : read-write

TXLODA : TXLODA
bits : 2 - 2 (1 bit)
access : read-write

TXLODB : TXLODB
bits : 3 - 3 (1 bit)
access : read-write

RXRST : RXRST
bits : 4 - 4 (1 bit)
access : write-only

TXRST : TXRST
bits : 5 - 5 (1 bit)
access : write-only


SC2_DMARXERRAR

Serial controller receive DMA channel A first error register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SC2_DMARXERRAR SC2_DMARXERRAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD

ADD : ADD
bits : 0 - 12 (13 bit)


SC2_DMARXERRBR

Serial controller receive DMA channel B first error register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SC2_DMARXERRBR SC2_DMARXERRBR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD

ADD : ADD
bits : 0 - 12 (13 bit)


SC2_DMARXENDADDAR

Serial controller receive DMA end address channel A register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC2_DMARXENDADDAR SC2_DMARXENDADDAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD

ADD : ADD
bits : 0 - 12 (13 bit)


SC2_DMARXCNTSAVEDR

Serial controller receive DMA saved counter channel B register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SC2_DMARXCNTSAVEDR SC2_DMARXCNTSAVEDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : CNT
bits : 0 - 12 (13 bit)


SC2_DMARXBEGADDBR

Serial controller receive DMA begin address channel B register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC2_DMARXBEGADDBR SC2_DMARXBEGADDBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD

ADD : ADD
bits : 0 - 12 (13 bit)


SC2_DMARXENDADDBR

Serial controller receive DMA end address channel B register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC2_DMARXENDADDBR SC2_DMARXENDADDBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD

ADD : ADD
bits : 0 - 12 (13 bit)



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