CCM

Registers

GPR0

PLL_CTRL0

PLL_CTRL27_SET

ACCESS_CTRL_ROOT0_SET

ACCESS_CTRL_ROOT0_CLR

ACCESS_CTRL_ROOT0_TOG

ACCESS_CTRL_ROOT1_SET

ACCESS_CTRL_ROOT1_CLR

ACCESS_CTRL_ROOT1_TOG

ACCESS_CTRL_ROOT2_SET

ACCESS_CTRL_ROOT2_CLR

ACCESS_CTRL_ROOT2_TOG

ACCESS_CTRL_ROOT3_SET

ACCESS_CTRL_ROOT3_CLR

ACCESS_CTRL_ROOT3_TOG

ACCESS_CTRL_ROOT4_SET

ACCESS_CTRL_ROOT4_CLR

ACCESS_CTRL_ROOT4_TOG

ACCESS_CTRL_ROOT16_SET

ACCESS_CTRL_ROOT16_CLR

ACCESS_CTRL_ROOT16_TOG

ACCESS_CTRL_ROOT17_SET

ACCESS_CTRL_ROOT17_CLR

ACCESS_CTRL_ROOT17_TOG

ACCESS_CTRL_ROOT18_SET

ACCESS_CTRL_ROOT18_CLR

ACCESS_CTRL_ROOT18_TOG

ACCESS_CTRL_ROOT19_SET

ACCESS_CTRL_ROOT19_CLR

ACCESS_CTRL_ROOT19_TOG

ACCESS_CTRL_ROOT20_SET

ACCESS_CTRL_ROOT20_CLR

ACCESS_CTRL_ROOT20_TOG

ACCESS_CTRL_ROOT21_SET

ACCESS_CTRL_ROOT21_CLR

ACCESS_CTRL_ROOT21_TOG

ACCESS_CTRL_ROOT22_SET

ACCESS_CTRL_ROOT22_CLR

ACCESS_CTRL_ROOT22_TOG

ACCESS_CTRL_ROOT23_SET

ACCESS_CTRL_ROOT23_CLR

ACCESS_CTRL_ROOT23_TOG

ACCESS_CTRL_ROOT24_SET

ACCESS_CTRL_ROOT24_CLR

ACCESS_CTRL_ROOT24_TOG

ACCESS_CTRL_ROOT25_SET

ACCESS_CTRL_ROOT25_CLR

ACCESS_CTRL_ROOT25_TOG

ACCESS_CTRL_ROOT26_SET

ACCESS_CTRL_ROOT26_CLR

ACCESS_CTRL_ROOT26_TOG

ACCESS_CTRL_ROOT27_SET

ACCESS_CTRL_ROOT27_CLR

ACCESS_CTRL_ROOT27_TOG

ACCESS_CTRL_ROOT32_SET

ACCESS_CTRL_ROOT32_CLR

ACCESS_CTRL_ROOT32_TOG

ACCESS_CTRL_ROOT33_SET

ACCESS_CTRL_ROOT33_CLR

ACCESS_CTRL_ROOT33_TOG

ACCESS_CTRL_ROOT34_SET

ACCESS_CTRL_ROOT34_CLR

ACCESS_CTRL_ROOT34_TOG

ACCESS_CTRL_ROOT35_SET

ACCESS_CTRL_ROOT35_CLR

ACCESS_CTRL_ROOT35_TOG

ACCESS_CTRL_ROOT36_SET

ACCESS_CTRL_ROOT36_CLR

ACCESS_CTRL_ROOT36_TOG

ACCESS_CTRL_ROOT37_SET

ACCESS_CTRL_ROOT37_CLR

ACCESS_CTRL_ROOT37_TOG

ACCESS_CTRL_ROOT48_SET

ACCESS_CTRL_ROOT48_CLR

ACCESS_CTRL_ROOT48_TOG

ACCESS_CTRL_ROOT49_SET

ACCESS_CTRL_ROOT49_CLR

ACCESS_CTRL_ROOT49_TOG

ACCESS_CTRL_ROOT64_SET

ACCESS_CTRL_ROOT64_CLR

ACCESS_CTRL_ROOT64_TOG

ACCESS_CTRL_ROOT65_SET

ACCESS_CTRL_ROOT65_CLR

ACCESS_CTRL_ROOT65_TOG

ACCESS_CTRL_ROOT66_SET

ACCESS_CTRL_ROOT66_CLR

ACCESS_CTRL_ROOT66_TOG

ACCESS_CTRL_ROOT67_SET

ACCESS_CTRL_ROOT67_CLR

ACCESS_CTRL_ROOT67_TOG

ACCESS_CTRL_ROOT68_SET

ACCESS_CTRL_ROOT68_CLR

ACCESS_CTRL_ROOT68_TOG

ACCESS_CTRL_ROOT69_SET

ACCESS_CTRL_ROOT69_CLR

CCGR38_CLR

ACCESS_CTRL_ROOT69_TOG

ACCESS_CTRL_ROOT70_SET

ACCESS_CTRL_ROOT70_CLR

ACCESS_CTRL_ROOT70_TOG

ACCESS_CTRL_ROOT71_SET

ACCESS_CTRL_ROOT71_CLR

ACCESS_CTRL_ROOT71_TOG

ACCESS_CTRL_ROOT72_SET

ACCESS_CTRL_ROOT72_CLR

ACCESS_CTRL_ROOT72_TOG

ACCESS_CTRL_ROOT73_SET

ACCESS_CTRL_ROOT73_CLR

ACCESS_CTRL_ROOT73_TOG

ACCESS_CTRL_ROOT74_SET

ACCESS_CTRL_ROOT74_CLR

ACCESS_CTRL_ROOT74_TOG

ACCESS_CTRL_ROOT75_SET

ACCESS_CTRL_ROOT75_CLR

ACCESS_CTRL_ROOT75_TOG

ACCESS_CTRL_ROOT76_SET

ACCESS_CTRL_ROOT76_CLR

ACCESS_CTRL_ROOT76_TOG

ACCESS_CTRL_ROOT77_SET

ACCESS_CTRL_ROOT77_CLR

ACCESS_CTRL_ROOT77_TOG

ACCESS_CTRL_ROOT78_SET

ACCESS_CTRL_ROOT78_CLR

ACCESS_CTRL_ROOT78_TOG

ACCESS_CTRL_ROOT79_SET

ACCESS_CTRL_ROOT79_CLR

ACCESS_CTRL_ROOT79_TOG

ACCESS_CTRL_ROOT80_SET

ACCESS_CTRL_ROOT80_CLR

ACCESS_CTRL_ROOT80_TOG

ACCESS_CTRL_ROOT81_SET

ACCESS_CTRL_ROOT81_CLR

ACCESS_CTRL_ROOT81_TOG

ACCESS_CTRL_ROOT82_SET

ACCESS_CTRL_ROOT82_CLR

ACCESS_CTRL_ROOT82_TOG

ACCESS_CTRL_ROOT83_SET

ACCESS_CTRL_ROOT83_CLR

ACCESS_CTRL_ROOT83_TOG

ACCESS_CTRL_ROOT84_SET

ACCESS_CTRL_ROOT84_CLR

ACCESS_CTRL_ROOT84_TOG

ACCESS_CTRL_ROOT85_SET

ACCESS_CTRL_ROOT85_CLR

ACCESS_CTRL_ROOT85_TOG

ACCESS_CTRL_ROOT86_SET

ACCESS_CTRL_ROOT86_CLR

ACCESS_CTRL_ROOT86_TOG

ACCESS_CTRL_ROOT87_SET

ACCESS_CTRL_ROOT87_CLR

ACCESS_CTRL_ROOT87_TOG

ACCESS_CTRL_ROOT88_SET

ACCESS_CTRL_ROOT88_CLR

ACCESS_CTRL_ROOT88_TOG

ACCESS_CTRL_ROOT89_SET

ACCESS_CTRL_ROOT89_CLR

ACCESS_CTRL_ROOT89_TOG

ACCESS_CTRL_ROOT90_SET

ACCESS_CTRL_ROOT90_CLR

ACCESS_CTRL_ROOT90_TOG

ACCESS_CTRL_ROOT91_SET

ACCESS_CTRL_ROOT91_CLR

ACCESS_CTRL_ROOT91_TOG

ACCESS_CTRL_ROOT92_SET

ACCESS_CTRL_ROOT92_CLR

ACCESS_CTRL_ROOT92_TOG

ACCESS_CTRL_ROOT93_SET

ACCESS_CTRL_ROOT93_CLR

ACCESS_CTRL_ROOT93_TOG

ACCESS_CTRL_ROOT94_SET

ACCESS_CTRL_ROOT94_CLR

ACCESS_CTRL_ROOT94_TOG

ACCESS_CTRL_ROOT95_SET

ACCESS_CTRL_ROOT95_CLR

ACCESS_CTRL_ROOT95_TOG

ACCESS_CTRL_ROOT96_SET

ACCESS_CTRL_ROOT96_CLR

ACCESS_CTRL_ROOT96_TOG

ACCESS_CTRL_ROOT97_SET

ACCESS_CTRL_ROOT97_CLR

ACCESS_CTRL_ROOT97_TOG

ACCESS_CTRL_ROOT98_SET

ACCESS_CTRL_ROOT98_CLR

ACCESS_CTRL_ROOT98_TOG

ACCESS_CTRL_ROOT99_SET

ACCESS_CTRL_ROOT99_CLR

ACCESS_CTRL_ROOT99_TOG

ACCESS_CTRL_ROOT100_SET

ACCESS_CTRL_ROOT100_CLR

ACCESS_CTRL_ROOT100_TOG

ACCESS_CTRL_ROOT101_SET

ACCESS_CTRL_ROOT101_CLR

ACCESS_CTRL_ROOT101_TOG

ACCESS_CTRL_ROOT102_SET

ACCESS_CTRL_ROOT102_CLR

ACCESS_CTRL_ROOT102_TOG

ACCESS_CTRL_ROOT103_SET

ACCESS_CTRL_ROOT103_CLR

ACCESS_CTRL_ROOT103_TOG

ACCESS_CTRL_ROOT104_SET

ACCESS_CTRL_ROOT104_CLR

ACCESS_CTRL_ROOT104_TOG

ACCESS_CTRL_ROOT105_SET

ACCESS_CTRL_ROOT105_CLR

ACCESS_CTRL_ROOT105_TOG

ACCESS_CTRL_ROOT106_SET

ACCESS_CTRL_ROOT106_CLR

ACCESS_CTRL_ROOT106_TOG

ACCESS_CTRL_ROOT107_SET

ACCESS_CTRL_ROOT107_CLR

ACCESS_CTRL_ROOT107_TOG

ACCESS_CTRL_ROOT108_SET

ACCESS_CTRL_ROOT108_CLR

ACCESS_CTRL_ROOT108_TOG

ACCESS_CTRL_ROOT109_SET

ACCESS_CTRL_ROOT109_CLR

ACCESS_CTRL_ROOT109_TOG

ACCESS_CTRL_ROOT110_SET

ACCESS_CTRL_ROOT110_CLR

ACCESS_CTRL_ROOT110_TOG

ACCESS_CTRL_ROOT111_SET

ACCESS_CTRL_ROOT111_CLR

ACCESS_CTRL_ROOT111_TOG

ACCESS_CTRL_ROOT112_SET

ACCESS_CTRL_ROOT112_CLR

ACCESS_CTRL_ROOT112_TOG

ACCESS_CTRL_ROOT113_SET

ACCESS_CTRL_ROOT113_CLR

ACCESS_CTRL_ROOT113_TOG

ACCESS_CTRL_ROOT114_SET

ACCESS_CTRL_ROOT114_CLR

ACCESS_CTRL_ROOT114_TOG

ACCESS_CTRL_ROOT115_SET

ACCESS_CTRL_ROOT115_CLR

ACCESS_CTRL_ROOT115_TOG

ACCESS_CTRL_ROOT116_SET

ACCESS_CTRL_ROOT116_CLR

ACCESS_CTRL_ROOT116_TOG

ACCESS_CTRL_ROOT117_SET

ACCESS_CTRL_ROOT117_CLR

ACCESS_CTRL_ROOT117_TOG

ACCESS_CTRL_ROOT118_SET

ACCESS_CTRL_ROOT118_CLR

ACCESS_CTRL_ROOT118_TOG

ACCESS_CTRL_ROOT119_SET

CCGR44_CLR

ACCESS_CTRL_ROOT119_CLR

ACCESS_CTRL_ROOT119_TOG

ACCESS_CTRL_ROOT120_SET

ACCESS_CTRL_ROOT120_CLR

ACCESS_CTRL_ROOT120_TOG

ACCESS_CTRL_ROOT121_SET

ACCESS_CTRL_ROOT121_CLR

ACCESS_CTRL_ROOT121_TOG

ACCESS_CTRL_ROOT122_SET

PLL_CTRL20_SET

ACCESS_CTRL_ROOT122_CLR

ACCESS_CTRL_ROOT122_TOG

ACCESS_CTRL_ROOT123_SET

ACCESS_CTRL_ROOT123_CLR

ACCESS_CTRL_ROOT123_TOG

ACCESS_CTRL_ROOT124_SET

ACCESS_CTRL_ROOT124_CLR

ACCESS_CTRL_ROOT124_TOG

ACCESS_CTRL_ROOT125_SET

ACCESS_CTRL_ROOT125_CLR

ACCESS_CTRL_ROOT125_TOG

ACCESS_CTRL_ROOT126_SET

ACCESS_CTRL_ROOT126_CLR

ACCESS_CTRL_ROOT126_TOG

ACCESS_CTRL_ROOT127_SET

ACCESS_CTRL_ROOT127_CLR

ACCESS_CTRL_ROOT127_TOG

ACCESS_CTRL_ROOT128_SET

ACCESS_CTRL_ROOT128_CLR

ACCESS_CTRL_ROOT128_TOG

ACCESS_CTRL_ROOT129_SET

ACCESS_CTRL_ROOT129_CLR

ACCESS_CTRL_ROOT129_TOG

ACCESS_CTRL_ROOT130_SET

ACCESS_CTRL_ROOT130_CLR

ACCESS_CTRL_ROOT130_TOG

ACCESS_CTRL_ROOT131_SET

ACCESS_CTRL_ROOT131_CLR

ACCESS_CTRL_ROOT131_TOG

ACCESS_CTRL_ROOT132_SET

ACCESS_CTRL_ROOT132_CLR

ACCESS_CTRL_ROOT132_TOG

ACCESS_CTRL_ROOT133_SET

ACCESS_CTRL_ROOT133_CLR

ACCESS_CTRL_ROOT133_TOG

ACCESS_CTRL_ROOT134_SET

ACCESS_CTRL_ROOT134_CLR

ACCESS_CTRL_ROOT134_TOG

ACCESS_CTRL_ROOT135_SET

ACCESS_CTRL_ROOT135_CLR

ACCESS_CTRL_ROOT135_TOG

ACCESS_CTRL_ROOT136_SET

ACCESS_CTRL_ROOT136_CLR

ACCESS_CTRL_ROOT136_TOG

ACCESS_CTRL_ROOT137_SET

ACCESS_CTRL_ROOT137_CLR

ACCESS_CTRL_ROOT137_TOG

ACCESS_CTRL_ROOT138_SET

ACCESS_CTRL_ROOT138_CLR

ACCESS_CTRL_ROOT138_TOG

ACCESS_CTRL_ROOT139_SET

ACCESS_CTRL_ROOT139_CLR

ACCESS_CTRL_ROOT139_TOG

ACCESS_CTRL_ROOT140_SET

ACCESS_CTRL_ROOT140_CLR

ACCESS_CTRL_ROOT140_TOG

ACCESS_CTRL_ROOT141_SET

ACCESS_CTRL_ROOT141_CLR

ACCESS_CTRL_ROOT141_TOG

GPR0

General Purpose Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP0 : Timeout cycle count of ipg_clk, when perform read and write.
bits : 0 - 31 (32 bit)
access : read-write

PLL_CTRL0

CCM PLL Control Register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL27_SET

CCM PLL Control Register
address_offset : 0x10014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR2

CCM Clock Gating Register
address_offset : 0x10030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR2_SET

CCM Clock Gating Register
address_offset : 0x10040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR2_CLR

CCM Clock Gating Register
address_offset : 0x10050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR2_TOG

CCM Clock Gating Register
address_offset : 0x10060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL0_SET

CCM PLL Control Register
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL27_CLR

CCM PLL Control Register
address_offset : 0x10088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL27_TOG

CCM PLL Control Register
address_offset : 0x100FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL0_CLR

CCM PLL Control Register
address_offset : 0x1010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL0_TOG

CCM PLL Control Register
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR61

CCM Clock Gating Register
address_offset : 0x103630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR61_SET

CCM Clock Gating Register
address_offset : 0x10372C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR61_CLR

CCM Clock Gating Register
address_offset : 0x103828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR61_TOG

CCM Clock Gating Register
address_offset : 0x103924 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR62

CCM Clock Gating Register
address_offset : 0x107A10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR62_SET

CCM Clock Gating Register
address_offset : 0x107B10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR62_CLR

CCM Clock Gating Register
address_offset : 0x107C10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR62_TOG

CCM Clock Gating Register
address_offset : 0x107D10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL28

CCM PLL Control Register
address_offset : 0x10960 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL28_SET

CCM PLL Control Register
address_offset : 0x109D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL28_CLR

CCM PLL Control Register
address_offset : 0x10A50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL28_TOG

CCM PLL Control Register
address_offset : 0x10AC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR63

CCM Clock Gating Register
address_offset : 0x10BE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR63_SET

CCM Clock Gating Register
address_offset : 0x10BF04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR63_CLR

CCM Clock Gating Register
address_offset : 0x10C008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR63_TOG

CCM Clock Gating Register
address_offset : 0x10C10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR64

CCM Clock Gating Register
address_offset : 0x110200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR64_SET

CCM Clock Gating Register
address_offset : 0x110308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR64_CLR

CCM Clock Gating Register
address_offset : 0x110410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR64_TOG

CCM Clock Gating Register
address_offset : 0x110518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL29

CCM PLL Control Register
address_offset : 0x11330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL29_SET

CCM PLL Control Register
address_offset : 0x113AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL29_CLR

CCM PLL Control Register
address_offset : 0x11428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR65

CCM Clock Gating Register
address_offset : 0x114610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR65_SET

CCM Clock Gating Register
address_offset : 0x11471C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR65_CLR

CCM Clock Gating Register
address_offset : 0x114828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR65_TOG

CCM Clock Gating Register
address_offset : 0x114934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL29_TOG

CCM PLL Control Register
address_offset : 0x114A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR66

CCM Clock Gating Register
address_offset : 0x118A30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR66_SET

CCM Clock Gating Register
address_offset : 0x118B40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR66_CLR

CCM Clock Gating Register
address_offset : 0x118C50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR66_TOG

CCM Clock Gating Register
address_offset : 0x118D60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR67

CCM Clock Gating Register
address_offset : 0x11CE60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR67_SET

CCM Clock Gating Register
address_offset : 0x11CF74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR67_CLR

CCM Clock Gating Register
address_offset : 0x11D088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL30

CCM PLL Control Register
address_offset : 0x11D10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR67_TOG

CCM Clock Gating Register
address_offset : 0x11D19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL30_SET

CCM PLL Control Register
address_offset : 0x11D90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL30_CLR

CCM PLL Control Register
address_offset : 0x11E10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL30_TOG

CCM PLL Control Register
address_offset : 0x11E90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR68

CCM Clock Gating Register
address_offset : 0x1212A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR68_SET

CCM Clock Gating Register
address_offset : 0x1213B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR68_CLR

CCM Clock Gating Register
address_offset : 0x1214D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR68_TOG

CCM Clock Gating Register
address_offset : 0x1215E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR69

CCM Clock Gating Register
address_offset : 0x1256F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR69_SET

CCM Clock Gating Register
address_offset : 0x12580C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR69_CLR

CCM Clock Gating Register
address_offset : 0x125928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR69_TOG

CCM Clock Gating Register
address_offset : 0x125A44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL31

CCM PLL Control Register
address_offset : 0x12700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL31_SET

CCM PLL Control Register
address_offset : 0x12784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL31_CLR

CCM PLL Control Register
address_offset : 0x12808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL31_TOG

CCM PLL Control Register
address_offset : 0x1288C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR70

CCM Clock Gating Register
address_offset : 0x129B50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR70_SET

CCM Clock Gating Register
address_offset : 0x129C70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR70_CLR

CCM Clock Gating Register
address_offset : 0x129D90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR70_TOG

CCM Clock Gating Register
address_offset : 0x129EB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR71

CCM Clock Gating Register
address_offset : 0x12DFC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR71_SET

CCM Clock Gating Register
address_offset : 0x12E0E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR71_CLR

CCM Clock Gating Register
address_offset : 0x12E208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR71_TOG

CCM Clock Gating Register
address_offset : 0x12E32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL32

CCM PLL Control Register
address_offset : 0x13100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL32_SET

CCM PLL Control Register
address_offset : 0x13188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL32_CLR

CCM PLL Control Register
address_offset : 0x13210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR72

CCM Clock Gating Register
address_offset : 0x132440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR72_SET

CCM Clock Gating Register
address_offset : 0x132568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR72_CLR

CCM Clock Gating Register
address_offset : 0x132690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR72_TOG

CCM Clock Gating Register
address_offset : 0x1327B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL32_TOG

CCM PLL Control Register
address_offset : 0x13298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR73

CCM Clock Gating Register
address_offset : 0x1368D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR73_SET

CCM Clock Gating Register
address_offset : 0x1369FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR73_CLR

CCM Clock Gating Register
address_offset : 0x136B28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR73_TOG

CCM Clock Gating Register
address_offset : 0x136C54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR74

CCM Clock Gating Register
address_offset : 0x13AD70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR74_SET

CCM Clock Gating Register
address_offset : 0x13AEA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR74_CLR

CCM Clock Gating Register
address_offset : 0x13AFD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL33

CCM PLL Control Register
address_offset : 0x13B10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR74_TOG

CCM Clock Gating Register
address_offset : 0x13B100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL33_SET

CCM PLL Control Register
address_offset : 0x13B9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL33_CLR

CCM PLL Control Register
address_offset : 0x13C28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL33_TOG

CCM PLL Control Register
address_offset : 0x13CB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR75

CCM Clock Gating Register
address_offset : 0x13F220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR75_SET

CCM Clock Gating Register
address_offset : 0x13F354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR75_CLR

CCM Clock Gating Register
address_offset : 0x13F488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR75_TOG

CCM Clock Gating Register
address_offset : 0x13F5BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR3

CCM Clock Gating Register
address_offset : 0x14060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR3_SET

CCM Clock Gating Register
address_offset : 0x14074 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR3_CLR

CCM Clock Gating Register
address_offset : 0x14088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR3_TOG

CCM Clock Gating Register
address_offset : 0x1409C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR76

CCM Clock Gating Register
address_offset : 0x1436E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR76_SET

CCM Clock Gating Register
address_offset : 0x143818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR76_CLR

CCM Clock Gating Register
address_offset : 0x143950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR76_TOG

CCM Clock Gating Register
address_offset : 0x143A88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL34

CCM PLL Control Register
address_offset : 0x14530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL34_SET

CCM PLL Control Register
address_offset : 0x145C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL34_CLR

CCM PLL Control Register
address_offset : 0x14650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL34_TOG

CCM PLL Control Register
address_offset : 0x146E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR77

CCM Clock Gating Register
address_offset : 0x147BB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR77_SET

CCM Clock Gating Register
address_offset : 0x147CEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR77_CLR

CCM Clock Gating Register
address_offset : 0x147E28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR77_TOG

CCM Clock Gating Register
address_offset : 0x147F64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR78

CCM Clock Gating Register
address_offset : 0x14C090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR78_SET

CCM Clock Gating Register
address_offset : 0x14C1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR78_CLR

CCM Clock Gating Register
address_offset : 0x14C310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR78_TOG

CCM Clock Gating Register
address_offset : 0x14C450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL35

CCM PLL Control Register
address_offset : 0x14F60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL35_SET

CCM PLL Control Register
address_offset : 0x14FF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR79

CCM Clock Gating Register
address_offset : 0x150580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR79_SET

CCM Clock Gating Register
address_offset : 0x1506C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR79_CLR

CCM Clock Gating Register
address_offset : 0x150808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL35_CLR

CCM PLL Control Register
address_offset : 0x15088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR79_TOG

CCM Clock Gating Register
address_offset : 0x15094C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL35_TOG

CCM PLL Control Register
address_offset : 0x1511C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR80

CCM Clock Gating Register
address_offset : 0x154A80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR80_SET

CCM Clock Gating Register
address_offset : 0x154BC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR80_CLR

CCM Clock Gating Register
address_offset : 0x154D10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR80_TOG

CCM Clock Gating Register
address_offset : 0x154E58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR81

CCM Clock Gating Register
address_offset : 0x158F90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR81_SET

CCM Clock Gating Register
address_offset : 0x1590DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR81_CLR

CCM Clock Gating Register
address_offset : 0x159228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR81_TOG

CCM Clock Gating Register
address_offset : 0x159374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL36

CCM PLL Control Register
address_offset : 0x159A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL36_SET

CCM PLL Control Register
address_offset : 0x15A38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL36_CLR

CCM PLL Control Register
address_offset : 0x15AD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL36_TOG

CCM PLL Control Register
address_offset : 0x15B68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR82

CCM Clock Gating Register
address_offset : 0x15D4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR82_SET

CCM Clock Gating Register
address_offset : 0x15D600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR82_CLR

CCM Clock Gating Register
address_offset : 0x15D750 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR82_TOG

CCM Clock Gating Register
address_offset : 0x15D8A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR83

CCM Clock Gating Register
address_offset : 0x1619E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR83_SET

CCM Clock Gating Register
address_offset : 0x161B34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR83_CLR

CCM Clock Gating Register
address_offset : 0x161C88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR83_TOG

CCM Clock Gating Register
address_offset : 0x161DDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL37

CCM PLL Control Register
address_offset : 0x163F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL37_SET

CCM PLL Control Register
address_offset : 0x1648C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL37_CLR

CCM PLL Control Register
address_offset : 0x16528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL37_TOG

CCM PLL Control Register
address_offset : 0x165C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR84

CCM Clock Gating Register
address_offset : 0x165F20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR84_SET

CCM Clock Gating Register
address_offset : 0x166078 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR84_CLR

CCM Clock Gating Register
address_offset : 0x1661D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR84_TOG

CCM Clock Gating Register
address_offset : 0x166328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR85

CCM Clock Gating Register
address_offset : 0x16A470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR85_SET

CCM Clock Gating Register
address_offset : 0x16A5CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR85_CLR

CCM Clock Gating Register
address_offset : 0x16A728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR85_TOG

CCM Clock Gating Register
address_offset : 0x16A884 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL38

CCM PLL Control Register
address_offset : 0x16E50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR86

CCM Clock Gating Register
address_offset : 0x16E9D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR86_SET

CCM Clock Gating Register
address_offset : 0x16EB30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR86_CLR

CCM Clock Gating Register
address_offset : 0x16EC90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR86_TOG

CCM Clock Gating Register
address_offset : 0x16EDF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL38_SET

CCM PLL Control Register
address_offset : 0x16EF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL38_CLR

CCM PLL Control Register
address_offset : 0x16F90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL38_TOG

CCM PLL Control Register
address_offset : 0x17030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR87

CCM Clock Gating Register
address_offset : 0x172F40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR87_SET

CCM Clock Gating Register
address_offset : 0x1730A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR87_CLR

CCM Clock Gating Register
address_offset : 0x173208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR87_TOG

CCM Clock Gating Register
address_offset : 0x17336C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR88

CCM Clock Gating Register
address_offset : 0x1774C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR88_SET

CCM Clock Gating Register
address_offset : 0x177628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR88_CLR

CCM Clock Gating Register
address_offset : 0x177790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR88_TOG

CCM Clock Gating Register
address_offset : 0x1778F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR89

CCM Clock Gating Register
address_offset : 0x17BA50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR89_SET

CCM Clock Gating Register
address_offset : 0x17BBBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR89_CLR

CCM Clock Gating Register
address_offset : 0x17BD28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR89_TOG

CCM Clock Gating Register
address_offset : 0x17BE94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR90

CCM Clock Gating Register
address_offset : 0x17FFF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR90_SET

CCM Clock Gating Register
address_offset : 0x180160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR90_CLR

CCM Clock Gating Register
address_offset : 0x1802D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR90_TOG

CCM Clock Gating Register
address_offset : 0x180440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR4

CCM Clock Gating Register
address_offset : 0x180A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR4_SET

CCM Clock Gating Register
address_offset : 0x180B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR4_CLR

CCM Clock Gating Register
address_offset : 0x180D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR4_TOG

CCM Clock Gating Register
address_offset : 0x180E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL1

CCM PLL Control Register
address_offset : 0x1810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL1_SET

CCM PLL Control Register
address_offset : 0x181C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL1_CLR

CCM PLL Control Register
address_offset : 0x1828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL1_TOG

CCM PLL Control Register
address_offset : 0x1834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR91

CCM Clock Gating Register
address_offset : 0x1845A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR91_SET

CCM Clock Gating Register
address_offset : 0x184714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR91_CLR

CCM Clock Gating Register
address_offset : 0x184888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR91_TOG

CCM Clock Gating Register
address_offset : 0x1849FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR92

CCM Clock Gating Register
address_offset : 0x188B60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR92_SET

CCM Clock Gating Register
address_offset : 0x188CD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR92_CLR

CCM Clock Gating Register
address_offset : 0x188E50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR92_TOG

CCM Clock Gating Register
address_offset : 0x188FC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR93

CCM Clock Gating Register
address_offset : 0x18D130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR93_SET

CCM Clock Gating Register
address_offset : 0x18D2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR93_CLR

CCM Clock Gating Register
address_offset : 0x18D428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR93_TOG

CCM Clock Gating Register
address_offset : 0x18D5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR94

CCM Clock Gating Register
address_offset : 0x191710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR94_SET

CCM Clock Gating Register
address_offset : 0x191890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR94_CLR

CCM Clock Gating Register
address_offset : 0x191A10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR94_TOG

CCM Clock Gating Register
address_offset : 0x191B90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR95

CCM Clock Gating Register
address_offset : 0x195D00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR95_SET

CCM Clock Gating Register
address_offset : 0x195E84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR95_CLR

CCM Clock Gating Register
address_offset : 0x196008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR95_TOG

CCM Clock Gating Register
address_offset : 0x19618C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR96

CCM Clock Gating Register
address_offset : 0x19A300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR96_SET

CCM Clock Gating Register
address_offset : 0x19A488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR96_CLR

CCM Clock Gating Register
address_offset : 0x19A610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR96_TOG

CCM Clock Gating Register
address_offset : 0x19A798 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR97

CCM Clock Gating Register
address_offset : 0x19E910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR97_SET

CCM Clock Gating Register
address_offset : 0x19EA9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR97_CLR

CCM Clock Gating Register
address_offset : 0x19EC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR97_TOG

CCM Clock Gating Register
address_offset : 0x19EDB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR98

CCM Clock Gating Register
address_offset : 0x1A2F30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR98_SET

CCM Clock Gating Register
address_offset : 0x1A30C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR98_CLR

CCM Clock Gating Register
address_offset : 0x1A3250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR98_TOG

CCM Clock Gating Register
address_offset : 0x1A33E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR99

CCM Clock Gating Register
address_offset : 0x1A7560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR99_SET

CCM Clock Gating Register
address_offset : 0x1A76F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR99_CLR

CCM Clock Gating Register
address_offset : 0x1A7888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR99_TOG

CCM Clock Gating Register
address_offset : 0x1A7A1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR100

CCM Clock Gating Register
address_offset : 0x1ABBA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR100_SET

CCM Clock Gating Register
address_offset : 0x1ABD38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR100_CLR

CCM Clock Gating Register
address_offset : 0x1ABED0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR100_TOG

CCM Clock Gating Register
address_offset : 0x1AC068 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR101

CCM Clock Gating Register
address_offset : 0x1B01F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR101_SET

CCM Clock Gating Register
address_offset : 0x1B038C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR101_CLR

CCM Clock Gating Register
address_offset : 0x1B0528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR101_TOG

CCM Clock Gating Register
address_offset : 0x1B06C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR102

CCM Clock Gating Register
address_offset : 0x1B4850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR102_SET

CCM Clock Gating Register
address_offset : 0x1B49F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR102_CLR

CCM Clock Gating Register
address_offset : 0x1B4B90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR102_TOG

CCM Clock Gating Register
address_offset : 0x1B4D30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR103

CCM Clock Gating Register
address_offset : 0x1B8EC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR103_SET

CCM Clock Gating Register
address_offset : 0x1B9064 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR103_CLR

CCM Clock Gating Register
address_offset : 0x1B9208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR103_TOG

CCM Clock Gating Register
address_offset : 0x1B93AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR104

CCM Clock Gating Register
address_offset : 0x1BD540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR104_SET

CCM Clock Gating Register
address_offset : 0x1BD6E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR104_CLR

CCM Clock Gating Register
address_offset : 0x1BD890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR104_TOG

CCM Clock Gating Register
address_offset : 0x1BDA38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR5

CCM Clock Gating Register
address_offset : 0x1C0F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR5_SET

CCM Clock Gating Register
address_offset : 0x1C10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR5_CLR

CCM Clock Gating Register
address_offset : 0x1C128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR5_TOG

CCM Clock Gating Register
address_offset : 0x1C144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR105

CCM Clock Gating Register
address_offset : 0x1C1BD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR105_SET

CCM Clock Gating Register
address_offset : 0x1C1D7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR105_CLR

CCM Clock Gating Register
address_offset : 0x1C1F28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR105_TOG

CCM Clock Gating Register
address_offset : 0x1C20D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR106

CCM Clock Gating Register
address_offset : 0x1C6270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR106_SET

CCM Clock Gating Register
address_offset : 0x1C6420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR106_CLR

CCM Clock Gating Register
address_offset : 0x1C65D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR106_TOG

CCM Clock Gating Register
address_offset : 0x1C6780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR107

CCM Clock Gating Register
address_offset : 0x1CA920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR107_SET

CCM Clock Gating Register
address_offset : 0x1CAAD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR107_CLR

CCM Clock Gating Register
address_offset : 0x1CAC88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR107_TOG

CCM Clock Gating Register
address_offset : 0x1CAE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR108

CCM Clock Gating Register
address_offset : 0x1CEFE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR108_SET

CCM Clock Gating Register
address_offset : 0x1CF198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR108_CLR

CCM Clock Gating Register
address_offset : 0x1CF350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR108_TOG

CCM Clock Gating Register
address_offset : 0x1CF508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR109

CCM Clock Gating Register
address_offset : 0x1D36B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR109_SET

CCM Clock Gating Register
address_offset : 0x1D386C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR109_CLR

CCM Clock Gating Register
address_offset : 0x1D3A28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR109_TOG

CCM Clock Gating Register
address_offset : 0x1D3BE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR110

CCM Clock Gating Register
address_offset : 0x1D7D90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR110_SET

CCM Clock Gating Register
address_offset : 0x1D7F50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR110_CLR

CCM Clock Gating Register
address_offset : 0x1D8110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR110_TOG

CCM Clock Gating Register
address_offset : 0x1D82D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR111

CCM Clock Gating Register
address_offset : 0x1DC480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR111_SET

CCM Clock Gating Register
address_offset : 0x1DC644 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR111_CLR

CCM Clock Gating Register
address_offset : 0x1DC808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR111_TOG

CCM Clock Gating Register
address_offset : 0x1DC9CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR112

CCM Clock Gating Register
address_offset : 0x1E0B80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR112_SET

CCM Clock Gating Register
address_offset : 0x1E0D48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR112_CLR

CCM Clock Gating Register
address_offset : 0x1E0F10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR112_TOG

CCM Clock Gating Register
address_offset : 0x1E10D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR113

CCM Clock Gating Register
address_offset : 0x1E5290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR113_SET

CCM Clock Gating Register
address_offset : 0x1E545C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR113_CLR

CCM Clock Gating Register
address_offset : 0x1E5628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR113_TOG

CCM Clock Gating Register
address_offset : 0x1E57F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR114

CCM Clock Gating Register
address_offset : 0x1E99B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR114_SET

CCM Clock Gating Register
address_offset : 0x1E9B80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR114_CLR

CCM Clock Gating Register
address_offset : 0x1E9D50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR114_TOG

CCM Clock Gating Register
address_offset : 0x1E9F20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR115

CCM Clock Gating Register
address_offset : 0x1EE0E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR115_SET

CCM Clock Gating Register
address_offset : 0x1EE2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR115_CLR

CCM Clock Gating Register
address_offset : 0x1EE488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR115_TOG

CCM Clock Gating Register
address_offset : 0x1EE65C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR116

CCM Clock Gating Register
address_offset : 0x1F2820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR116_SET

CCM Clock Gating Register
address_offset : 0x1F29F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR116_CLR

CCM Clock Gating Register
address_offset : 0x1F2BD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR116_TOG

CCM Clock Gating Register
address_offset : 0x1F2DA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR117

CCM Clock Gating Register
address_offset : 0x1F6F70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR117_SET

CCM Clock Gating Register
address_offset : 0x1F714C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR117_CLR

CCM Clock Gating Register
address_offset : 0x1F7328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR117_TOG

CCM Clock Gating Register
address_offset : 0x1F7504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR118

CCM Clock Gating Register
address_offset : 0x1FB6D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR118_SET

CCM Clock Gating Register
address_offset : 0x1FB8B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR118_CLR

CCM Clock Gating Register
address_offset : 0x1FBA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR118_TOG

CCM Clock Gating Register
address_offset : 0x1FBC70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR119

CCM Clock Gating Register
address_offset : 0x1FFE40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR119_SET

CCM Clock Gating Register
address_offset : 0x200024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR119_CLR

CCM Clock Gating Register
address_offset : 0x200208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR119_TOG

CCM Clock Gating Register
address_offset : 0x2003EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR6

CCM Clock Gating Register
address_offset : 0x20150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR6_SET

CCM Clock Gating Register
address_offset : 0x20170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR6_CLR

CCM Clock Gating Register
address_offset : 0x20190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR6_TOG

CCM Clock Gating Register
address_offset : 0x201B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL2

CCM PLL Control Register
address_offset : 0x2030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL2_SET

CCM PLL Control Register
address_offset : 0x2040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR120

CCM Clock Gating Register
address_offset : 0x2045C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR120_SET

CCM Clock Gating Register
address_offset : 0x2047A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR120_CLR

CCM Clock Gating Register
address_offset : 0x204990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR120_TOG

CCM Clock Gating Register
address_offset : 0x204B78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL2_CLR

CCM PLL Control Register
address_offset : 0x2050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL2_TOG

CCM PLL Control Register
address_offset : 0x2060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR121

CCM Clock Gating Register
address_offset : 0x208D50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR121_SET

CCM Clock Gating Register
address_offset : 0x208F3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR121_CLR

CCM Clock Gating Register
address_offset : 0x209128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR121_TOG

CCM Clock Gating Register
address_offset : 0x209314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR122

CCM Clock Gating Register
address_offset : 0x20D4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR122_SET

CCM Clock Gating Register
address_offset : 0x20D6E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR122_CLR

CCM Clock Gating Register
address_offset : 0x20D8D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR122_TOG

CCM Clock Gating Register
address_offset : 0x20DAC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR123

CCM Clock Gating Register
address_offset : 0x211CA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR123_SET

CCM Clock Gating Register
address_offset : 0x211E94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR123_CLR

CCM Clock Gating Register
address_offset : 0x212088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR123_TOG

CCM Clock Gating Register
address_offset : 0x21227C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR124

CCM Clock Gating Register
address_offset : 0x216460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR124_SET

CCM Clock Gating Register
address_offset : 0x216658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR124_CLR

CCM Clock Gating Register
address_offset : 0x216850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR124_TOG

CCM Clock Gating Register
address_offset : 0x216A48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR125

CCM Clock Gating Register
address_offset : 0x21AC30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR125_SET

CCM Clock Gating Register
address_offset : 0x21AE2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR125_CLR

CCM Clock Gating Register
address_offset : 0x21B028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR125_TOG

CCM Clock Gating Register
address_offset : 0x21B224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR126

CCM Clock Gating Register
address_offset : 0x21F410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR126_SET

CCM Clock Gating Register
address_offset : 0x21F610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR126_CLR

CCM Clock Gating Register
address_offset : 0x21F810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR126_TOG

CCM Clock Gating Register
address_offset : 0x21FA10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR127

CCM Clock Gating Register
address_offset : 0x223C00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR127_SET

CCM Clock Gating Register
address_offset : 0x223E04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR127_CLR

CCM Clock Gating Register
address_offset : 0x224008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR127_TOG

CCM Clock Gating Register
address_offset : 0x22420C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR128

CCM Clock Gating Register
address_offset : 0x228400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR128_SET

CCM Clock Gating Register
address_offset : 0x228608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR128_CLR

CCM Clock Gating Register
address_offset : 0x228810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR128_TOG

CCM Clock Gating Register
address_offset : 0x228A18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR129

CCM Clock Gating Register
address_offset : 0x22CC10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR129_SET

CCM Clock Gating Register
address_offset : 0x22CE1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR129_CLR

CCM Clock Gating Register
address_offset : 0x22D028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR129_TOG

CCM Clock Gating Register
address_offset : 0x22D234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR130

CCM Clock Gating Register
address_offset : 0x231430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR130_SET

CCM Clock Gating Register
address_offset : 0x231640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR130_CLR

CCM Clock Gating Register
address_offset : 0x231850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR130_TOG

CCM Clock Gating Register
address_offset : 0x231A60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR131

CCM Clock Gating Register
address_offset : 0x235C60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR131_SET

CCM Clock Gating Register
address_offset : 0x235E74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR131_CLR

CCM Clock Gating Register
address_offset : 0x236088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR131_TOG

CCM Clock Gating Register
address_offset : 0x23629C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR132

CCM Clock Gating Register
address_offset : 0x23A4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR132_SET

CCM Clock Gating Register
address_offset : 0x23A6B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR132_CLR

CCM Clock Gating Register
address_offset : 0x23A8D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR132_TOG

CCM Clock Gating Register
address_offset : 0x23AAE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR133

CCM Clock Gating Register
address_offset : 0x23ECF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR133_SET

CCM Clock Gating Register
address_offset : 0x23EF0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR133_CLR

CCM Clock Gating Register
address_offset : 0x23F128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR133_TOG

CCM Clock Gating Register
address_offset : 0x23F344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR7

CCM Clock Gating Register
address_offset : 0x241C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR7_SET

CCM Clock Gating Register
address_offset : 0x241E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR7_CLR

CCM Clock Gating Register
address_offset : 0x24208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR7_TOG

CCM Clock Gating Register
address_offset : 0x2422C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR134

CCM Clock Gating Register
address_offset : 0x243550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR134_SET

CCM Clock Gating Register
address_offset : 0x243770 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR134_CLR

CCM Clock Gating Register
address_offset : 0x243990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR134_TOG

CCM Clock Gating Register
address_offset : 0x243BB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR135

CCM Clock Gating Register
address_offset : 0x247DC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR135_SET

CCM Clock Gating Register
address_offset : 0x247FE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR135_CLR

CCM Clock Gating Register
address_offset : 0x248208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR135_TOG

CCM Clock Gating Register
address_offset : 0x24842C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR136

CCM Clock Gating Register
address_offset : 0x24C640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR136_SET

CCM Clock Gating Register
address_offset : 0x24C868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR136_CLR

CCM Clock Gating Register
address_offset : 0x24CA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR136_TOG

CCM Clock Gating Register
address_offset : 0x24CCB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR137

CCM Clock Gating Register
address_offset : 0x250ED0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR137_SET

CCM Clock Gating Register
address_offset : 0x2510FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR137_CLR

CCM Clock Gating Register
address_offset : 0x251328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR137_TOG

CCM Clock Gating Register
address_offset : 0x251554 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR138

CCM Clock Gating Register
address_offset : 0x255770 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR138_SET

CCM Clock Gating Register
address_offset : 0x2559A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR138_CLR

CCM Clock Gating Register
address_offset : 0x255BD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR138_TOG

CCM Clock Gating Register
address_offset : 0x255E00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR139

CCM Clock Gating Register
address_offset : 0x25A020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR139_SET

CCM Clock Gating Register
address_offset : 0x25A254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR139_CLR

CCM Clock Gating Register
address_offset : 0x25A488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR139_TOG

CCM Clock Gating Register
address_offset : 0x25A6BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR140

CCM Clock Gating Register
address_offset : 0x25E8E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR140_SET

CCM Clock Gating Register
address_offset : 0x25EB18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR140_CLR

CCM Clock Gating Register
address_offset : 0x25ED50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR140_TOG

CCM Clock Gating Register
address_offset : 0x25EF88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR141

CCM Clock Gating Register
address_offset : 0x2631B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR141_SET

CCM Clock Gating Register
address_offset : 0x2633EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR141_CLR

CCM Clock Gating Register
address_offset : 0x263628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR141_TOG

CCM Clock Gating Register
address_offset : 0x263864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR142

CCM Clock Gating Register
address_offset : 0x267A90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR142_SET

CCM Clock Gating Register
address_offset : 0x267CD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR142_CLR

CCM Clock Gating Register
address_offset : 0x267F10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR142_TOG

CCM Clock Gating Register
address_offset : 0x268150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR143

CCM Clock Gating Register
address_offset : 0x26C380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR143_SET

CCM Clock Gating Register
address_offset : 0x26C5C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR143_CLR

CCM Clock Gating Register
address_offset : 0x26C808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR143_TOG

CCM Clock Gating Register
address_offset : 0x26CA4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR144

CCM Clock Gating Register
address_offset : 0x270C80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR144_SET

CCM Clock Gating Register
address_offset : 0x270EC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR144_CLR

CCM Clock Gating Register
address_offset : 0x271110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR144_TOG

CCM Clock Gating Register
address_offset : 0x271358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR145

CCM Clock Gating Register
address_offset : 0x275590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR145_SET

CCM Clock Gating Register
address_offset : 0x2757DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR145_CLR

CCM Clock Gating Register
address_offset : 0x275A28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR145_TOG

CCM Clock Gating Register
address_offset : 0x275C74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR146

CCM Clock Gating Register
address_offset : 0x279EB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR146_SET

CCM Clock Gating Register
address_offset : 0x27A100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR146_CLR

CCM Clock Gating Register
address_offset : 0x27A350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR146_TOG

CCM Clock Gating Register
address_offset : 0x27A5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR147

CCM Clock Gating Register
address_offset : 0x27E7E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR147_SET

CCM Clock Gating Register
address_offset : 0x27EA34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR147_CLR

CCM Clock Gating Register
address_offset : 0x27EC88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR147_TOG

CCM Clock Gating Register
address_offset : 0x27EEDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR8

CCM Clock Gating Register
address_offset : 0x28240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR8_SET

CCM Clock Gating Register
address_offset : 0x28268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR8_CLR

CCM Clock Gating Register
address_offset : 0x28290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR8_TOG

CCM Clock Gating Register
address_offset : 0x282B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR148

CCM Clock Gating Register
address_offset : 0x283120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR148_SET

CCM Clock Gating Register
address_offset : 0x283378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR148_CLR

CCM Clock Gating Register
address_offset : 0x2835D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR148_TOG

CCM Clock Gating Register
address_offset : 0x283828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL3

CCM PLL Control Register
address_offset : 0x2860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL3_SET

CCM PLL Control Register
address_offset : 0x2874 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR149

CCM Clock Gating Register
address_offset : 0x287A70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR149_SET

CCM Clock Gating Register
address_offset : 0x287CCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR149_CLR

CCM Clock Gating Register
address_offset : 0x287F28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR149_TOG

CCM Clock Gating Register
address_offset : 0x288184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL3_CLR

CCM PLL Control Register
address_offset : 0x2888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL3_TOG

CCM PLL Control Register
address_offset : 0x289C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR150

CCM Clock Gating Register
address_offset : 0x28C3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR150_SET

CCM Clock Gating Register
address_offset : 0x28C630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR150_CLR

CCM Clock Gating Register
address_offset : 0x28C890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR150_TOG

CCM Clock Gating Register
address_offset : 0x28CAF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR151

CCM Clock Gating Register
address_offset : 0x290D40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR151_SET

CCM Clock Gating Register
address_offset : 0x290FA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR151_CLR

CCM Clock Gating Register
address_offset : 0x291208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR151_TOG

CCM Clock Gating Register
address_offset : 0x29146C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR152

CCM Clock Gating Register
address_offset : 0x2956C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR152_SET

CCM Clock Gating Register
address_offset : 0x295928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR152_CLR

CCM Clock Gating Register
address_offset : 0x295B90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR152_TOG

CCM Clock Gating Register
address_offset : 0x295DF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR153

CCM Clock Gating Register
address_offset : 0x29A050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR153_SET

CCM Clock Gating Register
address_offset : 0x29A2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR153_CLR

CCM Clock Gating Register
address_offset : 0x29A528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR153_TOG

CCM Clock Gating Register
address_offset : 0x29A794 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR154

CCM Clock Gating Register
address_offset : 0x29E9F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR154_SET

CCM Clock Gating Register
address_offset : 0x29EC60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR154_CLR

CCM Clock Gating Register
address_offset : 0x29EED0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR154_TOG

CCM Clock Gating Register
address_offset : 0x29F140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR155

CCM Clock Gating Register
address_offset : 0x2A33A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR155_SET

CCM Clock Gating Register
address_offset : 0x2A3614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR155_CLR

CCM Clock Gating Register
address_offset : 0x2A3888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR155_TOG

CCM Clock Gating Register
address_offset : 0x2A3AFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR156

CCM Clock Gating Register
address_offset : 0x2A7D60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR156_SET

CCM Clock Gating Register
address_offset : 0x2A7FD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR156_CLR

CCM Clock Gating Register
address_offset : 0x2A8250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR156_TOG

CCM Clock Gating Register
address_offset : 0x2A84C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR157

CCM Clock Gating Register
address_offset : 0x2AC730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR157_SET

CCM Clock Gating Register
address_offset : 0x2AC9AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR157_CLR

CCM Clock Gating Register
address_offset : 0x2ACC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR157_TOG

CCM Clock Gating Register
address_offset : 0x2ACEA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR158

CCM Clock Gating Register
address_offset : 0x2B1110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR158_SET

CCM Clock Gating Register
address_offset : 0x2B1390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR158_CLR

CCM Clock Gating Register
address_offset : 0x2B1610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR158_TOG

CCM Clock Gating Register
address_offset : 0x2B1890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR159

CCM Clock Gating Register
address_offset : 0x2B5B00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR159_SET

CCM Clock Gating Register
address_offset : 0x2B5D84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR159_CLR

CCM Clock Gating Register
address_offset : 0x2B6008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR159_TOG

CCM Clock Gating Register
address_offset : 0x2B628C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR160

CCM Clock Gating Register
address_offset : 0x2BA500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR160_SET

CCM Clock Gating Register
address_offset : 0x2BA788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR160_CLR

CCM Clock Gating Register
address_offset : 0x2BAA10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR160_TOG

CCM Clock Gating Register
address_offset : 0x2BAC98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR161

CCM Clock Gating Register
address_offset : 0x2BEF10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR161_SET

CCM Clock Gating Register
address_offset : 0x2BF19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR161_CLR

CCM Clock Gating Register
address_offset : 0x2BF428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR161_TOG

CCM Clock Gating Register
address_offset : 0x2BF6B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR9

CCM Clock Gating Register
address_offset : 0x2C2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR9_SET

CCM Clock Gating Register
address_offset : 0x2C2FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR9_CLR

CCM Clock Gating Register
address_offset : 0x2C328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR9_TOG

CCM Clock Gating Register
address_offset : 0x2C354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR162

CCM Clock Gating Register
address_offset : 0x2C3930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR162_SET

CCM Clock Gating Register
address_offset : 0x2C3BC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR162_CLR

CCM Clock Gating Register
address_offset : 0x2C3E50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR162_TOG

CCM Clock Gating Register
address_offset : 0x2C40E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR163

CCM Clock Gating Register
address_offset : 0x2C8360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR163_SET

CCM Clock Gating Register
address_offset : 0x2C85F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR163_CLR

CCM Clock Gating Register
address_offset : 0x2C8888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR163_TOG

CCM Clock Gating Register
address_offset : 0x2C8B1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR164

CCM Clock Gating Register
address_offset : 0x2CCDA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR164_SET

CCM Clock Gating Register
address_offset : 0x2CD038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR164_CLR

CCM Clock Gating Register
address_offset : 0x2CD2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR164_TOG

CCM Clock Gating Register
address_offset : 0x2CD568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR165

CCM Clock Gating Register
address_offset : 0x2D17F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR165_SET

CCM Clock Gating Register
address_offset : 0x2D1A8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR165_CLR

CCM Clock Gating Register
address_offset : 0x2D1D28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR165_TOG

CCM Clock Gating Register
address_offset : 0x2D1FC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR166

CCM Clock Gating Register
address_offset : 0x2D6250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR166_SET

CCM Clock Gating Register
address_offset : 0x2D64F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR166_CLR

CCM Clock Gating Register
address_offset : 0x2D6790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR166_TOG

CCM Clock Gating Register
address_offset : 0x2D6A30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR167

CCM Clock Gating Register
address_offset : 0x2DACC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR167_SET

CCM Clock Gating Register
address_offset : 0x2DAF64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR167_CLR

CCM Clock Gating Register
address_offset : 0x2DB208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR167_TOG

CCM Clock Gating Register
address_offset : 0x2DB4AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR168

CCM Clock Gating Register
address_offset : 0x2DF740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR168_SET

CCM Clock Gating Register
address_offset : 0x2DF9E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR168_CLR

CCM Clock Gating Register
address_offset : 0x2DFC90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR168_TOG

CCM Clock Gating Register
address_offset : 0x2DFF38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR169

CCM Clock Gating Register
address_offset : 0x2E41D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR169_SET

CCM Clock Gating Register
address_offset : 0x2E447C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR169_CLR

CCM Clock Gating Register
address_offset : 0x2E4728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR169_TOG

CCM Clock Gating Register
address_offset : 0x2E49D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR170

CCM Clock Gating Register
address_offset : 0x2E8C70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR170_SET

CCM Clock Gating Register
address_offset : 0x2E8F20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR170_CLR

CCM Clock Gating Register
address_offset : 0x2E91D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR170_TOG

CCM Clock Gating Register
address_offset : 0x2E9480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR171

CCM Clock Gating Register
address_offset : 0x2ED720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR171_SET

CCM Clock Gating Register
address_offset : 0x2ED9D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR171_CLR

CCM Clock Gating Register
address_offset : 0x2EDC88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR171_TOG

CCM Clock Gating Register
address_offset : 0x2EDF3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR172

CCM Clock Gating Register
address_offset : 0x2F21E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR172_SET

CCM Clock Gating Register
address_offset : 0x2F2498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR172_CLR

CCM Clock Gating Register
address_offset : 0x2F2750 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR172_TOG

CCM Clock Gating Register
address_offset : 0x2F2A08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR173

CCM Clock Gating Register
address_offset : 0x2F6CB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR173_SET

CCM Clock Gating Register
address_offset : 0x2F6F6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR173_CLR

CCM Clock Gating Register
address_offset : 0x2F7228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR173_TOG

CCM Clock Gating Register
address_offset : 0x2F74E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR174

CCM Clock Gating Register
address_offset : 0x2FB790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR174_SET

CCM Clock Gating Register
address_offset : 0x2FBA50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR174_CLR

CCM Clock Gating Register
address_offset : 0x2FBD10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR174_TOG

CCM Clock Gating Register
address_offset : 0x2FBFD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR175

CCM Clock Gating Register
address_offset : 0x300280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR175_SET

CCM Clock Gating Register
address_offset : 0x300544 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR175_CLR

CCM Clock Gating Register
address_offset : 0x300808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR175_TOG

CCM Clock Gating Register
address_offset : 0x300ACC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR10

CCM Clock Gating Register
address_offset : 0x30370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR10_SET

CCM Clock Gating Register
address_offset : 0x303A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR10_CLR

CCM Clock Gating Register
address_offset : 0x303D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR10_TOG

CCM Clock Gating Register
address_offset : 0x30400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR176

CCM Clock Gating Register
address_offset : 0x304D80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR176_SET

CCM Clock Gating Register
address_offset : 0x305048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR176_CLR

CCM Clock Gating Register
address_offset : 0x305310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR176_TOG

CCM Clock Gating Register
address_offset : 0x3055D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR177

CCM Clock Gating Register
address_offset : 0x309890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR177_SET

CCM Clock Gating Register
address_offset : 0x309B5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR177_CLR

CCM Clock Gating Register
address_offset : 0x309E28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL4

CCM PLL Control Register
address_offset : 0x30A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR177_TOG

CCM Clock Gating Register
address_offset : 0x30A0F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL4_SET

CCM PLL Control Register
address_offset : 0x30B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL4_CLR

CCM PLL Control Register
address_offset : 0x30D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR178

CCM Clock Gating Register
address_offset : 0x30E3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR178_SET

CCM Clock Gating Register
address_offset : 0x30E680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL4_TOG

CCM PLL Control Register
address_offset : 0x30E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR178_CLR

CCM Clock Gating Register
address_offset : 0x30E950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR178_TOG

CCM Clock Gating Register
address_offset : 0x30EC20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR179

CCM Clock Gating Register
address_offset : 0x312EE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR179_SET

CCM Clock Gating Register
address_offset : 0x3131B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR179_CLR

CCM Clock Gating Register
address_offset : 0x313488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR179_TOG

CCM Clock Gating Register
address_offset : 0x31375C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR180

CCM Clock Gating Register
address_offset : 0x317A20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR180_SET

CCM Clock Gating Register
address_offset : 0x317CF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR180_CLR

CCM Clock Gating Register
address_offset : 0x317FD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR180_TOG

CCM Clock Gating Register
address_offset : 0x3182A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR181

CCM Clock Gating Register
address_offset : 0x31C570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR181_SET

CCM Clock Gating Register
address_offset : 0x31C84C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR181_CLR

CCM Clock Gating Register
address_offset : 0x31CB28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR181_TOG

CCM Clock Gating Register
address_offset : 0x31CE04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR182

CCM Clock Gating Register
address_offset : 0x3210D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR182_SET

CCM Clock Gating Register
address_offset : 0x3213B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR182_CLR

CCM Clock Gating Register
address_offset : 0x321690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR182_TOG

CCM Clock Gating Register
address_offset : 0x321970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR183

CCM Clock Gating Register
address_offset : 0x325C40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR183_SET

CCM Clock Gating Register
address_offset : 0x325F24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR183_CLR

CCM Clock Gating Register
address_offset : 0x326208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR183_TOG

CCM Clock Gating Register
address_offset : 0x3264EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR184

CCM Clock Gating Register
address_offset : 0x32A7C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR184_SET

CCM Clock Gating Register
address_offset : 0x32AAA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR184_CLR

CCM Clock Gating Register
address_offset : 0x32AD90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR184_TOG

CCM Clock Gating Register
address_offset : 0x32B078 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR185

CCM Clock Gating Register
address_offset : 0x32F350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR185_SET

CCM Clock Gating Register
address_offset : 0x32F63C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR185_CLR

CCM Clock Gating Register
address_offset : 0x32F928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR185_TOG

CCM Clock Gating Register
address_offset : 0x32FC14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR186

CCM Clock Gating Register
address_offset : 0x333EF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR186_SET

CCM Clock Gating Register
address_offset : 0x3341E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR186_CLR

CCM Clock Gating Register
address_offset : 0x3344D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR186_TOG

CCM Clock Gating Register
address_offset : 0x3347C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR187

CCM Clock Gating Register
address_offset : 0x338AA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR187_SET

CCM Clock Gating Register
address_offset : 0x338D94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR187_CLR

CCM Clock Gating Register
address_offset : 0x339088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR187_TOG

CCM Clock Gating Register
address_offset : 0x33937C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR188

CCM Clock Gating Register
address_offset : 0x33D660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR188_SET

CCM Clock Gating Register
address_offset : 0x33D958 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR188_CLR

CCM Clock Gating Register
address_offset : 0x33DC50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR188_TOG

CCM Clock Gating Register
address_offset : 0x33DF48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR189

CCM Clock Gating Register
address_offset : 0x342230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR189_SET

CCM Clock Gating Register
address_offset : 0x34252C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR189_CLR

CCM Clock Gating Register
address_offset : 0x342828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR189_TOG

CCM Clock Gating Register
address_offset : 0x342B24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR11

CCM Clock Gating Register
address_offset : 0x34420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR11_SET

CCM Clock Gating Register
address_offset : 0x34454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR11_CLR

CCM Clock Gating Register
address_offset : 0x34488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR11_TOG

CCM Clock Gating Register
address_offset : 0x344BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR190

CCM Clock Gating Register
address_offset : 0x346E10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR190_SET

CCM Clock Gating Register
address_offset : 0x347110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR190_CLR

CCM Clock Gating Register
address_offset : 0x347410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR190_TOG

CCM Clock Gating Register
address_offset : 0x347710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR12

CCM Clock Gating Register
address_offset : 0x384E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR12_SET

CCM Clock Gating Register
address_offset : 0x38518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR12_CLR

CCM Clock Gating Register
address_offset : 0x38550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR12_TOG

CCM Clock Gating Register
address_offset : 0x38588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL5

CCM PLL Control Register
address_offset : 0x38F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL5_SET

CCM PLL Control Register
address_offset : 0x390C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL5_CLR

CCM PLL Control Register
address_offset : 0x3928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL5_TOG

CCM PLL Control Register
address_offset : 0x3944 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR13

CCM Clock Gating Register
address_offset : 0x3C5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR13_SET

CCM Clock Gating Register
address_offset : 0x3C5EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR13_CLR

CCM Clock Gating Register
address_offset : 0x3C628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR13_TOG

CCM Clock Gating Register
address_offset : 0x3C664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

GPR0_SET

General Purpose Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP0 : Timeout cycle count of ipg_clk, when perform read and write.
bits : 0 - 31 (32 bit)
access : read-write

CCGR14

CCM Clock Gating Register
address_offset : 0x40690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR14_SET

CCM Clock Gating Register
address_offset : 0x406D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR14_CLR

CCM Clock Gating Register
address_offset : 0x40710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR14_TOG

CCM Clock Gating Register
address_offset : 0x40750 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL6

CCM PLL Control Register
address_offset : 0x4150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL6_SET

CCM PLL Control Register
address_offset : 0x4170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL6_CLR

CCM PLL Control Register
address_offset : 0x4190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL6_TOG

CCM PLL Control Register
address_offset : 0x41B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR15

CCM Clock Gating Register
address_offset : 0x44780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR15_SET

CCM Clock Gating Register
address_offset : 0x447C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR15_CLR

CCM Clock Gating Register
address_offset : 0x44808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR15_TOG

CCM Clock Gating Register
address_offset : 0x4484C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR16

CCM Clock Gating Register
address_offset : 0x48880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR16_SET

CCM Clock Gating Register
address_offset : 0x488C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR16_CLR

CCM Clock Gating Register
address_offset : 0x48910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR16_TOG

CCM Clock Gating Register
address_offset : 0x48958 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL7

CCM PLL Control Register
address_offset : 0x49C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL7_SET

CCM PLL Control Register
address_offset : 0x49E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL7_CLR

CCM PLL Control Register
address_offset : 0x4A08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL7_TOG

CCM PLL Control Register
address_offset : 0x4A2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR17

CCM Clock Gating Register
address_offset : 0x4C990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR17_SET

CCM Clock Gating Register
address_offset : 0x4C9DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR17_CLR

CCM Clock Gating Register
address_offset : 0x4CA28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR17_TOG

CCM Clock Gating Register
address_offset : 0x4CA74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR18

CCM Clock Gating Register
address_offset : 0x50AB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR18_SET

CCM Clock Gating Register
address_offset : 0x50B00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR18_CLR

CCM Clock Gating Register
address_offset : 0x50B50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR18_TOG

CCM Clock Gating Register
address_offset : 0x50BA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL8

CCM PLL Control Register
address_offset : 0x5240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL8_SET

CCM PLL Control Register
address_offset : 0x5268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL8_CLR

CCM PLL Control Register
address_offset : 0x5290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL8_TOG

CCM PLL Control Register
address_offset : 0x52B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR19

CCM Clock Gating Register
address_offset : 0x54BE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR19_SET

CCM Clock Gating Register
address_offset : 0x54C34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR19_CLR

CCM Clock Gating Register
address_offset : 0x54C88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR19_TOG

CCM Clock Gating Register
address_offset : 0x54CDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR20

CCM Clock Gating Register
address_offset : 0x58D20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR20_SET

CCM Clock Gating Register
address_offset : 0x58D78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR20_CLR

CCM Clock Gating Register
address_offset : 0x58DD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR20_TOG

CCM Clock Gating Register
address_offset : 0x58E28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL9

CCM PLL Control Register
address_offset : 0x5AD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL9_SET

CCM PLL Control Register
address_offset : 0x5AFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL9_CLR

CCM PLL Control Register
address_offset : 0x5B28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL9_TOG

CCM PLL Control Register
address_offset : 0x5B54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR21

CCM Clock Gating Register
address_offset : 0x5CE70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR21_SET

CCM Clock Gating Register
address_offset : 0x5CECC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR21_CLR

CCM Clock Gating Register
address_offset : 0x5CF28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR21_TOG

CCM Clock Gating Register
address_offset : 0x5CF84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR22

CCM Clock Gating Register
address_offset : 0x60FD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR22_SET

CCM Clock Gating Register
address_offset : 0x61030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR22_CLR

CCM Clock Gating Register
address_offset : 0x61090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR22_TOG

CCM Clock Gating Register
address_offset : 0x610F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL10

CCM PLL Control Register
address_offset : 0x6370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL10_SET

CCM PLL Control Register
address_offset : 0x63A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL10_CLR

CCM PLL Control Register
address_offset : 0x63D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL10_TOG

CCM PLL Control Register
address_offset : 0x6400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR23

CCM Clock Gating Register
address_offset : 0x65140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR23_SET

CCM Clock Gating Register
address_offset : 0x651A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR23_CLR

CCM Clock Gating Register
address_offset : 0x65208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR23_TOG

CCM Clock Gating Register
address_offset : 0x6526C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR24

CCM Clock Gating Register
address_offset : 0x692C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR24_SET

CCM Clock Gating Register
address_offset : 0x69328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR24_CLR

CCM Clock Gating Register
address_offset : 0x69390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR24_TOG

CCM Clock Gating Register
address_offset : 0x693F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL11

CCM PLL Control Register
address_offset : 0x6C20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL11_SET

CCM PLL Control Register
address_offset : 0x6C54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL11_CLR

CCM PLL Control Register
address_offset : 0x6C88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL11_TOG

CCM PLL Control Register
address_offset : 0x6CBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR25

CCM Clock Gating Register
address_offset : 0x6D450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR25_SET

CCM Clock Gating Register
address_offset : 0x6D4BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR25_CLR

CCM Clock Gating Register
address_offset : 0x6D528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR25_TOG

CCM Clock Gating Register
address_offset : 0x6D594 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR26

CCM Clock Gating Register
address_offset : 0x715F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR26_SET

CCM Clock Gating Register
address_offset : 0x71660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR26_CLR

CCM Clock Gating Register
address_offset : 0x716D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR26_TOG

CCM Clock Gating Register
address_offset : 0x71740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL12

CCM PLL Control Register
address_offset : 0x74E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL12_SET

CCM PLL Control Register
address_offset : 0x7518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL12_CLR

CCM PLL Control Register
address_offset : 0x7550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR27

CCM Clock Gating Register
address_offset : 0x757A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR27_SET

CCM Clock Gating Register
address_offset : 0x75814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL12_TOG

CCM PLL Control Register
address_offset : 0x7588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR27_CLR

CCM Clock Gating Register
address_offset : 0x75888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR27_TOG

CCM Clock Gating Register
address_offset : 0x758FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR28

CCM Clock Gating Register
address_offset : 0x79960 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR28_SET

CCM Clock Gating Register
address_offset : 0x799D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR28_CLR

CCM Clock Gating Register
address_offset : 0x79A50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR28_TOG

CCM Clock Gating Register
address_offset : 0x79AC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL13

CCM PLL Control Register
address_offset : 0x7DB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR29

CCM Clock Gating Register
address_offset : 0x7DB30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR29_SET

CCM Clock Gating Register
address_offset : 0x7DBAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR29_CLR

CCM Clock Gating Register
address_offset : 0x7DC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR29_TOG

CCM Clock Gating Register
address_offset : 0x7DCA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL13_SET

CCM PLL Control Register
address_offset : 0x7DEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL13_CLR

CCM PLL Control Register
address_offset : 0x7E28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL13_TOG

CCM PLL Control Register
address_offset : 0x7E64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

GPR0_CLR

General Purpose Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP0 : Timeout cycle count of ipg_clk, when perform read and write.
bits : 0 - 31 (32 bit)
access : read-write

CCGR0

CCM Clock Gating Register
address_offset : 0x8000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

TARGET_ROOT0

Target Register
address_offset : 0x8000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT0_SET

Target Register
address_offset : 0x8004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

CCGR0_SET

CCM Clock Gating Register
address_offset : 0x8008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

TARGET_ROOT0_CLR

Target Register
address_offset : 0x8008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT0_TOG

Target Register
address_offset : 0x800C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

CCGR0_CLR

CCM Clock Gating Register
address_offset : 0x8010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

MISC0

Miscellaneous Register
address_offset : 0x8010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT0_SET

Miscellaneous Register
address_offset : 0x8014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

CCGR0_TOG

CCM Clock Gating Register
address_offset : 0x8018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

MISC_ROOT0_CLR

Miscellaneous Register
address_offset : 0x8018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT0_TOG

Miscellaneous Register
address_offset : 0x801C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST0

Post Divider Register
address_offset : 0x8020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT0_SET

Post Divider Register
address_offset : 0x8024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT0_CLR

Post Divider Register
address_offset : 0x8028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT0_TOG

Post Divider Register
address_offset : 0x802C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE0

Pre Divider Register
address_offset : 0x8030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT0_SET

Pre Divider Register
address_offset : 0x8034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT0_CLR

Pre Divider Register
address_offset : 0x8038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT0_TOG

Pre Divider Register
address_offset : 0x803C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL0

Access Control Register
address_offset : 0x8070 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT0_SET

Access Control Register
address_offset : 0x8074 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT0_CLR

Access Control Register
address_offset : 0x8078 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT0_TOG

Access Control Register
address_offset : 0x807C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT1

Target Register
address_offset : 0x8080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT1_SET

Target Register
address_offset : 0x8084 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT1_CLR

Target Register
address_offset : 0x8088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT1_TOG

Target Register
address_offset : 0x808C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC1

Miscellaneous Register
address_offset : 0x8090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT1_SET

Miscellaneous Register
address_offset : 0x8094 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT1_CLR

Miscellaneous Register
address_offset : 0x8098 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT1_TOG

Miscellaneous Register
address_offset : 0x809C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST1

Post Divider Register
address_offset : 0x80A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT1_SET

Post Divider Register
address_offset : 0x80A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT1_CLR

Post Divider Register
address_offset : 0x80A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT1_TOG

Post Divider Register
address_offset : 0x80AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE1

Pre Divider Register
address_offset : 0x80B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT1_SET

Pre Divider Register
address_offset : 0x80B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT1_CLR

Pre Divider Register
address_offset : 0x80B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT1_TOG

Pre Divider Register
address_offset : 0x80BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL1

Access Control Register
address_offset : 0x80F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT1_SET

Access Control Register
address_offset : 0x80F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT1_CLR

Access Control Register
address_offset : 0x80F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT1_TOG

Access Control Register
address_offset : 0x80FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT2

Target Register
address_offset : 0x8100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT2_SET

Target Register
address_offset : 0x8104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT2_CLR

Target Register
address_offset : 0x8108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT2_TOG

Target Register
address_offset : 0x810C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC2

Miscellaneous Register
address_offset : 0x8110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT2_SET

Miscellaneous Register
address_offset : 0x8114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT2_CLR

Miscellaneous Register
address_offset : 0x8118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT2_TOG

Miscellaneous Register
address_offset : 0x811C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST2

Post Divider Register
address_offset : 0x8120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT2_SET

Post Divider Register
address_offset : 0x8124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT2_CLR

Post Divider Register
address_offset : 0x8128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT2_TOG

Post Divider Register
address_offset : 0x812C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE2

Pre Divider Register
address_offset : 0x8130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT2_SET

Pre Divider Register
address_offset : 0x8134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT2_CLR

Pre Divider Register
address_offset : 0x8138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT2_TOG

Pre Divider Register
address_offset : 0x813C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL2

Access Control Register
address_offset : 0x8170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT2_SET

Access Control Register
address_offset : 0x8174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT2_CLR

Access Control Register
address_offset : 0x8178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT2_TOG

Access Control Register
address_offset : 0x817C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT3

Target Register
address_offset : 0x8180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT3_SET

Target Register
address_offset : 0x8184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT3_CLR

Target Register
address_offset : 0x8188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT3_TOG

Target Register
address_offset : 0x818C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC3

Miscellaneous Register
address_offset : 0x8190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT3_SET

Miscellaneous Register
address_offset : 0x8194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT3_CLR

Miscellaneous Register
address_offset : 0x8198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT3_TOG

Miscellaneous Register
address_offset : 0x819C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST3

Post Divider Register
address_offset : 0x81A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT3_SET

Post Divider Register
address_offset : 0x81A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT3_CLR

Post Divider Register
address_offset : 0x81A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT3_TOG

Post Divider Register
address_offset : 0x81AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE3

Pre Divider Register
address_offset : 0x81B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT3_SET

Pre Divider Register
address_offset : 0x81B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT3_CLR

Pre Divider Register
address_offset : 0x81B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT3_TOG

Pre Divider Register
address_offset : 0x81BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

CCGR30

CCM Clock Gating Register
address_offset : 0x81D10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR30_SET

CCM Clock Gating Register
address_offset : 0x81D90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR30_CLR

CCM Clock Gating Register
address_offset : 0x81E10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR30_TOG

CCM Clock Gating Register
address_offset : 0x81E90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL3

Access Control Register
address_offset : 0x81F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT3_SET

Access Control Register
address_offset : 0x81F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT3_CLR

Access Control Register
address_offset : 0x81F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT3_TOG

Access Control Register
address_offset : 0x81FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT4

Target Register
address_offset : 0x8200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT4_SET

Target Register
address_offset : 0x8204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT4_CLR

Target Register
address_offset : 0x8208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT4_TOG

Target Register
address_offset : 0x820C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC4

Miscellaneous Register
address_offset : 0x8210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT4_SET

Miscellaneous Register
address_offset : 0x8214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT4_CLR

Miscellaneous Register
address_offset : 0x8218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT4_TOG

Miscellaneous Register
address_offset : 0x821C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST4

Post Divider Register
address_offset : 0x8220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT4_SET

Post Divider Register
address_offset : 0x8224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT4_CLR

Post Divider Register
address_offset : 0x8228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT4_TOG

Post Divider Register
address_offset : 0x822C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE4

Pre Divider Register
address_offset : 0x8230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT4_SET

Pre Divider Register
address_offset : 0x8234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT4_CLR

Pre Divider Register
address_offset : 0x8238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT4_TOG

Pre Divider Register
address_offset : 0x823C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL4

Access Control Register
address_offset : 0x8270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT4_SET

Access Control Register
address_offset : 0x8274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT4_CLR

Access Control Register
address_offset : 0x8278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT4_TOG

Access Control Register
address_offset : 0x827C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

CCGR31

CCM Clock Gating Register
address_offset : 0x85F00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR31_SET

CCM Clock Gating Register
address_offset : 0x85F84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR31_CLR

CCM Clock Gating Register
address_offset : 0x86008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR31_TOG

CCM Clock Gating Register
address_offset : 0x8608C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL14

CCM PLL Control Register
address_offset : 0x8690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL14_SET

CCM PLL Control Register
address_offset : 0x86D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL14_CLR

CCM PLL Control Register
address_offset : 0x8710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL14_TOG

CCM PLL Control Register
address_offset : 0x8750 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

TARGET_ROOT16

Target Register
address_offset : 0x8800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT16_SET

Target Register
address_offset : 0x8804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT16_CLR

Target Register
address_offset : 0x8808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT16_TOG

Target Register
address_offset : 0x880C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC16

Miscellaneous Register
address_offset : 0x8810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT16_SET

Miscellaneous Register
address_offset : 0x8814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT16_CLR

Miscellaneous Register
address_offset : 0x8818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT16_TOG

Miscellaneous Register
address_offset : 0x881C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST16

Post Divider Register
address_offset : 0x8820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT16_SET

Post Divider Register
address_offset : 0x8824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT16_CLR

Post Divider Register
address_offset : 0x8828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT16_TOG

Post Divider Register
address_offset : 0x882C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE16

Pre Divider Register
address_offset : 0x8830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT16_SET

Pre Divider Register
address_offset : 0x8834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT16_CLR

Pre Divider Register
address_offset : 0x8838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT16_TOG

Pre Divider Register
address_offset : 0x883C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL16

Access Control Register
address_offset : 0x8870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT16_SET

Access Control Register
address_offset : 0x8874 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT16_CLR

Access Control Register
address_offset : 0x8878 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT16_TOG

Access Control Register
address_offset : 0x887C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT17

Target Register
address_offset : 0x8880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT17_SET

Target Register
address_offset : 0x8884 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT17_CLR

Target Register
address_offset : 0x8888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT17_TOG

Target Register
address_offset : 0x888C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC17

Miscellaneous Register
address_offset : 0x8890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT17_SET

Miscellaneous Register
address_offset : 0x8894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT17_CLR

Miscellaneous Register
address_offset : 0x8898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT17_TOG

Miscellaneous Register
address_offset : 0x889C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST17

Post Divider Register
address_offset : 0x88A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT17_SET

Post Divider Register
address_offset : 0x88A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT17_CLR

Post Divider Register
address_offset : 0x88A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT17_TOG

Post Divider Register
address_offset : 0x88AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE17

Pre Divider Register
address_offset : 0x88B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT17_SET

Pre Divider Register
address_offset : 0x88B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT17_CLR

Pre Divider Register
address_offset : 0x88B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT17_TOG

Pre Divider Register
address_offset : 0x88BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL17

Access Control Register
address_offset : 0x88F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT17_SET

Access Control Register
address_offset : 0x88F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT17_CLR

Access Control Register
address_offset : 0x88F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT17_TOG

Access Control Register
address_offset : 0x88FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT18

Target Register
address_offset : 0x8900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT18_SET

Target Register
address_offset : 0x8904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT18_CLR

Target Register
address_offset : 0x8908 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT18_TOG

Target Register
address_offset : 0x890C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC18

Miscellaneous Register
address_offset : 0x8910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT18_SET

Miscellaneous Register
address_offset : 0x8914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT18_CLR

Miscellaneous Register
address_offset : 0x8918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT18_TOG

Miscellaneous Register
address_offset : 0x891C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST18

Post Divider Register
address_offset : 0x8920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT18_SET

Post Divider Register
address_offset : 0x8924 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT18_CLR

Post Divider Register
address_offset : 0x8928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT18_TOG

Post Divider Register
address_offset : 0x892C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE18

Pre Divider Register
address_offset : 0x8930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT18_SET

Pre Divider Register
address_offset : 0x8934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT18_CLR

Pre Divider Register
address_offset : 0x8938 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT18_TOG

Pre Divider Register
address_offset : 0x893C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL18

Access Control Register
address_offset : 0x8970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT18_SET

Access Control Register
address_offset : 0x8974 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT18_CLR

Access Control Register
address_offset : 0x8978 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT18_TOG

Access Control Register
address_offset : 0x897C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT19

Target Register
address_offset : 0x8980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT19_SET

Target Register
address_offset : 0x8984 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT19_CLR

Target Register
address_offset : 0x8988 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT19_TOG

Target Register
address_offset : 0x898C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC19

Miscellaneous Register
address_offset : 0x8990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT19_SET

Miscellaneous Register
address_offset : 0x8994 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT19_CLR

Miscellaneous Register
address_offset : 0x8998 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT19_TOG

Miscellaneous Register
address_offset : 0x899C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST19

Post Divider Register
address_offset : 0x89A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT19_SET

Post Divider Register
address_offset : 0x89A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT19_CLR

Post Divider Register
address_offset : 0x89A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT19_TOG

Post Divider Register
address_offset : 0x89AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE19

Pre Divider Register
address_offset : 0x89B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT19_SET

Pre Divider Register
address_offset : 0x89B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT19_CLR

Pre Divider Register
address_offset : 0x89B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT19_TOG

Pre Divider Register
address_offset : 0x89BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL19

Access Control Register
address_offset : 0x89F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT19_SET

Access Control Register
address_offset : 0x89F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT19_CLR

Access Control Register
address_offset : 0x89F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT19_TOG

Access Control Register
address_offset : 0x89FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT20

Target Register
address_offset : 0x8A00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT20_SET

Target Register
address_offset : 0x8A04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT20_CLR

Target Register
address_offset : 0x8A08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT20_TOG

Target Register
address_offset : 0x8A0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC20

Miscellaneous Register
address_offset : 0x8A10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

CCGR32

CCM Clock Gating Register
address_offset : 0x8A100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

MISC_ROOT20_SET

Miscellaneous Register
address_offset : 0x8A14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT20_CLR

Miscellaneous Register
address_offset : 0x8A18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

CCGR32_SET

CCM Clock Gating Register
address_offset : 0x8A188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

MISC_ROOT20_TOG

Miscellaneous Register
address_offset : 0x8A1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST20

Post Divider Register
address_offset : 0x8A20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

CCGR32_CLR

CCM Clock Gating Register
address_offset : 0x8A210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

POST_ROOT20_SET

Post Divider Register
address_offset : 0x8A24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT20_CLR

Post Divider Register
address_offset : 0x8A28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

CCGR32_TOG

CCM Clock Gating Register
address_offset : 0x8A298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

POST_ROOT20_TOG

Post Divider Register
address_offset : 0x8A2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE20

Pre Divider Register
address_offset : 0x8A30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT20_SET

Pre Divider Register
address_offset : 0x8A34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT20_CLR

Pre Divider Register
address_offset : 0x8A38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT20_TOG

Pre Divider Register
address_offset : 0x8A3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL20

Access Control Register
address_offset : 0x8A70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT20_SET

Access Control Register
address_offset : 0x8A74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT20_CLR

Access Control Register
address_offset : 0x8A78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT20_TOG

Access Control Register
address_offset : 0x8A7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT21

Target Register
address_offset : 0x8A80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT21_SET

Target Register
address_offset : 0x8A84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT21_CLR

Target Register
address_offset : 0x8A88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT21_TOG

Target Register
address_offset : 0x8A8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC21

Miscellaneous Register
address_offset : 0x8A90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT21_SET

Miscellaneous Register
address_offset : 0x8A94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT21_CLR

Miscellaneous Register
address_offset : 0x8A98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT21_TOG

Miscellaneous Register
address_offset : 0x8A9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST21

Post Divider Register
address_offset : 0x8AA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT21_SET

Post Divider Register
address_offset : 0x8AA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT21_CLR

Post Divider Register
address_offset : 0x8AA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT21_TOG

Post Divider Register
address_offset : 0x8AAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE21

Pre Divider Register
address_offset : 0x8AB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT21_SET

Pre Divider Register
address_offset : 0x8AB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT21_CLR

Pre Divider Register
address_offset : 0x8AB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT21_TOG

Pre Divider Register
address_offset : 0x8ABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL21

Access Control Register
address_offset : 0x8AF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT21_SET

Access Control Register
address_offset : 0x8AF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT21_CLR

Access Control Register
address_offset : 0x8AF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT21_TOG

Access Control Register
address_offset : 0x8AFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT22

Target Register
address_offset : 0x8B00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT22_SET

Target Register
address_offset : 0x8B04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT22_CLR

Target Register
address_offset : 0x8B08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT22_TOG

Target Register
address_offset : 0x8B0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC22

Miscellaneous Register
address_offset : 0x8B10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT22_SET

Miscellaneous Register
address_offset : 0x8B14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT22_CLR

Miscellaneous Register
address_offset : 0x8B18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT22_TOG

Miscellaneous Register
address_offset : 0x8B1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST22

Post Divider Register
address_offset : 0x8B20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT22_SET

Post Divider Register
address_offset : 0x8B24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT22_CLR

Post Divider Register
address_offset : 0x8B28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT22_TOG

Post Divider Register
address_offset : 0x8B2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE22

Pre Divider Register
address_offset : 0x8B30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT22_SET

Pre Divider Register
address_offset : 0x8B34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT22_CLR

Pre Divider Register
address_offset : 0x8B38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT22_TOG

Pre Divider Register
address_offset : 0x8B3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL22

Access Control Register
address_offset : 0x8B70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT22_SET

Access Control Register
address_offset : 0x8B74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT22_CLR

Access Control Register
address_offset : 0x8B78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT22_TOG

Access Control Register
address_offset : 0x8B7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT23

Target Register
address_offset : 0x8B80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT23_SET

Target Register
address_offset : 0x8B84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT23_CLR

Target Register
address_offset : 0x8B88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT23_TOG

Target Register
address_offset : 0x8B8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC23

Miscellaneous Register
address_offset : 0x8B90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT23_SET

Miscellaneous Register
address_offset : 0x8B94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT23_CLR

Miscellaneous Register
address_offset : 0x8B98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT23_TOG

Miscellaneous Register
address_offset : 0x8B9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST23

Post Divider Register
address_offset : 0x8BA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT23_SET

Post Divider Register
address_offset : 0x8BA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT23_CLR

Post Divider Register
address_offset : 0x8BA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT23_TOG

Post Divider Register
address_offset : 0x8BAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE23

Pre Divider Register
address_offset : 0x8BB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT23_SET

Pre Divider Register
address_offset : 0x8BB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT23_CLR

Pre Divider Register
address_offset : 0x8BB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT23_TOG

Pre Divider Register
address_offset : 0x8BBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL23

Access Control Register
address_offset : 0x8BF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT23_SET

Access Control Register
address_offset : 0x8BF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT23_CLR

Access Control Register
address_offset : 0x8BF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT23_TOG

Access Control Register
address_offset : 0x8BFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT24

Target Register
address_offset : 0x8C00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT24_SET

Target Register
address_offset : 0x8C04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT24_CLR

Target Register
address_offset : 0x8C08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT24_TOG

Target Register
address_offset : 0x8C0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC24

Miscellaneous Register
address_offset : 0x8C10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT24_SET

Miscellaneous Register
address_offset : 0x8C14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT24_CLR

Miscellaneous Register
address_offset : 0x8C18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT24_TOG

Miscellaneous Register
address_offset : 0x8C1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST24

Post Divider Register
address_offset : 0x8C20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT24_SET

Post Divider Register
address_offset : 0x8C24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT24_CLR

Post Divider Register
address_offset : 0x8C28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT24_TOG

Post Divider Register
address_offset : 0x8C2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE24

Pre Divider Register
address_offset : 0x8C30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT24_SET

Pre Divider Register
address_offset : 0x8C34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT24_CLR

Pre Divider Register
address_offset : 0x8C38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT24_TOG

Pre Divider Register
address_offset : 0x8C3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL24

Access Control Register
address_offset : 0x8C70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT24_SET

Access Control Register
address_offset : 0x8C74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT24_CLR

Access Control Register
address_offset : 0x8C78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT24_TOG

Access Control Register
address_offset : 0x8C7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT25

Target Register
address_offset : 0x8C80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT25_SET

Target Register
address_offset : 0x8C84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT25_CLR

Target Register
address_offset : 0x8C88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT25_TOG

Target Register
address_offset : 0x8C8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC25

Miscellaneous Register
address_offset : 0x8C90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT25_SET

Miscellaneous Register
address_offset : 0x8C94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT25_CLR

Miscellaneous Register
address_offset : 0x8C98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT25_TOG

Miscellaneous Register
address_offset : 0x8C9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST25

Post Divider Register
address_offset : 0x8CA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT25_SET

Post Divider Register
address_offset : 0x8CA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT25_CLR

Post Divider Register
address_offset : 0x8CA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT25_TOG

Post Divider Register
address_offset : 0x8CAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE25

Pre Divider Register
address_offset : 0x8CB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT25_SET

Pre Divider Register
address_offset : 0x8CB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT25_CLR

Pre Divider Register
address_offset : 0x8CB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT25_TOG

Pre Divider Register
address_offset : 0x8CBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL25

Access Control Register
address_offset : 0x8CF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT25_SET

Access Control Register
address_offset : 0x8CF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT25_CLR

Access Control Register
address_offset : 0x8CF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT25_TOG

Access Control Register
address_offset : 0x8CFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT26

Target Register
address_offset : 0x8D00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT26_SET

Target Register
address_offset : 0x8D04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT26_CLR

Target Register
address_offset : 0x8D08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT26_TOG

Target Register
address_offset : 0x8D0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC26

Miscellaneous Register
address_offset : 0x8D10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT26_SET

Miscellaneous Register
address_offset : 0x8D14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT26_CLR

Miscellaneous Register
address_offset : 0x8D18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT26_TOG

Miscellaneous Register
address_offset : 0x8D1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST26

Post Divider Register
address_offset : 0x8D20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT26_SET

Post Divider Register
address_offset : 0x8D24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT26_CLR

Post Divider Register
address_offset : 0x8D28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT26_TOG

Post Divider Register
address_offset : 0x8D2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE26

Pre Divider Register
address_offset : 0x8D30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT26_SET

Pre Divider Register
address_offset : 0x8D34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT26_CLR

Pre Divider Register
address_offset : 0x8D38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT26_TOG

Pre Divider Register
address_offset : 0x8D3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL26

Access Control Register
address_offset : 0x8D70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT26_SET

Access Control Register
address_offset : 0x8D74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT26_CLR

Access Control Register
address_offset : 0x8D78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT26_TOG

Access Control Register
address_offset : 0x8D7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT27

Target Register
address_offset : 0x8D80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT27_SET

Target Register
address_offset : 0x8D84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT27_CLR

Target Register
address_offset : 0x8D88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT27_TOG

Target Register
address_offset : 0x8D8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC27

Miscellaneous Register
address_offset : 0x8D90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT27_SET

Miscellaneous Register
address_offset : 0x8D94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT27_CLR

Miscellaneous Register
address_offset : 0x8D98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT27_TOG

Miscellaneous Register
address_offset : 0x8D9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST27

Post Divider Register
address_offset : 0x8DA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT27_SET

Post Divider Register
address_offset : 0x8DA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT27_CLR

Post Divider Register
address_offset : 0x8DA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT27_TOG

Post Divider Register
address_offset : 0x8DAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE27

Pre Divider Register
address_offset : 0x8DB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT27_SET

Pre Divider Register
address_offset : 0x8DB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT27_CLR

Pre Divider Register
address_offset : 0x8DB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT27_TOG

Pre Divider Register
address_offset : 0x8DBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL27

Access Control Register
address_offset : 0x8DF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT27_SET

Access Control Register
address_offset : 0x8DF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT27_CLR

Access Control Register
address_offset : 0x8DF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT27_TOG

Access Control Register
address_offset : 0x8DFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

CCGR33

CCM Clock Gating Register
address_offset : 0x8E310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR33_SET

CCM Clock Gating Register
address_offset : 0x8E39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR33_CLR

CCM Clock Gating Register
address_offset : 0x8E428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR33_TOG

CCM Clock Gating Register
address_offset : 0x8E4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL15

CCM PLL Control Register
address_offset : 0x8F80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL15_SET

CCM PLL Control Register
address_offset : 0x8FC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

TARGET_ROOT32

Target Register
address_offset : 0x9000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT32_SET

Target Register
address_offset : 0x9004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

PLL_CTRL15_CLR

CCM PLL Control Register
address_offset : 0x9008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

TARGET_ROOT32_CLR

Target Register
address_offset : 0x9008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT32_TOG

Target Register
address_offset : 0x900C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC32

Miscellaneous Register
address_offset : 0x9010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT32_SET

Miscellaneous Register
address_offset : 0x9014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT32_CLR

Miscellaneous Register
address_offset : 0x9018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT32_TOG

Miscellaneous Register
address_offset : 0x901C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST32

Post Divider Register
address_offset : 0x9020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT32_SET

Post Divider Register
address_offset : 0x9024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT32_CLR

Post Divider Register
address_offset : 0x9028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT32_TOG

Post Divider Register
address_offset : 0x902C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE32

Pre Divider Register
address_offset : 0x9030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT32_SET

Pre Divider Register
address_offset : 0x9034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT32_CLR

Pre Divider Register
address_offset : 0x9038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT32_TOG

Pre Divider Register
address_offset : 0x903C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PLL_CTRL15_TOG

CCM PLL Control Register
address_offset : 0x904C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL32

Access Control Register
address_offset : 0x9070 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT32_SET

Access Control Register
address_offset : 0x9074 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT32_CLR

Access Control Register
address_offset : 0x9078 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT32_TOG

Access Control Register
address_offset : 0x907C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT33

Target Register
address_offset : 0x9080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT33_SET

Target Register
address_offset : 0x9084 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT33_CLR

Target Register
address_offset : 0x9088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT33_TOG

Target Register
address_offset : 0x908C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC33

Miscellaneous Register
address_offset : 0x9090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT33_SET

Miscellaneous Register
address_offset : 0x9094 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT33_CLR

Miscellaneous Register
address_offset : 0x9098 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT33_TOG

Miscellaneous Register
address_offset : 0x909C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST33

Post Divider Register
address_offset : 0x90A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT33_SET

Post Divider Register
address_offset : 0x90A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT33_CLR

Post Divider Register
address_offset : 0x90A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT33_TOG

Post Divider Register
address_offset : 0x90AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE33

Pre Divider Register
address_offset : 0x90B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT33_SET

Pre Divider Register
address_offset : 0x90B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT33_CLR

Pre Divider Register
address_offset : 0x90B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT33_TOG

Pre Divider Register
address_offset : 0x90BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL33

Access Control Register
address_offset : 0x90F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT33_SET

Access Control Register
address_offset : 0x90F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT33_CLR

Access Control Register
address_offset : 0x90F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT33_TOG

Access Control Register
address_offset : 0x90FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT34

Target Register
address_offset : 0x9100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT34_SET

Target Register
address_offset : 0x9104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT34_CLR

Target Register
address_offset : 0x9108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT34_TOG

Target Register
address_offset : 0x910C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC34

Miscellaneous Register
address_offset : 0x9110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT34_SET

Miscellaneous Register
address_offset : 0x9114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT34_CLR

Miscellaneous Register
address_offset : 0x9118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT34_TOG

Miscellaneous Register
address_offset : 0x911C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST34

Post Divider Register
address_offset : 0x9120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT34_SET

Post Divider Register
address_offset : 0x9124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT34_CLR

Post Divider Register
address_offset : 0x9128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT34_TOG

Post Divider Register
address_offset : 0x912C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE34

Pre Divider Register
address_offset : 0x9130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT34_SET

Pre Divider Register
address_offset : 0x9134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT34_CLR

Pre Divider Register
address_offset : 0x9138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT34_TOG

Pre Divider Register
address_offset : 0x913C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL34

Access Control Register
address_offset : 0x9170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT34_SET

Access Control Register
address_offset : 0x9174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT34_CLR

Access Control Register
address_offset : 0x9178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT34_TOG

Access Control Register
address_offset : 0x917C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT35

Target Register
address_offset : 0x9180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT35_SET

Target Register
address_offset : 0x9184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT35_CLR

Target Register
address_offset : 0x9188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT35_TOG

Target Register
address_offset : 0x918C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC35

Miscellaneous Register
address_offset : 0x9190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT35_SET

Miscellaneous Register
address_offset : 0x9194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT35_CLR

Miscellaneous Register
address_offset : 0x9198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT35_TOG

Miscellaneous Register
address_offset : 0x919C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST35

Post Divider Register
address_offset : 0x91A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT35_SET

Post Divider Register
address_offset : 0x91A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT35_CLR

Post Divider Register
address_offset : 0x91A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT35_TOG

Post Divider Register
address_offset : 0x91AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE35

Pre Divider Register
address_offset : 0x91B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT35_SET

Pre Divider Register
address_offset : 0x91B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT35_CLR

Pre Divider Register
address_offset : 0x91B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT35_TOG

Pre Divider Register
address_offset : 0x91BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL35

Access Control Register
address_offset : 0x91F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT35_SET

Access Control Register
address_offset : 0x91F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT35_CLR

Access Control Register
address_offset : 0x91F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT35_TOG

Access Control Register
address_offset : 0x91FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT36

Target Register
address_offset : 0x9200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT36_SET

Target Register
address_offset : 0x9204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT36_CLR

Target Register
address_offset : 0x9208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT36_TOG

Target Register
address_offset : 0x920C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC36

Miscellaneous Register
address_offset : 0x9210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT36_SET

Miscellaneous Register
address_offset : 0x9214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT36_CLR

Miscellaneous Register
address_offset : 0x9218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT36_TOG

Miscellaneous Register
address_offset : 0x921C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST36

Post Divider Register
address_offset : 0x9220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT36_SET

Post Divider Register
address_offset : 0x9224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT36_CLR

Post Divider Register
address_offset : 0x9228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT36_TOG

Post Divider Register
address_offset : 0x922C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE36

Pre Divider Register
address_offset : 0x9230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT36_SET

Pre Divider Register
address_offset : 0x9234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT36_CLR

Pre Divider Register
address_offset : 0x9238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT36_TOG

Pre Divider Register
address_offset : 0x923C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

CCGR34

CCM Clock Gating Register
address_offset : 0x92530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR34_SET

CCM Clock Gating Register
address_offset : 0x925C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR34_CLR

CCM Clock Gating Register
address_offset : 0x92650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR34_TOG

CCM Clock Gating Register
address_offset : 0x926E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL36

Access Control Register
address_offset : 0x9270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT36_SET

Access Control Register
address_offset : 0x9274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT36_CLR

Access Control Register
address_offset : 0x9278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT36_TOG

Access Control Register
address_offset : 0x927C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT37

Target Register
address_offset : 0x9280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT37_SET

Target Register
address_offset : 0x9284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT37_CLR

Target Register
address_offset : 0x9288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT37_TOG

Target Register
address_offset : 0x928C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC37

Miscellaneous Register
address_offset : 0x9290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT37_SET

Miscellaneous Register
address_offset : 0x9294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT37_CLR

Miscellaneous Register
address_offset : 0x9298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT37_TOG

Miscellaneous Register
address_offset : 0x929C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST37

Post Divider Register
address_offset : 0x92A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT37_SET

Post Divider Register
address_offset : 0x92A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT37_CLR

Post Divider Register
address_offset : 0x92A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT37_TOG

Post Divider Register
address_offset : 0x92AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE37

Pre Divider Register
address_offset : 0x92B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT37_SET

Pre Divider Register
address_offset : 0x92B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT37_CLR

Pre Divider Register
address_offset : 0x92B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT37_TOG

Pre Divider Register
address_offset : 0x92BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL37

Access Control Register
address_offset : 0x92F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT37_SET

Access Control Register
address_offset : 0x92F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT37_CLR

Access Control Register
address_offset : 0x92F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT37_TOG

Access Control Register
address_offset : 0x92FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

CCGR35

CCM Clock Gating Register
address_offset : 0x96760 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR35_SET

CCM Clock Gating Register
address_offset : 0x967F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR35_CLR

CCM Clock Gating Register
address_offset : 0x96888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR35_TOG

CCM Clock Gating Register
address_offset : 0x9691C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

TARGET_ROOT48

Target Register
address_offset : 0x9800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT48_SET

Target Register
address_offset : 0x9804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT48_CLR

Target Register
address_offset : 0x9808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT48_TOG

Target Register
address_offset : 0x980C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC48

Miscellaneous Register
address_offset : 0x9810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT48_SET

Miscellaneous Register
address_offset : 0x9814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT48_CLR

Miscellaneous Register
address_offset : 0x9818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT48_TOG

Miscellaneous Register
address_offset : 0x981C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST48

Post Divider Register
address_offset : 0x9820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT48_SET

Post Divider Register
address_offset : 0x9824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT48_CLR

Post Divider Register
address_offset : 0x9828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT48_TOG

Post Divider Register
address_offset : 0x982C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE48

Pre Divider Register
address_offset : 0x9830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT48_SET

Pre Divider Register
address_offset : 0x9834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT48_CLR

Pre Divider Register
address_offset : 0x9838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT48_TOG

Pre Divider Register
address_offset : 0x983C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL48

Access Control Register
address_offset : 0x9870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT48_SET

Access Control Register
address_offset : 0x9874 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT48_CLR

Access Control Register
address_offset : 0x9878 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT48_TOG

Access Control Register
address_offset : 0x987C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

PLL_CTRL16

CCM PLL Control Register
address_offset : 0x9880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

TARGET_ROOT49

Target Register
address_offset : 0x9880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT49_SET

Target Register
address_offset : 0x9884 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT49_CLR

Target Register
address_offset : 0x9888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT49_TOG

Target Register
address_offset : 0x988C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC49

Miscellaneous Register
address_offset : 0x9890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT49_SET

Miscellaneous Register
address_offset : 0x9894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT49_CLR

Miscellaneous Register
address_offset : 0x9898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT49_TOG

Miscellaneous Register
address_offset : 0x989C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST49

Post Divider Register
address_offset : 0x98A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT49_SET

Post Divider Register
address_offset : 0x98A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT49_CLR

Post Divider Register
address_offset : 0x98A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT49_TOG

Post Divider Register
address_offset : 0x98AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE49

Pre Divider Register
address_offset : 0x98B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT49_SET

Pre Divider Register
address_offset : 0x98B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT49_CLR

Pre Divider Register
address_offset : 0x98B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT49_TOG

Pre Divider Register
address_offset : 0x98BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PLL_CTRL16_SET

CCM PLL Control Register
address_offset : 0x98C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL49

Access Control Register
address_offset : 0x98F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT49_SET

Access Control Register
address_offset : 0x98F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT49_CLR

Access Control Register
address_offset : 0x98F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT49_TOG

Access Control Register
address_offset : 0x98FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

PLL_CTRL16_CLR

CCM PLL Control Register
address_offset : 0x9910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL16_TOG

CCM PLL Control Register
address_offset : 0x9958 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR36

CCM Clock Gating Register
address_offset : 0x9A9A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR36_SET

CCM Clock Gating Register
address_offset : 0x9AA38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR36_CLR

CCM Clock Gating Register
address_offset : 0x9AAD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR36_TOG

CCM Clock Gating Register
address_offset : 0x9AB68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR37

CCM Clock Gating Register
address_offset : 0x9EBF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR37_SET

CCM Clock Gating Register
address_offset : 0x9EC8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR37_CLR

CCM Clock Gating Register
address_offset : 0x9ED28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR37_TOG

CCM Clock Gating Register
address_offset : 0x9EDC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

TARGET_ROOT64

Target Register
address_offset : 0xA000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT64_SET

Target Register
address_offset : 0xA004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT64_CLR

Target Register
address_offset : 0xA008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT64_TOG

Target Register
address_offset : 0xA00C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC64

Miscellaneous Register
address_offset : 0xA010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT64_SET

Miscellaneous Register
address_offset : 0xA014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT64_CLR

Miscellaneous Register
address_offset : 0xA018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT64_TOG

Miscellaneous Register
address_offset : 0xA01C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST64

Post Divider Register
address_offset : 0xA020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT64_SET

Post Divider Register
address_offset : 0xA024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT64_CLR

Post Divider Register
address_offset : 0xA028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT64_TOG

Post Divider Register
address_offset : 0xA02C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE64

Pre Divider Register
address_offset : 0xA030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT64_SET

Pre Divider Register
address_offset : 0xA034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT64_CLR

Pre Divider Register
address_offset : 0xA038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT64_TOG

Pre Divider Register
address_offset : 0xA03C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL64

Access Control Register
address_offset : 0xA070 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT64_SET

Access Control Register
address_offset : 0xA074 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT64_CLR

Access Control Register
address_offset : 0xA078 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT64_TOG

Access Control Register
address_offset : 0xA07C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT65

Target Register
address_offset : 0xA080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT65_SET

Target Register
address_offset : 0xA084 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT65_CLR

Target Register
address_offset : 0xA088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT65_TOG

Target Register
address_offset : 0xA08C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC65

Miscellaneous Register
address_offset : 0xA090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT65_SET

Miscellaneous Register
address_offset : 0xA094 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT65_CLR

Miscellaneous Register
address_offset : 0xA098 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT65_TOG

Miscellaneous Register
address_offset : 0xA09C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST65

Post Divider Register
address_offset : 0xA0A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT65_SET

Post Divider Register
address_offset : 0xA0A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT65_CLR

Post Divider Register
address_offset : 0xA0A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT65_TOG

Post Divider Register
address_offset : 0xA0AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE65

Pre Divider Register
address_offset : 0xA0B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT65_SET

Pre Divider Register
address_offset : 0xA0B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT65_CLR

Pre Divider Register
address_offset : 0xA0B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT65_TOG

Pre Divider Register
address_offset : 0xA0BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL65

Access Control Register
address_offset : 0xA0F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT65_SET

Access Control Register
address_offset : 0xA0F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT65_CLR

Access Control Register
address_offset : 0xA0F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT65_TOG

Access Control Register
address_offset : 0xA0FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT66

Target Register
address_offset : 0xA100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT66_SET

Target Register
address_offset : 0xA104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT66_CLR

Target Register
address_offset : 0xA108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT66_TOG

Target Register
address_offset : 0xA10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC66

Miscellaneous Register
address_offset : 0xA110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT66_SET

Miscellaneous Register
address_offset : 0xA114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT66_CLR

Miscellaneous Register
address_offset : 0xA118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT66_TOG

Miscellaneous Register
address_offset : 0xA11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST66

Post Divider Register
address_offset : 0xA120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT66_SET

Post Divider Register
address_offset : 0xA124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT66_CLR

Post Divider Register
address_offset : 0xA128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT66_TOG

Post Divider Register
address_offset : 0xA12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE66

Pre Divider Register
address_offset : 0xA130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT66_SET

Pre Divider Register
address_offset : 0xA134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT66_CLR

Pre Divider Register
address_offset : 0xA138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT66_TOG

Pre Divider Register
address_offset : 0xA13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL66

Access Control Register
address_offset : 0xA170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT66_SET

Access Control Register
address_offset : 0xA174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT66_CLR

Access Control Register
address_offset : 0xA178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT66_TOG

Access Control Register
address_offset : 0xA17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT67

Target Register
address_offset : 0xA180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT67_SET

Target Register
address_offset : 0xA184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT67_CLR

Target Register
address_offset : 0xA188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT67_TOG

Target Register
address_offset : 0xA18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

PLL_CTRL17

CCM PLL Control Register
address_offset : 0xA190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

MISC67

Miscellaneous Register
address_offset : 0xA190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT67_SET

Miscellaneous Register
address_offset : 0xA194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT67_CLR

Miscellaneous Register
address_offset : 0xA198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT67_TOG

Miscellaneous Register
address_offset : 0xA19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST67

Post Divider Register
address_offset : 0xA1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT67_SET

Post Divider Register
address_offset : 0xA1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT67_CLR

Post Divider Register
address_offset : 0xA1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT67_TOG

Post Divider Register
address_offset : 0xA1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE67

Pre Divider Register
address_offset : 0xA1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT67_SET

Pre Divider Register
address_offset : 0xA1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT67_CLR

Pre Divider Register
address_offset : 0xA1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT67_TOG

Pre Divider Register
address_offset : 0xA1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PLL_CTRL17_SET

CCM PLL Control Register
address_offset : 0xA1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL67

Access Control Register
address_offset : 0xA1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT67_SET

Access Control Register
address_offset : 0xA1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT67_CLR

Access Control Register
address_offset : 0xA1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT67_TOG

Access Control Register
address_offset : 0xA1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT68

Target Register
address_offset : 0xA200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT68_SET

Target Register
address_offset : 0xA204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT68_CLR

Target Register
address_offset : 0xA208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT68_TOG

Target Register
address_offset : 0xA20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC68

Miscellaneous Register
address_offset : 0xA210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT68_SET

Miscellaneous Register
address_offset : 0xA214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT68_CLR

Miscellaneous Register
address_offset : 0xA218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT68_TOG

Miscellaneous Register
address_offset : 0xA21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST68

Post Divider Register
address_offset : 0xA220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT68_SET

Post Divider Register
address_offset : 0xA224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PLL_CTRL17_CLR

CCM PLL Control Register
address_offset : 0xA228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

POST_ROOT68_CLR

Post Divider Register
address_offset : 0xA228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT68_TOG

Post Divider Register
address_offset : 0xA22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE68

Pre Divider Register
address_offset : 0xA230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT68_SET

Pre Divider Register
address_offset : 0xA234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT68_CLR

Pre Divider Register
address_offset : 0xA238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT68_TOG

Pre Divider Register
address_offset : 0xA23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL68

Access Control Register
address_offset : 0xA270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

PLL_CTRL17_TOG

CCM PLL Control Register
address_offset : 0xA274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL_ROOT68_SET

Access Control Register
address_offset : 0xA274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT68_CLR

Access Control Register
address_offset : 0xA278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT68_TOG

Access Control Register
address_offset : 0xA27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT69

Target Register
address_offset : 0xA280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT69_SET

Target Register
address_offset : 0xA284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT69_CLR

Target Register
address_offset : 0xA288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT69_TOG

Target Register
address_offset : 0xA28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC69

Miscellaneous Register
address_offset : 0xA290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT69_SET

Miscellaneous Register
address_offset : 0xA294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT69_CLR

Miscellaneous Register
address_offset : 0xA298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT69_TOG

Miscellaneous Register
address_offset : 0xA29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST69

Post Divider Register
address_offset : 0xA2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT69_SET

Post Divider Register
address_offset : 0xA2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT69_CLR

Post Divider Register
address_offset : 0xA2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT69_TOG

Post Divider Register
address_offset : 0xA2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE69

Pre Divider Register
address_offset : 0xA2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT69_SET

Pre Divider Register
address_offset : 0xA2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT69_CLR

Pre Divider Register
address_offset : 0xA2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT69_TOG

Pre Divider Register
address_offset : 0xA2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

CCGR38

CCM Clock Gating Register
address_offset : 0xA2E50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR38_SET

CCM Clock Gating Register
address_offset : 0xA2EF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL69

Access Control Register
address_offset : 0xA2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT69_SET

Access Control Register
address_offset : 0xA2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT69_CLR

Access Control Register
address_offset : 0xA2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

CCGR38_CLR

CCM Clock Gating Register
address_offset : 0xA2F90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL_ROOT69_TOG

Access Control Register
address_offset : 0xA2FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT70

Target Register
address_offset : 0xA300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

CCGR38_TOG

CCM Clock Gating Register
address_offset : 0xA3030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

TARGET_ROOT70_SET

Target Register
address_offset : 0xA304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT70_CLR

Target Register
address_offset : 0xA308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT70_TOG

Target Register
address_offset : 0xA30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC70

Miscellaneous Register
address_offset : 0xA310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT70_SET

Miscellaneous Register
address_offset : 0xA314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT70_CLR

Miscellaneous Register
address_offset : 0xA318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT70_TOG

Miscellaneous Register
address_offset : 0xA31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST70

Post Divider Register
address_offset : 0xA320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT70_SET

Post Divider Register
address_offset : 0xA324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT70_CLR

Post Divider Register
address_offset : 0xA328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT70_TOG

Post Divider Register
address_offset : 0xA32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE70

Pre Divider Register
address_offset : 0xA330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT70_SET

Pre Divider Register
address_offset : 0xA334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT70_CLR

Pre Divider Register
address_offset : 0xA338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT70_TOG

Pre Divider Register
address_offset : 0xA33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL70

Access Control Register
address_offset : 0xA370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT70_SET

Access Control Register
address_offset : 0xA374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT70_CLR

Access Control Register
address_offset : 0xA378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT70_TOG

Access Control Register
address_offset : 0xA37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT71

Target Register
address_offset : 0xA380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT71_SET

Target Register
address_offset : 0xA384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT71_CLR

Target Register
address_offset : 0xA388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT71_TOG

Target Register
address_offset : 0xA38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC71

Miscellaneous Register
address_offset : 0xA390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT71_SET

Miscellaneous Register
address_offset : 0xA394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT71_CLR

Miscellaneous Register
address_offset : 0xA398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT71_TOG

Miscellaneous Register
address_offset : 0xA39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST71

Post Divider Register
address_offset : 0xA3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT71_SET

Post Divider Register
address_offset : 0xA3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT71_CLR

Post Divider Register
address_offset : 0xA3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT71_TOG

Post Divider Register
address_offset : 0xA3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE71

Pre Divider Register
address_offset : 0xA3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT71_SET

Pre Divider Register
address_offset : 0xA3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT71_CLR

Pre Divider Register
address_offset : 0xA3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT71_TOG

Pre Divider Register
address_offset : 0xA3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL71

Access Control Register
address_offset : 0xA3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT71_SET

Access Control Register
address_offset : 0xA3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT71_CLR

Access Control Register
address_offset : 0xA3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT71_TOG

Access Control Register
address_offset : 0xA3FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT72

Target Register
address_offset : 0xA400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT72_SET

Target Register
address_offset : 0xA404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT72_CLR

Target Register
address_offset : 0xA408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT72_TOG

Target Register
address_offset : 0xA40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC72

Miscellaneous Register
address_offset : 0xA410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT72_SET

Miscellaneous Register
address_offset : 0xA414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT72_CLR

Miscellaneous Register
address_offset : 0xA418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT72_TOG

Miscellaneous Register
address_offset : 0xA41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST72

Post Divider Register
address_offset : 0xA420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT72_SET

Post Divider Register
address_offset : 0xA424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT72_CLR

Post Divider Register
address_offset : 0xA428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT72_TOG

Post Divider Register
address_offset : 0xA42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE72

Pre Divider Register
address_offset : 0xA430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT72_SET

Pre Divider Register
address_offset : 0xA434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT72_CLR

Pre Divider Register
address_offset : 0xA438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT72_TOG

Pre Divider Register
address_offset : 0xA43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL72

Access Control Register
address_offset : 0xA470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT72_SET

Access Control Register
address_offset : 0xA474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT72_CLR

Access Control Register
address_offset : 0xA478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT72_TOG

Access Control Register
address_offset : 0xA47C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT73

Target Register
address_offset : 0xA480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT73_SET

Target Register
address_offset : 0xA484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT73_CLR

Target Register
address_offset : 0xA488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT73_TOG

Target Register
address_offset : 0xA48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC73

Miscellaneous Register
address_offset : 0xA490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT73_SET

Miscellaneous Register
address_offset : 0xA494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT73_CLR

Miscellaneous Register
address_offset : 0xA498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT73_TOG

Miscellaneous Register
address_offset : 0xA49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST73

Post Divider Register
address_offset : 0xA4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT73_SET

Post Divider Register
address_offset : 0xA4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT73_CLR

Post Divider Register
address_offset : 0xA4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT73_TOG

Post Divider Register
address_offset : 0xA4AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE73

Pre Divider Register
address_offset : 0xA4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT73_SET

Pre Divider Register
address_offset : 0xA4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT73_CLR

Pre Divider Register
address_offset : 0xA4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT73_TOG

Pre Divider Register
address_offset : 0xA4BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL73

Access Control Register
address_offset : 0xA4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT73_SET

Access Control Register
address_offset : 0xA4F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT73_CLR

Access Control Register
address_offset : 0xA4F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT73_TOG

Access Control Register
address_offset : 0xA4FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT74

Target Register
address_offset : 0xA500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT74_SET

Target Register
address_offset : 0xA504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT74_CLR

Target Register
address_offset : 0xA508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT74_TOG

Target Register
address_offset : 0xA50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC74

Miscellaneous Register
address_offset : 0xA510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT74_SET

Miscellaneous Register
address_offset : 0xA514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT74_CLR

Miscellaneous Register
address_offset : 0xA518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT74_TOG

Miscellaneous Register
address_offset : 0xA51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST74

Post Divider Register
address_offset : 0xA520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT74_SET

Post Divider Register
address_offset : 0xA524 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT74_CLR

Post Divider Register
address_offset : 0xA528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT74_TOG

Post Divider Register
address_offset : 0xA52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE74

Pre Divider Register
address_offset : 0xA530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT74_SET

Pre Divider Register
address_offset : 0xA534 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT74_CLR

Pre Divider Register
address_offset : 0xA538 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT74_TOG

Pre Divider Register
address_offset : 0xA53C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL74

Access Control Register
address_offset : 0xA570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT74_SET

Access Control Register
address_offset : 0xA574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT74_CLR

Access Control Register
address_offset : 0xA578 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT74_TOG

Access Control Register
address_offset : 0xA57C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT75

Target Register
address_offset : 0xA580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT75_SET

Target Register
address_offset : 0xA584 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT75_CLR

Target Register
address_offset : 0xA588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT75_TOG

Target Register
address_offset : 0xA58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC75

Miscellaneous Register
address_offset : 0xA590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT75_SET

Miscellaneous Register
address_offset : 0xA594 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT75_CLR

Miscellaneous Register
address_offset : 0xA598 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT75_TOG

Miscellaneous Register
address_offset : 0xA59C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST75

Post Divider Register
address_offset : 0xA5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT75_SET

Post Divider Register
address_offset : 0xA5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT75_CLR

Post Divider Register
address_offset : 0xA5A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT75_TOG

Post Divider Register
address_offset : 0xA5AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE75

Pre Divider Register
address_offset : 0xA5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT75_SET

Pre Divider Register
address_offset : 0xA5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT75_CLR

Pre Divider Register
address_offset : 0xA5B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT75_TOG

Pre Divider Register
address_offset : 0xA5BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL75

Access Control Register
address_offset : 0xA5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT75_SET

Access Control Register
address_offset : 0xA5F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT75_CLR

Access Control Register
address_offset : 0xA5F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT75_TOG

Access Control Register
address_offset : 0xA5FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT76

Target Register
address_offset : 0xA600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT76_SET

Target Register
address_offset : 0xA604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT76_CLR

Target Register
address_offset : 0xA608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT76_TOG

Target Register
address_offset : 0xA60C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC76

Miscellaneous Register
address_offset : 0xA610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT76_SET

Miscellaneous Register
address_offset : 0xA614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT76_CLR

Miscellaneous Register
address_offset : 0xA618 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT76_TOG

Miscellaneous Register
address_offset : 0xA61C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST76

Post Divider Register
address_offset : 0xA620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT76_SET

Post Divider Register
address_offset : 0xA624 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT76_CLR

Post Divider Register
address_offset : 0xA628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT76_TOG

Post Divider Register
address_offset : 0xA62C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE76

Pre Divider Register
address_offset : 0xA630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT76_SET

Pre Divider Register
address_offset : 0xA634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT76_CLR

Pre Divider Register
address_offset : 0xA638 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT76_TOG

Pre Divider Register
address_offset : 0xA63C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL76

Access Control Register
address_offset : 0xA670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT76_SET

Access Control Register
address_offset : 0xA674 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT76_CLR

Access Control Register
address_offset : 0xA678 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT76_TOG

Access Control Register
address_offset : 0xA67C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT77

Target Register
address_offset : 0xA680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT77_SET

Target Register
address_offset : 0xA684 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT77_CLR

Target Register
address_offset : 0xA688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT77_TOG

Target Register
address_offset : 0xA68C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC77

Miscellaneous Register
address_offset : 0xA690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT77_SET

Miscellaneous Register
address_offset : 0xA694 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT77_CLR

Miscellaneous Register
address_offset : 0xA698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT77_TOG

Miscellaneous Register
address_offset : 0xA69C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST77

Post Divider Register
address_offset : 0xA6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT77_SET

Post Divider Register
address_offset : 0xA6A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT77_CLR

Post Divider Register
address_offset : 0xA6A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT77_TOG

Post Divider Register
address_offset : 0xA6AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE77

Pre Divider Register
address_offset : 0xA6B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT77_SET

Pre Divider Register
address_offset : 0xA6B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT77_CLR

Pre Divider Register
address_offset : 0xA6B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT77_TOG

Pre Divider Register
address_offset : 0xA6BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL77

Access Control Register
address_offset : 0xA6F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT77_SET

Access Control Register
address_offset : 0xA6F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT77_CLR

Access Control Register
address_offset : 0xA6F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT77_TOG

Access Control Register
address_offset : 0xA6FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT78

Target Register
address_offset : 0xA700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT78_SET

Target Register
address_offset : 0xA704 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT78_CLR

Target Register
address_offset : 0xA708 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT78_TOG

Target Register
address_offset : 0xA70C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

CCGR39

CCM Clock Gating Register
address_offset : 0xA70C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

MISC78

Miscellaneous Register
address_offset : 0xA710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT78_SET

Miscellaneous Register
address_offset : 0xA714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

CCGR39_SET

CCM Clock Gating Register
address_offset : 0xA7164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

MISC_ROOT78_CLR

Miscellaneous Register
address_offset : 0xA718 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT78_TOG

Miscellaneous Register
address_offset : 0xA71C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST78

Post Divider Register
address_offset : 0xA720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

CCGR39_CLR

CCM Clock Gating Register
address_offset : 0xA7208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

POST_ROOT78_SET

Post Divider Register
address_offset : 0xA724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT78_CLR

Post Divider Register
address_offset : 0xA728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

CCGR39_TOG

CCM Clock Gating Register
address_offset : 0xA72AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

POST_ROOT78_TOG

Post Divider Register
address_offset : 0xA72C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE78

Pre Divider Register
address_offset : 0xA730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT78_SET

Pre Divider Register
address_offset : 0xA734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT78_CLR

Pre Divider Register
address_offset : 0xA738 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT78_TOG

Pre Divider Register
address_offset : 0xA73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL78

Access Control Register
address_offset : 0xA770 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT78_SET

Access Control Register
address_offset : 0xA774 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT78_CLR

Access Control Register
address_offset : 0xA778 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT78_TOG

Access Control Register
address_offset : 0xA77C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT79

Target Register
address_offset : 0xA780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT79_SET

Target Register
address_offset : 0xA784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT79_CLR

Target Register
address_offset : 0xA788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT79_TOG

Target Register
address_offset : 0xA78C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC79

Miscellaneous Register
address_offset : 0xA790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT79_SET

Miscellaneous Register
address_offset : 0xA794 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT79_CLR

Miscellaneous Register
address_offset : 0xA798 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT79_TOG

Miscellaneous Register
address_offset : 0xA79C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST79

Post Divider Register
address_offset : 0xA7A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT79_SET

Post Divider Register
address_offset : 0xA7A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT79_CLR

Post Divider Register
address_offset : 0xA7A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT79_TOG

Post Divider Register
address_offset : 0xA7AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE79

Pre Divider Register
address_offset : 0xA7B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT79_SET

Pre Divider Register
address_offset : 0xA7B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT79_CLR

Pre Divider Register
address_offset : 0xA7B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT79_TOG

Pre Divider Register
address_offset : 0xA7BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL79

Access Control Register
address_offset : 0xA7F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT79_SET

Access Control Register
address_offset : 0xA7F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT79_CLR

Access Control Register
address_offset : 0xA7F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT79_TOG

Access Control Register
address_offset : 0xA7FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT80

Target Register
address_offset : 0xA800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT80_SET

Target Register
address_offset : 0xA804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT80_CLR

Target Register
address_offset : 0xA808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT80_TOG

Target Register
address_offset : 0xA80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC80

Miscellaneous Register
address_offset : 0xA810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT80_SET

Miscellaneous Register
address_offset : 0xA814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT80_CLR

Miscellaneous Register
address_offset : 0xA818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT80_TOG

Miscellaneous Register
address_offset : 0xA81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST80

Post Divider Register
address_offset : 0xA820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT80_SET

Post Divider Register
address_offset : 0xA824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT80_CLR

Post Divider Register
address_offset : 0xA828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT80_TOG

Post Divider Register
address_offset : 0xA82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE80

Pre Divider Register
address_offset : 0xA830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT80_SET

Pre Divider Register
address_offset : 0xA834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT80_CLR

Pre Divider Register
address_offset : 0xA838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT80_TOG

Pre Divider Register
address_offset : 0xA83C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL80

Access Control Register
address_offset : 0xA870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT80_SET

Access Control Register
address_offset : 0xA874 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT80_CLR

Access Control Register
address_offset : 0xA878 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT80_TOG

Access Control Register
address_offset : 0xA87C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT81

Target Register
address_offset : 0xA880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT81_SET

Target Register
address_offset : 0xA884 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT81_CLR

Target Register
address_offset : 0xA888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT81_TOG

Target Register
address_offset : 0xA88C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC81

Miscellaneous Register
address_offset : 0xA890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT81_SET

Miscellaneous Register
address_offset : 0xA894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT81_CLR

Miscellaneous Register
address_offset : 0xA898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT81_TOG

Miscellaneous Register
address_offset : 0xA89C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST81

Post Divider Register
address_offset : 0xA8A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT81_SET

Post Divider Register
address_offset : 0xA8A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT81_CLR

Post Divider Register
address_offset : 0xA8A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT81_TOG

Post Divider Register
address_offset : 0xA8AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE81

Pre Divider Register
address_offset : 0xA8B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT81_SET

Pre Divider Register
address_offset : 0xA8B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT81_CLR

Pre Divider Register
address_offset : 0xA8B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT81_TOG

Pre Divider Register
address_offset : 0xA8BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL81

Access Control Register
address_offset : 0xA8F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT81_SET

Access Control Register
address_offset : 0xA8F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT81_CLR

Access Control Register
address_offset : 0xA8F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT81_TOG

Access Control Register
address_offset : 0xA8FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT82

Target Register
address_offset : 0xA900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT82_SET

Target Register
address_offset : 0xA904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT82_CLR

Target Register
address_offset : 0xA908 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT82_TOG

Target Register
address_offset : 0xA90C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC82

Miscellaneous Register
address_offset : 0xA910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT82_SET

Miscellaneous Register
address_offset : 0xA914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT82_CLR

Miscellaneous Register
address_offset : 0xA918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT82_TOG

Miscellaneous Register
address_offset : 0xA91C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST82

Post Divider Register
address_offset : 0xA920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT82_SET

Post Divider Register
address_offset : 0xA924 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT82_CLR

Post Divider Register
address_offset : 0xA928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT82_TOG

Post Divider Register
address_offset : 0xA92C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE82

Pre Divider Register
address_offset : 0xA930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT82_SET

Pre Divider Register
address_offset : 0xA934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT82_CLR

Pre Divider Register
address_offset : 0xA938 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT82_TOG

Pre Divider Register
address_offset : 0xA93C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL82

Access Control Register
address_offset : 0xA970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT82_SET

Access Control Register
address_offset : 0xA974 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT82_CLR

Access Control Register
address_offset : 0xA978 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT82_TOG

Access Control Register
address_offset : 0xA97C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT83

Target Register
address_offset : 0xA980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT83_SET

Target Register
address_offset : 0xA984 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT83_CLR

Target Register
address_offset : 0xA988 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT83_TOG

Target Register
address_offset : 0xA98C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC83

Miscellaneous Register
address_offset : 0xA990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT83_SET

Miscellaneous Register
address_offset : 0xA994 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT83_CLR

Miscellaneous Register
address_offset : 0xA998 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT83_TOG

Miscellaneous Register
address_offset : 0xA99C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST83

Post Divider Register
address_offset : 0xA9A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT83_SET

Post Divider Register
address_offset : 0xA9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT83_CLR

Post Divider Register
address_offset : 0xA9A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT83_TOG

Post Divider Register
address_offset : 0xA9AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE83

Pre Divider Register
address_offset : 0xA9B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT83_SET

Pre Divider Register
address_offset : 0xA9B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT83_CLR

Pre Divider Register
address_offset : 0xA9B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT83_TOG

Pre Divider Register
address_offset : 0xA9BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL83

Access Control Register
address_offset : 0xA9F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT83_SET

Access Control Register
address_offset : 0xA9F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT83_CLR

Access Control Register
address_offset : 0xA9F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT83_TOG

Access Control Register
address_offset : 0xA9FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT84

Target Register
address_offset : 0xAA00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT84_SET

Target Register
address_offset : 0xAA04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT84_CLR

Target Register
address_offset : 0xAA08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT84_TOG

Target Register
address_offset : 0xAA0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC84

Miscellaneous Register
address_offset : 0xAA10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT84_SET

Miscellaneous Register
address_offset : 0xAA14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT84_CLR

Miscellaneous Register
address_offset : 0xAA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT84_TOG

Miscellaneous Register
address_offset : 0xAA1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST84

Post Divider Register
address_offset : 0xAA20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT84_SET

Post Divider Register
address_offset : 0xAA24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT84_CLR

Post Divider Register
address_offset : 0xAA28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT84_TOG

Post Divider Register
address_offset : 0xAA2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE84

Pre Divider Register
address_offset : 0xAA30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT84_SET

Pre Divider Register
address_offset : 0xAA34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT84_CLR

Pre Divider Register
address_offset : 0xAA38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT84_TOG

Pre Divider Register
address_offset : 0xAA3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL84

Access Control Register
address_offset : 0xAA70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT84_SET

Access Control Register
address_offset : 0xAA74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT84_CLR

Access Control Register
address_offset : 0xAA78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT84_TOG

Access Control Register
address_offset : 0xAA7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT85

Target Register
address_offset : 0xAA80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT85_SET

Target Register
address_offset : 0xAA84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT85_CLR

Target Register
address_offset : 0xAA88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT85_TOG

Target Register
address_offset : 0xAA8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC85

Miscellaneous Register
address_offset : 0xAA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT85_SET

Miscellaneous Register
address_offset : 0xAA94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT85_CLR

Miscellaneous Register
address_offset : 0xAA98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT85_TOG

Miscellaneous Register
address_offset : 0xAA9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST85

Post Divider Register
address_offset : 0xAAA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT85_SET

Post Divider Register
address_offset : 0xAAA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT85_CLR

Post Divider Register
address_offset : 0xAAA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT85_TOG

Post Divider Register
address_offset : 0xAAAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PLL_CTRL18

CCM PLL Control Register
address_offset : 0xAAB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PRE85

Pre Divider Register
address_offset : 0xAAB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT85_SET

Pre Divider Register
address_offset : 0xAAB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT85_CLR

Pre Divider Register
address_offset : 0xAAB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT85_TOG

Pre Divider Register
address_offset : 0xAABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL85

Access Control Register
address_offset : 0xAAF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT85_SET

Access Control Register
address_offset : 0xAAF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT85_CLR

Access Control Register
address_offset : 0xAAF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT85_TOG

Access Control Register
address_offset : 0xAAFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

PLL_CTRL18_SET

CCM PLL Control Register
address_offset : 0xAB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

TARGET_ROOT86

Target Register
address_offset : 0xAB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT86_SET

Target Register
address_offset : 0xAB04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT86_CLR

Target Register
address_offset : 0xAB08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT86_TOG

Target Register
address_offset : 0xAB0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC86

Miscellaneous Register
address_offset : 0xAB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT86_SET

Miscellaneous Register
address_offset : 0xAB14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT86_CLR

Miscellaneous Register
address_offset : 0xAB18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT86_TOG

Miscellaneous Register
address_offset : 0xAB1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST86

Post Divider Register
address_offset : 0xAB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT86_SET

Post Divider Register
address_offset : 0xAB24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT86_CLR

Post Divider Register
address_offset : 0xAB28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT86_TOG

Post Divider Register
address_offset : 0xAB2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE86

Pre Divider Register
address_offset : 0xAB30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT86_SET

Pre Divider Register
address_offset : 0xAB34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

CCGR40

CCM Clock Gating Register
address_offset : 0xAB340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PRE_ROOT86_CLR

Pre Divider Register
address_offset : 0xAB38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT86_TOG

Pre Divider Register
address_offset : 0xAB3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

CCGR40_SET

CCM Clock Gating Register
address_offset : 0xAB3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR40_CLR

CCM Clock Gating Register
address_offset : 0xAB490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL18_CLR

CCM PLL Control Register
address_offset : 0xAB50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR40_TOG

CCM Clock Gating Register
address_offset : 0xAB538 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL86

Access Control Register
address_offset : 0xAB70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT86_SET

Access Control Register
address_offset : 0xAB74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT86_CLR

Access Control Register
address_offset : 0xAB78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT86_TOG

Access Control Register
address_offset : 0xAB7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT87

Target Register
address_offset : 0xAB80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT87_SET

Target Register
address_offset : 0xAB84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT87_CLR

Target Register
address_offset : 0xAB88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT87_TOG

Target Register
address_offset : 0xAB8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC87

Miscellaneous Register
address_offset : 0xAB90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT87_SET

Miscellaneous Register
address_offset : 0xAB94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT87_CLR

Miscellaneous Register
address_offset : 0xAB98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT87_TOG

Miscellaneous Register
address_offset : 0xAB9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

PLL_CTRL18_TOG

CCM PLL Control Register
address_offset : 0xABA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

POST87

Post Divider Register
address_offset : 0xABA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT87_SET

Post Divider Register
address_offset : 0xABA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT87_CLR

Post Divider Register
address_offset : 0xABA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT87_TOG

Post Divider Register
address_offset : 0xABAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE87

Pre Divider Register
address_offset : 0xABB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT87_SET

Pre Divider Register
address_offset : 0xABB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT87_CLR

Pre Divider Register
address_offset : 0xABB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT87_TOG

Pre Divider Register
address_offset : 0xABBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL87

Access Control Register
address_offset : 0xABF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT87_SET

Access Control Register
address_offset : 0xABF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT87_CLR

Access Control Register
address_offset : 0xABF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT87_TOG

Access Control Register
address_offset : 0xABFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT88

Target Register
address_offset : 0xAC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT88_SET

Target Register
address_offset : 0xAC04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT88_CLR

Target Register
address_offset : 0xAC08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT88_TOG

Target Register
address_offset : 0xAC0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC88

Miscellaneous Register
address_offset : 0xAC10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT88_SET

Miscellaneous Register
address_offset : 0xAC14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT88_CLR

Miscellaneous Register
address_offset : 0xAC18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT88_TOG

Miscellaneous Register
address_offset : 0xAC1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST88

Post Divider Register
address_offset : 0xAC20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT88_SET

Post Divider Register
address_offset : 0xAC24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT88_CLR

Post Divider Register
address_offset : 0xAC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT88_TOG

Post Divider Register
address_offset : 0xAC2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE88

Pre Divider Register
address_offset : 0xAC30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT88_SET

Pre Divider Register
address_offset : 0xAC34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT88_CLR

Pre Divider Register
address_offset : 0xAC38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT88_TOG

Pre Divider Register
address_offset : 0xAC3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL88

Access Control Register
address_offset : 0xAC70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT88_SET

Access Control Register
address_offset : 0xAC74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT88_CLR

Access Control Register
address_offset : 0xAC78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT88_TOG

Access Control Register
address_offset : 0xAC7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT89

Target Register
address_offset : 0xAC80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT89_SET

Target Register
address_offset : 0xAC84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT89_CLR

Target Register
address_offset : 0xAC88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT89_TOG

Target Register
address_offset : 0xAC8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC89

Miscellaneous Register
address_offset : 0xAC90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT89_SET

Miscellaneous Register
address_offset : 0xAC94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT89_CLR

Miscellaneous Register
address_offset : 0xAC98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT89_TOG

Miscellaneous Register
address_offset : 0xAC9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST89

Post Divider Register
address_offset : 0xACA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT89_SET

Post Divider Register
address_offset : 0xACA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT89_CLR

Post Divider Register
address_offset : 0xACA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT89_TOG

Post Divider Register
address_offset : 0xACAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE89

Pre Divider Register
address_offset : 0xACB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT89_SET

Pre Divider Register
address_offset : 0xACB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT89_CLR

Pre Divider Register
address_offset : 0xACB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT89_TOG

Pre Divider Register
address_offset : 0xACBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL89

Access Control Register
address_offset : 0xACF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT89_SET

Access Control Register
address_offset : 0xACF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT89_CLR

Access Control Register
address_offset : 0xACF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT89_TOG

Access Control Register
address_offset : 0xACFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT90

Target Register
address_offset : 0xAD00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT90_SET

Target Register
address_offset : 0xAD04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT90_CLR

Target Register
address_offset : 0xAD08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT90_TOG

Target Register
address_offset : 0xAD0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC90

Miscellaneous Register
address_offset : 0xAD10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT90_SET

Miscellaneous Register
address_offset : 0xAD14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT90_CLR

Miscellaneous Register
address_offset : 0xAD18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT90_TOG

Miscellaneous Register
address_offset : 0xAD1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST90

Post Divider Register
address_offset : 0xAD20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT90_SET

Post Divider Register
address_offset : 0xAD24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT90_CLR

Post Divider Register
address_offset : 0xAD28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT90_TOG

Post Divider Register
address_offset : 0xAD2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE90

Pre Divider Register
address_offset : 0xAD30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT90_SET

Pre Divider Register
address_offset : 0xAD34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT90_CLR

Pre Divider Register
address_offset : 0xAD38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT90_TOG

Pre Divider Register
address_offset : 0xAD3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL90

Access Control Register
address_offset : 0xAD70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT90_SET

Access Control Register
address_offset : 0xAD74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT90_CLR

Access Control Register
address_offset : 0xAD78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT90_TOG

Access Control Register
address_offset : 0xAD7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT91

Target Register
address_offset : 0xAD80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT91_SET

Target Register
address_offset : 0xAD84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT91_CLR

Target Register
address_offset : 0xAD88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT91_TOG

Target Register
address_offset : 0xAD8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC91

Miscellaneous Register
address_offset : 0xAD90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT91_SET

Miscellaneous Register
address_offset : 0xAD94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT91_CLR

Miscellaneous Register
address_offset : 0xAD98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT91_TOG

Miscellaneous Register
address_offset : 0xAD9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST91

Post Divider Register
address_offset : 0xADA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT91_SET

Post Divider Register
address_offset : 0xADA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT91_CLR

Post Divider Register
address_offset : 0xADA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT91_TOG

Post Divider Register
address_offset : 0xADAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE91

Pre Divider Register
address_offset : 0xADB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT91_SET

Pre Divider Register
address_offset : 0xADB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT91_CLR

Pre Divider Register
address_offset : 0xADB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT91_TOG

Pre Divider Register
address_offset : 0xADBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL91

Access Control Register
address_offset : 0xADF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT91_SET

Access Control Register
address_offset : 0xADF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT91_CLR

Access Control Register
address_offset : 0xADF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT91_TOG

Access Control Register
address_offset : 0xADFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT92

Target Register
address_offset : 0xAE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT92_SET

Target Register
address_offset : 0xAE04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT92_CLR

Target Register
address_offset : 0xAE08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT92_TOG

Target Register
address_offset : 0xAE0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC92

Miscellaneous Register
address_offset : 0xAE10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT92_SET

Miscellaneous Register
address_offset : 0xAE14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT92_CLR

Miscellaneous Register
address_offset : 0xAE18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT92_TOG

Miscellaneous Register
address_offset : 0xAE1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST92

Post Divider Register
address_offset : 0xAE20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT92_SET

Post Divider Register
address_offset : 0xAE24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT92_CLR

Post Divider Register
address_offset : 0xAE28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT92_TOG

Post Divider Register
address_offset : 0xAE2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE92

Pre Divider Register
address_offset : 0xAE30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT92_SET

Pre Divider Register
address_offset : 0xAE34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT92_CLR

Pre Divider Register
address_offset : 0xAE38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT92_TOG

Pre Divider Register
address_offset : 0xAE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL92

Access Control Register
address_offset : 0xAE70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT92_SET

Access Control Register
address_offset : 0xAE74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT92_CLR

Access Control Register
address_offset : 0xAE78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT92_TOG

Access Control Register
address_offset : 0xAE7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT93

Target Register
address_offset : 0xAE80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT93_SET

Target Register
address_offset : 0xAE84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT93_CLR

Target Register
address_offset : 0xAE88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT93_TOG

Target Register
address_offset : 0xAE8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC93

Miscellaneous Register
address_offset : 0xAE90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT93_SET

Miscellaneous Register
address_offset : 0xAE94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT93_CLR

Miscellaneous Register
address_offset : 0xAE98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT93_TOG

Miscellaneous Register
address_offset : 0xAE9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST93

Post Divider Register
address_offset : 0xAEA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT93_SET

Post Divider Register
address_offset : 0xAEA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT93_CLR

Post Divider Register
address_offset : 0xAEA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT93_TOG

Post Divider Register
address_offset : 0xAEAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE93

Pre Divider Register
address_offset : 0xAEB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT93_SET

Pre Divider Register
address_offset : 0xAEB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT93_CLR

Pre Divider Register
address_offset : 0xAEB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT93_TOG

Pre Divider Register
address_offset : 0xAEBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL93

Access Control Register
address_offset : 0xAEF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT93_SET

Access Control Register
address_offset : 0xAEF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT93_CLR

Access Control Register
address_offset : 0xAEF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT93_TOG

Access Control Register
address_offset : 0xAEFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT94

Target Register
address_offset : 0xAF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT94_SET

Target Register
address_offset : 0xAF04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT94_CLR

Target Register
address_offset : 0xAF08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT94_TOG

Target Register
address_offset : 0xAF0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC94

Miscellaneous Register
address_offset : 0xAF10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT94_SET

Miscellaneous Register
address_offset : 0xAF14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT94_CLR

Miscellaneous Register
address_offset : 0xAF18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT94_TOG

Miscellaneous Register
address_offset : 0xAF1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST94

Post Divider Register
address_offset : 0xAF20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT94_SET

Post Divider Register
address_offset : 0xAF24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT94_CLR

Post Divider Register
address_offset : 0xAF28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT94_TOG

Post Divider Register
address_offset : 0xAF2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE94

Pre Divider Register
address_offset : 0xAF30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT94_SET

Pre Divider Register
address_offset : 0xAF34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT94_CLR

Pre Divider Register
address_offset : 0xAF38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT94_TOG

Pre Divider Register
address_offset : 0xAF3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

CCGR41

CCM Clock Gating Register
address_offset : 0xAF5D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR41_SET

CCM Clock Gating Register
address_offset : 0xAF67C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL94

Access Control Register
address_offset : 0xAF70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

CCGR41_CLR

CCM Clock Gating Register
address_offset : 0xAF728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL_ROOT94_SET

Access Control Register
address_offset : 0xAF74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT94_CLR

Access Control Register
address_offset : 0xAF78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT94_TOG

Access Control Register
address_offset : 0xAF7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

CCGR41_TOG

CCM Clock Gating Register
address_offset : 0xAF7D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

TARGET_ROOT95

Target Register
address_offset : 0xAF80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT95_SET

Target Register
address_offset : 0xAF84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT95_CLR

Target Register
address_offset : 0xAF88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT95_TOG

Target Register
address_offset : 0xAF8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC95

Miscellaneous Register
address_offset : 0xAF90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT95_SET

Miscellaneous Register
address_offset : 0xAF94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT95_CLR

Miscellaneous Register
address_offset : 0xAF98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT95_TOG

Miscellaneous Register
address_offset : 0xAF9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST95

Post Divider Register
address_offset : 0xAFA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT95_SET

Post Divider Register
address_offset : 0xAFA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT95_CLR

Post Divider Register
address_offset : 0xAFA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT95_TOG

Post Divider Register
address_offset : 0xAFAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE95

Pre Divider Register
address_offset : 0xAFB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT95_SET

Pre Divider Register
address_offset : 0xAFB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT95_CLR

Pre Divider Register
address_offset : 0xAFB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT95_TOG

Pre Divider Register
address_offset : 0xAFBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL95

Access Control Register
address_offset : 0xAFF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT95_SET

Access Control Register
address_offset : 0xAFF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT95_CLR

Access Control Register
address_offset : 0xAFF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT95_TOG

Access Control Register
address_offset : 0xAFFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT96

Target Register
address_offset : 0xB000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT96_SET

Target Register
address_offset : 0xB004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT96_CLR

Target Register
address_offset : 0xB008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT96_TOG

Target Register
address_offset : 0xB00C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC96

Miscellaneous Register
address_offset : 0xB010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT96_SET

Miscellaneous Register
address_offset : 0xB014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT96_CLR

Miscellaneous Register
address_offset : 0xB018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT96_TOG

Miscellaneous Register
address_offset : 0xB01C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST96

Post Divider Register
address_offset : 0xB020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT96_SET

Post Divider Register
address_offset : 0xB024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT96_CLR

Post Divider Register
address_offset : 0xB028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT96_TOG

Post Divider Register
address_offset : 0xB02C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE96

Pre Divider Register
address_offset : 0xB030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT96_SET

Pre Divider Register
address_offset : 0xB034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT96_CLR

Pre Divider Register
address_offset : 0xB038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT96_TOG

Pre Divider Register
address_offset : 0xB03C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL96

Access Control Register
address_offset : 0xB070 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT96_SET

Access Control Register
address_offset : 0xB074 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT96_CLR

Access Control Register
address_offset : 0xB078 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT96_TOG

Access Control Register
address_offset : 0xB07C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT97

Target Register
address_offset : 0xB080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT97_SET

Target Register
address_offset : 0xB084 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT97_CLR

Target Register
address_offset : 0xB088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT97_TOG

Target Register
address_offset : 0xB08C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC97

Miscellaneous Register
address_offset : 0xB090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT97_SET

Miscellaneous Register
address_offset : 0xB094 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT97_CLR

Miscellaneous Register
address_offset : 0xB098 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT97_TOG

Miscellaneous Register
address_offset : 0xB09C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST97

Post Divider Register
address_offset : 0xB0A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT97_SET

Post Divider Register
address_offset : 0xB0A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT97_CLR

Post Divider Register
address_offset : 0xB0A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT97_TOG

Post Divider Register
address_offset : 0xB0AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE97

Pre Divider Register
address_offset : 0xB0B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT97_SET

Pre Divider Register
address_offset : 0xB0B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT97_CLR

Pre Divider Register
address_offset : 0xB0B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT97_TOG

Pre Divider Register
address_offset : 0xB0BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL97

Access Control Register
address_offset : 0xB0F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT97_SET

Access Control Register
address_offset : 0xB0F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT97_CLR

Access Control Register
address_offset : 0xB0F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT97_TOG

Access Control Register
address_offset : 0xB0FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT98

Target Register
address_offset : 0xB100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT98_SET

Target Register
address_offset : 0xB104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT98_CLR

Target Register
address_offset : 0xB108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT98_TOG

Target Register
address_offset : 0xB10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC98

Miscellaneous Register
address_offset : 0xB110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT98_SET

Miscellaneous Register
address_offset : 0xB114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT98_CLR

Miscellaneous Register
address_offset : 0xB118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT98_TOG

Miscellaneous Register
address_offset : 0xB11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST98

Post Divider Register
address_offset : 0xB120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT98_SET

Post Divider Register
address_offset : 0xB124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT98_CLR

Post Divider Register
address_offset : 0xB128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT98_TOG

Post Divider Register
address_offset : 0xB12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE98

Pre Divider Register
address_offset : 0xB130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT98_SET

Pre Divider Register
address_offset : 0xB134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT98_CLR

Pre Divider Register
address_offset : 0xB138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT98_TOG

Pre Divider Register
address_offset : 0xB13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL98

Access Control Register
address_offset : 0xB170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT98_SET

Access Control Register
address_offset : 0xB174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT98_CLR

Access Control Register
address_offset : 0xB178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT98_TOG

Access Control Register
address_offset : 0xB17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT99

Target Register
address_offset : 0xB180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT99_SET

Target Register
address_offset : 0xB184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT99_CLR

Target Register
address_offset : 0xB188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT99_TOG

Target Register
address_offset : 0xB18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC99

Miscellaneous Register
address_offset : 0xB190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT99_SET

Miscellaneous Register
address_offset : 0xB194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT99_CLR

Miscellaneous Register
address_offset : 0xB198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT99_TOG

Miscellaneous Register
address_offset : 0xB19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST99

Post Divider Register
address_offset : 0xB1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT99_SET

Post Divider Register
address_offset : 0xB1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT99_CLR

Post Divider Register
address_offset : 0xB1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT99_TOG

Post Divider Register
address_offset : 0xB1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE99

Pre Divider Register
address_offset : 0xB1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT99_SET

Pre Divider Register
address_offset : 0xB1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT99_CLR

Pre Divider Register
address_offset : 0xB1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT99_TOG

Pre Divider Register
address_offset : 0xB1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL99

Access Control Register
address_offset : 0xB1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT99_SET

Access Control Register
address_offset : 0xB1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT99_CLR

Access Control Register
address_offset : 0xB1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT99_TOG

Access Control Register
address_offset : 0xB1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT100

Target Register
address_offset : 0xB200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT100_SET

Target Register
address_offset : 0xB204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT100_CLR

Target Register
address_offset : 0xB208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT100_TOG

Target Register
address_offset : 0xB20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC100

Miscellaneous Register
address_offset : 0xB210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT100_SET

Miscellaneous Register
address_offset : 0xB214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT100_CLR

Miscellaneous Register
address_offset : 0xB218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT100_TOG

Miscellaneous Register
address_offset : 0xB21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST100

Post Divider Register
address_offset : 0xB220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT100_SET

Post Divider Register
address_offset : 0xB224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT100_CLR

Post Divider Register
address_offset : 0xB228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT100_TOG

Post Divider Register
address_offset : 0xB22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE100

Pre Divider Register
address_offset : 0xB230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT100_SET

Pre Divider Register
address_offset : 0xB234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT100_CLR

Pre Divider Register
address_offset : 0xB238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT100_TOG

Pre Divider Register
address_offset : 0xB23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL100

Access Control Register
address_offset : 0xB270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT100_SET

Access Control Register
address_offset : 0xB274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT100_CLR

Access Control Register
address_offset : 0xB278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT100_TOG

Access Control Register
address_offset : 0xB27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT101

Target Register
address_offset : 0xB280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT101_SET

Target Register
address_offset : 0xB284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT101_CLR

Target Register
address_offset : 0xB288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT101_TOG

Target Register
address_offset : 0xB28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC101

Miscellaneous Register
address_offset : 0xB290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT101_SET

Miscellaneous Register
address_offset : 0xB294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT101_CLR

Miscellaneous Register
address_offset : 0xB298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT101_TOG

Miscellaneous Register
address_offset : 0xB29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST101

Post Divider Register
address_offset : 0xB2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT101_SET

Post Divider Register
address_offset : 0xB2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT101_CLR

Post Divider Register
address_offset : 0xB2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT101_TOG

Post Divider Register
address_offset : 0xB2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE101

Pre Divider Register
address_offset : 0xB2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT101_SET

Pre Divider Register
address_offset : 0xB2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT101_CLR

Pre Divider Register
address_offset : 0xB2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT101_TOG

Pre Divider Register
address_offset : 0xB2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL101

Access Control Register
address_offset : 0xB2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT101_SET

Access Control Register
address_offset : 0xB2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT101_CLR

Access Control Register
address_offset : 0xB2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT101_TOG

Access Control Register
address_offset : 0xB2FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT102

Target Register
address_offset : 0xB300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT102_SET

Target Register
address_offset : 0xB304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT102_CLR

Target Register
address_offset : 0xB308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT102_TOG

Target Register
address_offset : 0xB30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC102

Miscellaneous Register
address_offset : 0xB310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT102_SET

Miscellaneous Register
address_offset : 0xB314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT102_CLR

Miscellaneous Register
address_offset : 0xB318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT102_TOG

Miscellaneous Register
address_offset : 0xB31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST102

Post Divider Register
address_offset : 0xB320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT102_SET

Post Divider Register
address_offset : 0xB324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT102_CLR

Post Divider Register
address_offset : 0xB328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT102_TOG

Post Divider Register
address_offset : 0xB32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE102

Pre Divider Register
address_offset : 0xB330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT102_SET

Pre Divider Register
address_offset : 0xB334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT102_CLR

Pre Divider Register
address_offset : 0xB338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT102_TOG

Pre Divider Register
address_offset : 0xB33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL102

Access Control Register
address_offset : 0xB370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT102_SET

Access Control Register
address_offset : 0xB374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT102_CLR

Access Control Register
address_offset : 0xB378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT102_TOG

Access Control Register
address_offset : 0xB37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT103

Target Register
address_offset : 0xB380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT103_SET

Target Register
address_offset : 0xB384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

CCGR42

CCM Clock Gating Register
address_offset : 0xB3870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

TARGET_ROOT103_CLR

Target Register
address_offset : 0xB388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT103_TOG

Target Register
address_offset : 0xB38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC103

Miscellaneous Register
address_offset : 0xB390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

CCGR42_SET

CCM Clock Gating Register
address_offset : 0xB3920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

MISC_ROOT103_SET

Miscellaneous Register
address_offset : 0xB394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT103_CLR

Miscellaneous Register
address_offset : 0xB398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT103_TOG

Miscellaneous Register
address_offset : 0xB39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

CCGR42_CLR

CCM Clock Gating Register
address_offset : 0xB39D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

POST103

Post Divider Register
address_offset : 0xB3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT103_SET

Post Divider Register
address_offset : 0xB3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT103_CLR

Post Divider Register
address_offset : 0xB3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

CCGR42_TOG

CCM Clock Gating Register
address_offset : 0xB3A80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

POST_ROOT103_TOG

Post Divider Register
address_offset : 0xB3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE103

Pre Divider Register
address_offset : 0xB3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT103_SET

Pre Divider Register
address_offset : 0xB3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT103_CLR

Pre Divider Register
address_offset : 0xB3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT103_TOG

Pre Divider Register
address_offset : 0xB3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PLL_CTRL19

CCM PLL Control Register
address_offset : 0xB3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL103

Access Control Register
address_offset : 0xB3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT103_SET

Access Control Register
address_offset : 0xB3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT103_CLR

Access Control Register
address_offset : 0xB3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT103_TOG

Access Control Register
address_offset : 0xB3FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT104

Target Register
address_offset : 0xB400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT104_SET

Target Register
address_offset : 0xB404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT104_CLR

Target Register
address_offset : 0xB408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT104_TOG

Target Register
address_offset : 0xB40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC104

Miscellaneous Register
address_offset : 0xB410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT104_SET

Miscellaneous Register
address_offset : 0xB414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT104_CLR

Miscellaneous Register
address_offset : 0xB418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT104_TOG

Miscellaneous Register
address_offset : 0xB41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST104

Post Divider Register
address_offset : 0xB420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT104_SET

Post Divider Register
address_offset : 0xB424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT104_CLR

Post Divider Register
address_offset : 0xB428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT104_TOG

Post Divider Register
address_offset : 0xB42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE104

Pre Divider Register
address_offset : 0xB430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PLL_CTRL19_SET

CCM PLL Control Register
address_offset : 0xB434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PRE_ROOT104_SET

Pre Divider Register
address_offset : 0xB434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT104_CLR

Pre Divider Register
address_offset : 0xB438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT104_TOG

Pre Divider Register
address_offset : 0xB43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL104

Access Control Register
address_offset : 0xB470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT104_SET

Access Control Register
address_offset : 0xB474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT104_CLR

Access Control Register
address_offset : 0xB478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT104_TOG

Access Control Register
address_offset : 0xB47C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT105

Target Register
address_offset : 0xB480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT105_SET

Target Register
address_offset : 0xB484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

PLL_CTRL19_CLR

CCM PLL Control Register
address_offset : 0xB488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

TARGET_ROOT105_CLR

Target Register
address_offset : 0xB488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT105_TOG

Target Register
address_offset : 0xB48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC105

Miscellaneous Register
address_offset : 0xB490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT105_SET

Miscellaneous Register
address_offset : 0xB494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT105_CLR

Miscellaneous Register
address_offset : 0xB498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT105_TOG

Miscellaneous Register
address_offset : 0xB49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST105

Post Divider Register
address_offset : 0xB4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT105_SET

Post Divider Register
address_offset : 0xB4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT105_CLR

Post Divider Register
address_offset : 0xB4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT105_TOG

Post Divider Register
address_offset : 0xB4AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE105

Pre Divider Register
address_offset : 0xB4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT105_SET

Pre Divider Register
address_offset : 0xB4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT105_CLR

Pre Divider Register
address_offset : 0xB4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT105_TOG

Pre Divider Register
address_offset : 0xB4BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PLL_CTRL19_TOG

CCM PLL Control Register
address_offset : 0xB4DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL105

Access Control Register
address_offset : 0xB4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT105_SET

Access Control Register
address_offset : 0xB4F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT105_CLR

Access Control Register
address_offset : 0xB4F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT105_TOG

Access Control Register
address_offset : 0xB4FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT106

Target Register
address_offset : 0xB500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT106_SET

Target Register
address_offset : 0xB504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT106_CLR

Target Register
address_offset : 0xB508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT106_TOG

Target Register
address_offset : 0xB50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC106

Miscellaneous Register
address_offset : 0xB510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT106_SET

Miscellaneous Register
address_offset : 0xB514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT106_CLR

Miscellaneous Register
address_offset : 0xB518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT106_TOG

Miscellaneous Register
address_offset : 0xB51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST106

Post Divider Register
address_offset : 0xB520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT106_SET

Post Divider Register
address_offset : 0xB524 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT106_CLR

Post Divider Register
address_offset : 0xB528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT106_TOG

Post Divider Register
address_offset : 0xB52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE106

Pre Divider Register
address_offset : 0xB530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT106_SET

Pre Divider Register
address_offset : 0xB534 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT106_CLR

Pre Divider Register
address_offset : 0xB538 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT106_TOG

Pre Divider Register
address_offset : 0xB53C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL106

Access Control Register
address_offset : 0xB570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT106_SET

Access Control Register
address_offset : 0xB574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT106_CLR

Access Control Register
address_offset : 0xB578 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT106_TOG

Access Control Register
address_offset : 0xB57C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT107

Target Register
address_offset : 0xB580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT107_SET

Target Register
address_offset : 0xB584 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT107_CLR

Target Register
address_offset : 0xB588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT107_TOG

Target Register
address_offset : 0xB58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC107

Miscellaneous Register
address_offset : 0xB590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT107_SET

Miscellaneous Register
address_offset : 0xB594 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT107_CLR

Miscellaneous Register
address_offset : 0xB598 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT107_TOG

Miscellaneous Register
address_offset : 0xB59C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST107

Post Divider Register
address_offset : 0xB5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT107_SET

Post Divider Register
address_offset : 0xB5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT107_CLR

Post Divider Register
address_offset : 0xB5A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT107_TOG

Post Divider Register
address_offset : 0xB5AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE107

Pre Divider Register
address_offset : 0xB5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT107_SET

Pre Divider Register
address_offset : 0xB5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT107_CLR

Pre Divider Register
address_offset : 0xB5B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT107_TOG

Pre Divider Register
address_offset : 0xB5BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL107

Access Control Register
address_offset : 0xB5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT107_SET

Access Control Register
address_offset : 0xB5F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT107_CLR

Access Control Register
address_offset : 0xB5F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT107_TOG

Access Control Register
address_offset : 0xB5FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT108

Target Register
address_offset : 0xB600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT108_SET

Target Register
address_offset : 0xB604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT108_CLR

Target Register
address_offset : 0xB608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT108_TOG

Target Register
address_offset : 0xB60C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC108

Miscellaneous Register
address_offset : 0xB610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT108_SET

Miscellaneous Register
address_offset : 0xB614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT108_CLR

Miscellaneous Register
address_offset : 0xB618 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT108_TOG

Miscellaneous Register
address_offset : 0xB61C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST108

Post Divider Register
address_offset : 0xB620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT108_SET

Post Divider Register
address_offset : 0xB624 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT108_CLR

Post Divider Register
address_offset : 0xB628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT108_TOG

Post Divider Register
address_offset : 0xB62C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE108

Pre Divider Register
address_offset : 0xB630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT108_SET

Pre Divider Register
address_offset : 0xB634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT108_CLR

Pre Divider Register
address_offset : 0xB638 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT108_TOG

Pre Divider Register
address_offset : 0xB63C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL108

Access Control Register
address_offset : 0xB670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT108_SET

Access Control Register
address_offset : 0xB674 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT108_CLR

Access Control Register
address_offset : 0xB678 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT108_TOG

Access Control Register
address_offset : 0xB67C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT109

Target Register
address_offset : 0xB680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT109_SET

Target Register
address_offset : 0xB684 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT109_CLR

Target Register
address_offset : 0xB688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT109_TOG

Target Register
address_offset : 0xB68C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC109

Miscellaneous Register
address_offset : 0xB690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT109_SET

Miscellaneous Register
address_offset : 0xB694 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT109_CLR

Miscellaneous Register
address_offset : 0xB698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT109_TOG

Miscellaneous Register
address_offset : 0xB69C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST109

Post Divider Register
address_offset : 0xB6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT109_SET

Post Divider Register
address_offset : 0xB6A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT109_CLR

Post Divider Register
address_offset : 0xB6A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT109_TOG

Post Divider Register
address_offset : 0xB6AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE109

Pre Divider Register
address_offset : 0xB6B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT109_SET

Pre Divider Register
address_offset : 0xB6B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT109_CLR

Pre Divider Register
address_offset : 0xB6B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT109_TOG

Pre Divider Register
address_offset : 0xB6BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL109

Access Control Register
address_offset : 0xB6F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT109_SET

Access Control Register
address_offset : 0xB6F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT109_CLR

Access Control Register
address_offset : 0xB6F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT109_TOG

Access Control Register
address_offset : 0xB6FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT110

Target Register
address_offset : 0xB700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT110_SET

Target Register
address_offset : 0xB704 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT110_CLR

Target Register
address_offset : 0xB708 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT110_TOG

Target Register
address_offset : 0xB70C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC110

Miscellaneous Register
address_offset : 0xB710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT110_SET

Miscellaneous Register
address_offset : 0xB714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT110_CLR

Miscellaneous Register
address_offset : 0xB718 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT110_TOG

Miscellaneous Register
address_offset : 0xB71C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST110

Post Divider Register
address_offset : 0xB720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT110_SET

Post Divider Register
address_offset : 0xB724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT110_CLR

Post Divider Register
address_offset : 0xB728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT110_TOG

Post Divider Register
address_offset : 0xB72C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE110

Pre Divider Register
address_offset : 0xB730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT110_SET

Pre Divider Register
address_offset : 0xB734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT110_CLR

Pre Divider Register
address_offset : 0xB738 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT110_TOG

Pre Divider Register
address_offset : 0xB73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL110

Access Control Register
address_offset : 0xB770 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT110_SET

Access Control Register
address_offset : 0xB774 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT110_CLR

Access Control Register
address_offset : 0xB778 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT110_TOG

Access Control Register
address_offset : 0xB77C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT111

Target Register
address_offset : 0xB780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT111_SET

Target Register
address_offset : 0xB784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT111_CLR

Target Register
address_offset : 0xB788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT111_TOG

Target Register
address_offset : 0xB78C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC111

Miscellaneous Register
address_offset : 0xB790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT111_SET

Miscellaneous Register
address_offset : 0xB794 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT111_CLR

Miscellaneous Register
address_offset : 0xB798 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT111_TOG

Miscellaneous Register
address_offset : 0xB79C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST111

Post Divider Register
address_offset : 0xB7A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT111_SET

Post Divider Register
address_offset : 0xB7A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT111_CLR

Post Divider Register
address_offset : 0xB7A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT111_TOG

Post Divider Register
address_offset : 0xB7AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE111

Pre Divider Register
address_offset : 0xB7B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

CCGR43

CCM Clock Gating Register
address_offset : 0xB7B20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PRE_ROOT111_SET

Pre Divider Register
address_offset : 0xB7B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT111_CLR

Pre Divider Register
address_offset : 0xB7B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT111_TOG

Pre Divider Register
address_offset : 0xB7BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

CCGR43_SET

CCM Clock Gating Register
address_offset : 0xB7BD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR43_CLR

CCM Clock Gating Register
address_offset : 0xB7C88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR43_TOG

CCM Clock Gating Register
address_offset : 0xB7D3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL111

Access Control Register
address_offset : 0xB7F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT111_SET

Access Control Register
address_offset : 0xB7F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT111_CLR

Access Control Register
address_offset : 0xB7F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT111_TOG

Access Control Register
address_offset : 0xB7FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT112

Target Register
address_offset : 0xB800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT112_SET

Target Register
address_offset : 0xB804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT112_CLR

Target Register
address_offset : 0xB808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT112_TOG

Target Register
address_offset : 0xB80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC112

Miscellaneous Register
address_offset : 0xB810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT112_SET

Miscellaneous Register
address_offset : 0xB814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT112_CLR

Miscellaneous Register
address_offset : 0xB818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT112_TOG

Miscellaneous Register
address_offset : 0xB81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST112

Post Divider Register
address_offset : 0xB820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT112_SET

Post Divider Register
address_offset : 0xB824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT112_CLR

Post Divider Register
address_offset : 0xB828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT112_TOG

Post Divider Register
address_offset : 0xB82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE112

Pre Divider Register
address_offset : 0xB830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT112_SET

Pre Divider Register
address_offset : 0xB834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT112_CLR

Pre Divider Register
address_offset : 0xB838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT112_TOG

Pre Divider Register
address_offset : 0xB83C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL112

Access Control Register
address_offset : 0xB870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT112_SET

Access Control Register
address_offset : 0xB874 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT112_CLR

Access Control Register
address_offset : 0xB878 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT112_TOG

Access Control Register
address_offset : 0xB87C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT113

Target Register
address_offset : 0xB880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT113_SET

Target Register
address_offset : 0xB884 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT113_CLR

Target Register
address_offset : 0xB888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT113_TOG

Target Register
address_offset : 0xB88C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC113

Miscellaneous Register
address_offset : 0xB890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT113_SET

Miscellaneous Register
address_offset : 0xB894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT113_CLR

Miscellaneous Register
address_offset : 0xB898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT113_TOG

Miscellaneous Register
address_offset : 0xB89C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST113

Post Divider Register
address_offset : 0xB8A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT113_SET

Post Divider Register
address_offset : 0xB8A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT113_CLR

Post Divider Register
address_offset : 0xB8A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT113_TOG

Post Divider Register
address_offset : 0xB8AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE113

Pre Divider Register
address_offset : 0xB8B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT113_SET

Pre Divider Register
address_offset : 0xB8B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT113_CLR

Pre Divider Register
address_offset : 0xB8B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT113_TOG

Pre Divider Register
address_offset : 0xB8BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL113

Access Control Register
address_offset : 0xB8F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT113_SET

Access Control Register
address_offset : 0xB8F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT113_CLR

Access Control Register
address_offset : 0xB8F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT113_TOG

Access Control Register
address_offset : 0xB8FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT114

Target Register
address_offset : 0xB900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT114_SET

Target Register
address_offset : 0xB904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT114_CLR

Target Register
address_offset : 0xB908 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT114_TOG

Target Register
address_offset : 0xB90C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC114

Miscellaneous Register
address_offset : 0xB910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT114_SET

Miscellaneous Register
address_offset : 0xB914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT114_CLR

Miscellaneous Register
address_offset : 0xB918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT114_TOG

Miscellaneous Register
address_offset : 0xB91C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST114

Post Divider Register
address_offset : 0xB920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT114_SET

Post Divider Register
address_offset : 0xB924 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT114_CLR

Post Divider Register
address_offset : 0xB928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT114_TOG

Post Divider Register
address_offset : 0xB92C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE114

Pre Divider Register
address_offset : 0xB930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT114_SET

Pre Divider Register
address_offset : 0xB934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT114_CLR

Pre Divider Register
address_offset : 0xB938 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT114_TOG

Pre Divider Register
address_offset : 0xB93C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL114

Access Control Register
address_offset : 0xB970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT114_SET

Access Control Register
address_offset : 0xB974 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT114_CLR

Access Control Register
address_offset : 0xB978 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT114_TOG

Access Control Register
address_offset : 0xB97C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT115

Target Register
address_offset : 0xB980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT115_SET

Target Register
address_offset : 0xB984 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT115_CLR

Target Register
address_offset : 0xB988 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT115_TOG

Target Register
address_offset : 0xB98C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC115

Miscellaneous Register
address_offset : 0xB990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT115_SET

Miscellaneous Register
address_offset : 0xB994 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT115_CLR

Miscellaneous Register
address_offset : 0xB998 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT115_TOG

Miscellaneous Register
address_offset : 0xB99C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST115

Post Divider Register
address_offset : 0xB9A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT115_SET

Post Divider Register
address_offset : 0xB9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT115_CLR

Post Divider Register
address_offset : 0xB9A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT115_TOG

Post Divider Register
address_offset : 0xB9AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE115

Pre Divider Register
address_offset : 0xB9B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT115_SET

Pre Divider Register
address_offset : 0xB9B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT115_CLR

Pre Divider Register
address_offset : 0xB9B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT115_TOG

Pre Divider Register
address_offset : 0xB9BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL115

Access Control Register
address_offset : 0xB9F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT115_SET

Access Control Register
address_offset : 0xB9F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT115_CLR

Access Control Register
address_offset : 0xB9F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT115_TOG

Access Control Register
address_offset : 0xB9FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT116

Target Register
address_offset : 0xBA00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT116_SET

Target Register
address_offset : 0xBA04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT116_CLR

Target Register
address_offset : 0xBA08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT116_TOG

Target Register
address_offset : 0xBA0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC116

Miscellaneous Register
address_offset : 0xBA10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT116_SET

Miscellaneous Register
address_offset : 0xBA14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT116_CLR

Miscellaneous Register
address_offset : 0xBA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT116_TOG

Miscellaneous Register
address_offset : 0xBA1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST116

Post Divider Register
address_offset : 0xBA20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT116_SET

Post Divider Register
address_offset : 0xBA24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT116_CLR

Post Divider Register
address_offset : 0xBA28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT116_TOG

Post Divider Register
address_offset : 0xBA2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE116

Pre Divider Register
address_offset : 0xBA30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT116_SET

Pre Divider Register
address_offset : 0xBA34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT116_CLR

Pre Divider Register
address_offset : 0xBA38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT116_TOG

Pre Divider Register
address_offset : 0xBA3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL116

Access Control Register
address_offset : 0xBA70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT116_SET

Access Control Register
address_offset : 0xBA74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT116_CLR

Access Control Register
address_offset : 0xBA78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT116_TOG

Access Control Register
address_offset : 0xBA7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT117

Target Register
address_offset : 0xBA80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT117_SET

Target Register
address_offset : 0xBA84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT117_CLR

Target Register
address_offset : 0xBA88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT117_TOG

Target Register
address_offset : 0xBA8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC117

Miscellaneous Register
address_offset : 0xBA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT117_SET

Miscellaneous Register
address_offset : 0xBA94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT117_CLR

Miscellaneous Register
address_offset : 0xBA98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT117_TOG

Miscellaneous Register
address_offset : 0xBA9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST117

Post Divider Register
address_offset : 0xBAA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT117_SET

Post Divider Register
address_offset : 0xBAA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT117_CLR

Post Divider Register
address_offset : 0xBAA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT117_TOG

Post Divider Register
address_offset : 0xBAAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE117

Pre Divider Register
address_offset : 0xBAB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT117_SET

Pre Divider Register
address_offset : 0xBAB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT117_CLR

Pre Divider Register
address_offset : 0xBAB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT117_TOG

Pre Divider Register
address_offset : 0xBABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL117

Access Control Register
address_offset : 0xBAF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT117_SET

Access Control Register
address_offset : 0xBAF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT117_CLR

Access Control Register
address_offset : 0xBAF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT117_TOG

Access Control Register
address_offset : 0xBAFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT118

Target Register
address_offset : 0xBB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT118_SET

Target Register
address_offset : 0xBB04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT118_CLR

Target Register
address_offset : 0xBB08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT118_TOG

Target Register
address_offset : 0xBB0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC118

Miscellaneous Register
address_offset : 0xBB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT118_SET

Miscellaneous Register
address_offset : 0xBB14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT118_CLR

Miscellaneous Register
address_offset : 0xBB18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT118_TOG

Miscellaneous Register
address_offset : 0xBB1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST118

Post Divider Register
address_offset : 0xBB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT118_SET

Post Divider Register
address_offset : 0xBB24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT118_CLR

Post Divider Register
address_offset : 0xBB28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT118_TOG

Post Divider Register
address_offset : 0xBB2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE118

Pre Divider Register
address_offset : 0xBB30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT118_SET

Pre Divider Register
address_offset : 0xBB34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT118_CLR

Pre Divider Register
address_offset : 0xBB38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT118_TOG

Pre Divider Register
address_offset : 0xBB3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL118

Access Control Register
address_offset : 0xBB70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT118_SET

Access Control Register
address_offset : 0xBB74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT118_CLR

Access Control Register
address_offset : 0xBB78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT118_TOG

Access Control Register
address_offset : 0xBB7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT119

Target Register
address_offset : 0xBB80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT119_SET

Target Register
address_offset : 0xBB84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT119_CLR

Target Register
address_offset : 0xBB88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT119_TOG

Target Register
address_offset : 0xBB8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC119

Miscellaneous Register
address_offset : 0xBB90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT119_SET

Miscellaneous Register
address_offset : 0xBB94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT119_CLR

Miscellaneous Register
address_offset : 0xBB98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT119_TOG

Miscellaneous Register
address_offset : 0xBB9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST119

Post Divider Register
address_offset : 0xBBA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT119_SET

Post Divider Register
address_offset : 0xBBA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT119_CLR

Post Divider Register
address_offset : 0xBBA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT119_TOG

Post Divider Register
address_offset : 0xBBAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE119

Pre Divider Register
address_offset : 0xBBB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT119_SET

Pre Divider Register
address_offset : 0xBBB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT119_CLR

Pre Divider Register
address_offset : 0xBBB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT119_TOG

Pre Divider Register
address_offset : 0xBBBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

CCGR44

CCM Clock Gating Register
address_offset : 0xBBDE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR44_SET

CCM Clock Gating Register
address_offset : 0xBBE98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL119

Access Control Register
address_offset : 0xBBF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT119_SET

Access Control Register
address_offset : 0xBBF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

CCGR44_CLR

CCM Clock Gating Register
address_offset : 0xBBF50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL_ROOT119_CLR

Access Control Register
address_offset : 0xBBF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT119_TOG

Access Control Register
address_offset : 0xBBFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT120

Target Register
address_offset : 0xBC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

CCGR44_TOG

CCM Clock Gating Register
address_offset : 0xBC008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

TARGET_ROOT120_SET

Target Register
address_offset : 0xBC04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT120_CLR

Target Register
address_offset : 0xBC08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT120_TOG

Target Register
address_offset : 0xBC0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC120

Miscellaneous Register
address_offset : 0xBC10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT120_SET

Miscellaneous Register
address_offset : 0xBC14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT120_CLR

Miscellaneous Register
address_offset : 0xBC18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT120_TOG

Miscellaneous Register
address_offset : 0xBC1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST120

Post Divider Register
address_offset : 0xBC20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT120_SET

Post Divider Register
address_offset : 0xBC24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT120_CLR

Post Divider Register
address_offset : 0xBC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT120_TOG

Post Divider Register
address_offset : 0xBC2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE120

Pre Divider Register
address_offset : 0xBC30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT120_SET

Pre Divider Register
address_offset : 0xBC34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT120_CLR

Pre Divider Register
address_offset : 0xBC38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT120_TOG

Pre Divider Register
address_offset : 0xBC3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL120

Access Control Register
address_offset : 0xBC70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT120_SET

Access Control Register
address_offset : 0xBC74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT120_CLR

Access Control Register
address_offset : 0xBC78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT120_TOG

Access Control Register
address_offset : 0xBC7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT121

Target Register
address_offset : 0xBC80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT121_SET

Target Register
address_offset : 0xBC84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT121_CLR

Target Register
address_offset : 0xBC88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT121_TOG

Target Register
address_offset : 0xBC8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC121

Miscellaneous Register
address_offset : 0xBC90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT121_SET

Miscellaneous Register
address_offset : 0xBC94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT121_CLR

Miscellaneous Register
address_offset : 0xBC98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT121_TOG

Miscellaneous Register
address_offset : 0xBC9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST121

Post Divider Register
address_offset : 0xBCA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT121_SET

Post Divider Register
address_offset : 0xBCA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT121_CLR

Post Divider Register
address_offset : 0xBCA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT121_TOG

Post Divider Register
address_offset : 0xBCAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE121

Pre Divider Register
address_offset : 0xBCB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT121_SET

Pre Divider Register
address_offset : 0xBCB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT121_CLR

Pre Divider Register
address_offset : 0xBCB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT121_TOG

Pre Divider Register
address_offset : 0xBCBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL121

Access Control Register
address_offset : 0xBCF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT121_SET

Access Control Register
address_offset : 0xBCF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT121_CLR

Access Control Register
address_offset : 0xBCF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT121_TOG

Access Control Register
address_offset : 0xBCFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT122

Target Register
address_offset : 0xBD00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT122_SET

Target Register
address_offset : 0xBD04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT122_CLR

Target Register
address_offset : 0xBD08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT122_TOG

Target Register
address_offset : 0xBD0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC122

Miscellaneous Register
address_offset : 0xBD10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT122_SET

Miscellaneous Register
address_offset : 0xBD14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT122_CLR

Miscellaneous Register
address_offset : 0xBD18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT122_TOG

Miscellaneous Register
address_offset : 0xBD1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

PLL_CTRL20

CCM PLL Control Register
address_offset : 0xBD20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

POST122

Post Divider Register
address_offset : 0xBD20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT122_SET

Post Divider Register
address_offset : 0xBD24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT122_CLR

Post Divider Register
address_offset : 0xBD28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT122_TOG

Post Divider Register
address_offset : 0xBD2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE122

Pre Divider Register
address_offset : 0xBD30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT122_SET

Pre Divider Register
address_offset : 0xBD34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT122_CLR

Pre Divider Register
address_offset : 0xBD38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT122_TOG

Pre Divider Register
address_offset : 0xBD3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL122

Access Control Register
address_offset : 0xBD70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT122_SET

Access Control Register
address_offset : 0xBD74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

PLL_CTRL20_SET

CCM PLL Control Register
address_offset : 0xBD78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL_ROOT122_CLR

Access Control Register
address_offset : 0xBD78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT122_TOG

Access Control Register
address_offset : 0xBD7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT123

Target Register
address_offset : 0xBD80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT123_SET

Target Register
address_offset : 0xBD84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT123_CLR

Target Register
address_offset : 0xBD88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT123_TOG

Target Register
address_offset : 0xBD8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC123

Miscellaneous Register
address_offset : 0xBD90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT123_SET

Miscellaneous Register
address_offset : 0xBD94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT123_CLR

Miscellaneous Register
address_offset : 0xBD98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT123_TOG

Miscellaneous Register
address_offset : 0xBD9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST123

Post Divider Register
address_offset : 0xBDA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT123_SET

Post Divider Register
address_offset : 0xBDA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT123_CLR

Post Divider Register
address_offset : 0xBDA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT123_TOG

Post Divider Register
address_offset : 0xBDAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE123

Pre Divider Register
address_offset : 0xBDB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT123_SET

Pre Divider Register
address_offset : 0xBDB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT123_CLR

Pre Divider Register
address_offset : 0xBDB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT123_TOG

Pre Divider Register
address_offset : 0xBDBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PLL_CTRL20_CLR

CCM PLL Control Register
address_offset : 0xBDD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL123

Access Control Register
address_offset : 0xBDF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT123_SET

Access Control Register
address_offset : 0xBDF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT123_CLR

Access Control Register
address_offset : 0xBDF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT123_TOG

Access Control Register
address_offset : 0xBDFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT124

Target Register
address_offset : 0xBE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT124_SET

Target Register
address_offset : 0xBE04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT124_CLR

Target Register
address_offset : 0xBE08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT124_TOG

Target Register
address_offset : 0xBE0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC124

Miscellaneous Register
address_offset : 0xBE10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT124_SET

Miscellaneous Register
address_offset : 0xBE14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT124_CLR

Miscellaneous Register
address_offset : 0xBE18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT124_TOG

Miscellaneous Register
address_offset : 0xBE1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST124

Post Divider Register
address_offset : 0xBE20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT124_SET

Post Divider Register
address_offset : 0xBE24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PLL_CTRL20_TOG

CCM PLL Control Register
address_offset : 0xBE28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

POST_ROOT124_CLR

Post Divider Register
address_offset : 0xBE28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT124_TOG

Post Divider Register
address_offset : 0xBE2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE124

Pre Divider Register
address_offset : 0xBE30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT124_SET

Pre Divider Register
address_offset : 0xBE34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT124_CLR

Pre Divider Register
address_offset : 0xBE38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT124_TOG

Pre Divider Register
address_offset : 0xBE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL124

Access Control Register
address_offset : 0xBE70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT124_SET

Access Control Register
address_offset : 0xBE74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT124_CLR

Access Control Register
address_offset : 0xBE78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT124_TOG

Access Control Register
address_offset : 0xBE7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT125

Target Register
address_offset : 0xBE80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT125_SET

Target Register
address_offset : 0xBE84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT125_CLR

Target Register
address_offset : 0xBE88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT125_TOG

Target Register
address_offset : 0xBE8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC125

Miscellaneous Register
address_offset : 0xBE90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT125_SET

Miscellaneous Register
address_offset : 0xBE94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT125_CLR

Miscellaneous Register
address_offset : 0xBE98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT125_TOG

Miscellaneous Register
address_offset : 0xBE9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST125

Post Divider Register
address_offset : 0xBEA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT125_SET

Post Divider Register
address_offset : 0xBEA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT125_CLR

Post Divider Register
address_offset : 0xBEA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT125_TOG

Post Divider Register
address_offset : 0xBEAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE125

Pre Divider Register
address_offset : 0xBEB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT125_SET

Pre Divider Register
address_offset : 0xBEB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT125_CLR

Pre Divider Register
address_offset : 0xBEB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT125_TOG

Pre Divider Register
address_offset : 0xBEBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL125

Access Control Register
address_offset : 0xBEF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT125_SET

Access Control Register
address_offset : 0xBEF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT125_CLR

Access Control Register
address_offset : 0xBEF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT125_TOG

Access Control Register
address_offset : 0xBEFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT126

Target Register
address_offset : 0xBF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT126_SET

Target Register
address_offset : 0xBF04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT126_CLR

Target Register
address_offset : 0xBF08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT126_TOG

Target Register
address_offset : 0xBF0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC126

Miscellaneous Register
address_offset : 0xBF10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT126_SET

Miscellaneous Register
address_offset : 0xBF14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT126_CLR

Miscellaneous Register
address_offset : 0xBF18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT126_TOG

Miscellaneous Register
address_offset : 0xBF1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST126

Post Divider Register
address_offset : 0xBF20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT126_SET

Post Divider Register
address_offset : 0xBF24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT126_CLR

Post Divider Register
address_offset : 0xBF28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT126_TOG

Post Divider Register
address_offset : 0xBF2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE126

Pre Divider Register
address_offset : 0xBF30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT126_SET

Pre Divider Register
address_offset : 0xBF34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT126_CLR

Pre Divider Register
address_offset : 0xBF38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT126_TOG

Pre Divider Register
address_offset : 0xBF3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL126

Access Control Register
address_offset : 0xBF70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT126_SET

Access Control Register
address_offset : 0xBF74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT126_CLR

Access Control Register
address_offset : 0xBF78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT126_TOG

Access Control Register
address_offset : 0xBF7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT127

Target Register
address_offset : 0xBF80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT127_SET

Target Register
address_offset : 0xBF84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT127_CLR

Target Register
address_offset : 0xBF88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT127_TOG

Target Register
address_offset : 0xBF8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC127

Miscellaneous Register
address_offset : 0xBF90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT127_SET

Miscellaneous Register
address_offset : 0xBF94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT127_CLR

Miscellaneous Register
address_offset : 0xBF98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT127_TOG

Miscellaneous Register
address_offset : 0xBF9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST127

Post Divider Register
address_offset : 0xBFA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT127_SET

Post Divider Register
address_offset : 0xBFA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT127_CLR

Post Divider Register
address_offset : 0xBFA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT127_TOG

Post Divider Register
address_offset : 0xBFAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE127

Pre Divider Register
address_offset : 0xBFB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT127_SET

Pre Divider Register
address_offset : 0xBFB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT127_CLR

Pre Divider Register
address_offset : 0xBFB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT127_TOG

Pre Divider Register
address_offset : 0xBFBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL127

Access Control Register
address_offset : 0xBFF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT127_SET

Access Control Register
address_offset : 0xBFF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT127_CLR

Access Control Register
address_offset : 0xBFF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT127_TOG

Access Control Register
address_offset : 0xBFFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

GPR0_TOG

General Purpose Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP0 : Timeout cycle count of ipg_clk, when perform read and write.
bits : 0 - 31 (32 bit)
access : read-write

TARGET_ROOT128

Target Register
address_offset : 0xC000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT128_SET

Target Register
address_offset : 0xC004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT128_CLR

Target Register
address_offset : 0xC008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

CCGR45

CCM Clock Gating Register
address_offset : 0xC00B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

TARGET_ROOT128_TOG

Target Register
address_offset : 0xC00C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

CCGR1

CCM Clock Gating Register
address_offset : 0xC010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

MISC128

Miscellaneous Register
address_offset : 0xC010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT128_SET

Miscellaneous Register
address_offset : 0xC014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

CCGR45_SET

CCM Clock Gating Register
address_offset : 0xC016C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

MISC_ROOT128_CLR

Miscellaneous Register
address_offset : 0xC018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

CCGR1_SET

CCM Clock Gating Register
address_offset : 0xC01C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

MISC_ROOT128_TOG

Miscellaneous Register
address_offset : 0xC01C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST128

Post Divider Register
address_offset : 0xC020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

CCGR45_CLR

CCM Clock Gating Register
address_offset : 0xC0228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

POST_ROOT128_SET

Post Divider Register
address_offset : 0xC024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

CCGR1_CLR

CCM Clock Gating Register
address_offset : 0xC028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

POST_ROOT128_CLR

Post Divider Register
address_offset : 0xC028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT128_TOG

Post Divider Register
address_offset : 0xC02C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

CCGR45_TOG

CCM Clock Gating Register
address_offset : 0xC02E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PRE128

Pre Divider Register
address_offset : 0xC030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

CCGR1_TOG

CCM Clock Gating Register
address_offset : 0xC034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PRE_ROOT128_SET

Pre Divider Register
address_offset : 0xC034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT128_CLR

Pre Divider Register
address_offset : 0xC038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT128_TOG

Pre Divider Register
address_offset : 0xC03C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL128

Access Control Register
address_offset : 0xC070 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT128_SET

Access Control Register
address_offset : 0xC074 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT128_CLR

Access Control Register
address_offset : 0xC078 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT128_TOG

Access Control Register
address_offset : 0xC07C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT129

Target Register
address_offset : 0xC080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT129_SET

Target Register
address_offset : 0xC084 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT129_CLR

Target Register
address_offset : 0xC088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT129_TOG

Target Register
address_offset : 0xC08C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC129

Miscellaneous Register
address_offset : 0xC090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT129_SET

Miscellaneous Register
address_offset : 0xC094 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT129_CLR

Miscellaneous Register
address_offset : 0xC098 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT129_TOG

Miscellaneous Register
address_offset : 0xC09C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST129

Post Divider Register
address_offset : 0xC0A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT129_SET

Post Divider Register
address_offset : 0xC0A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT129_CLR

Post Divider Register
address_offset : 0xC0A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT129_TOG

Post Divider Register
address_offset : 0xC0AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE129

Pre Divider Register
address_offset : 0xC0B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT129_SET

Pre Divider Register
address_offset : 0xC0B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT129_CLR

Pre Divider Register
address_offset : 0xC0B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT129_TOG

Pre Divider Register
address_offset : 0xC0BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL129

Access Control Register
address_offset : 0xC0F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT129_SET

Access Control Register
address_offset : 0xC0F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT129_CLR

Access Control Register
address_offset : 0xC0F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT129_TOG

Access Control Register
address_offset : 0xC0FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT130

Target Register
address_offset : 0xC100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT130_SET

Target Register
address_offset : 0xC104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT130_CLR

Target Register
address_offset : 0xC108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT130_TOG

Target Register
address_offset : 0xC10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC130

Miscellaneous Register
address_offset : 0xC110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT130_SET

Miscellaneous Register
address_offset : 0xC114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT130_CLR

Miscellaneous Register
address_offset : 0xC118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT130_TOG

Miscellaneous Register
address_offset : 0xC11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST130

Post Divider Register
address_offset : 0xC120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT130_SET

Post Divider Register
address_offset : 0xC124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT130_CLR

Post Divider Register
address_offset : 0xC128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT130_TOG

Post Divider Register
address_offset : 0xC12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE130

Pre Divider Register
address_offset : 0xC130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT130_SET

Pre Divider Register
address_offset : 0xC134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT130_CLR

Pre Divider Register
address_offset : 0xC138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT130_TOG

Pre Divider Register
address_offset : 0xC13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL130

Access Control Register
address_offset : 0xC170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT130_SET

Access Control Register
address_offset : 0xC174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT130_CLR

Access Control Register
address_offset : 0xC178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT130_TOG

Access Control Register
address_offset : 0xC17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT131

Target Register
address_offset : 0xC180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT131_SET

Target Register
address_offset : 0xC184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT131_CLR

Target Register
address_offset : 0xC188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT131_TOG

Target Register
address_offset : 0xC18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC131

Miscellaneous Register
address_offset : 0xC190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT131_SET

Miscellaneous Register
address_offset : 0xC194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT131_CLR

Miscellaneous Register
address_offset : 0xC198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT131_TOG

Miscellaneous Register
address_offset : 0xC19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST131

Post Divider Register
address_offset : 0xC1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT131_SET

Post Divider Register
address_offset : 0xC1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT131_CLR

Post Divider Register
address_offset : 0xC1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT131_TOG

Post Divider Register
address_offset : 0xC1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE131

Pre Divider Register
address_offset : 0xC1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT131_SET

Pre Divider Register
address_offset : 0xC1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT131_CLR

Pre Divider Register
address_offset : 0xC1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT131_TOG

Pre Divider Register
address_offset : 0xC1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL131

Access Control Register
address_offset : 0xC1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT131_SET

Access Control Register
address_offset : 0xC1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT131_CLR

Access Control Register
address_offset : 0xC1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT131_TOG

Access Control Register
address_offset : 0xC1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT132

Target Register
address_offset : 0xC200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT132_SET

Target Register
address_offset : 0xC204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT132_CLR

Target Register
address_offset : 0xC208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT132_TOG

Target Register
address_offset : 0xC20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC132

Miscellaneous Register
address_offset : 0xC210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT132_SET

Miscellaneous Register
address_offset : 0xC214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT132_CLR

Miscellaneous Register
address_offset : 0xC218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT132_TOG

Miscellaneous Register
address_offset : 0xC21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST132

Post Divider Register
address_offset : 0xC220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT132_SET

Post Divider Register
address_offset : 0xC224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT132_CLR

Post Divider Register
address_offset : 0xC228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT132_TOG

Post Divider Register
address_offset : 0xC22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE132

Pre Divider Register
address_offset : 0xC230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT132_SET

Pre Divider Register
address_offset : 0xC234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT132_CLR

Pre Divider Register
address_offset : 0xC238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT132_TOG

Pre Divider Register
address_offset : 0xC23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL132

Access Control Register
address_offset : 0xC270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT132_SET

Access Control Register
address_offset : 0xC274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT132_CLR

Access Control Register
address_offset : 0xC278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT132_TOG

Access Control Register
address_offset : 0xC27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT133

Target Register
address_offset : 0xC280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT133_SET

Target Register
address_offset : 0xC284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT133_CLR

Target Register
address_offset : 0xC288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT133_TOG

Target Register
address_offset : 0xC28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC133

Miscellaneous Register
address_offset : 0xC290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT133_SET

Miscellaneous Register
address_offset : 0xC294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT133_CLR

Miscellaneous Register
address_offset : 0xC298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT133_TOG

Miscellaneous Register
address_offset : 0xC29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST133

Post Divider Register
address_offset : 0xC2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT133_SET

Post Divider Register
address_offset : 0xC2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT133_CLR

Post Divider Register
address_offset : 0xC2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT133_TOG

Post Divider Register
address_offset : 0xC2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE133

Pre Divider Register
address_offset : 0xC2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT133_SET

Pre Divider Register
address_offset : 0xC2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT133_CLR

Pre Divider Register
address_offset : 0xC2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT133_TOG

Pre Divider Register
address_offset : 0xC2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL133

Access Control Register
address_offset : 0xC2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT133_SET

Access Control Register
address_offset : 0xC2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT133_CLR

Access Control Register
address_offset : 0xC2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT133_TOG

Access Control Register
address_offset : 0xC2FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT134

Target Register
address_offset : 0xC300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT134_SET

Target Register
address_offset : 0xC304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT134_CLR

Target Register
address_offset : 0xC308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT134_TOG

Target Register
address_offset : 0xC30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC134

Miscellaneous Register
address_offset : 0xC310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT134_SET

Miscellaneous Register
address_offset : 0xC314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT134_CLR

Miscellaneous Register
address_offset : 0xC318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT134_TOG

Miscellaneous Register
address_offset : 0xC31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST134

Post Divider Register
address_offset : 0xC320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT134_SET

Post Divider Register
address_offset : 0xC324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT134_CLR

Post Divider Register
address_offset : 0xC328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT134_TOG

Post Divider Register
address_offset : 0xC32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE134

Pre Divider Register
address_offset : 0xC330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT134_SET

Pre Divider Register
address_offset : 0xC334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT134_CLR

Pre Divider Register
address_offset : 0xC338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT134_TOG

Pre Divider Register
address_offset : 0xC33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL134

Access Control Register
address_offset : 0xC370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT134_SET

Access Control Register
address_offset : 0xC374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT134_CLR

Access Control Register
address_offset : 0xC378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT134_TOG

Access Control Register
address_offset : 0xC37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT135

Target Register
address_offset : 0xC380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT135_SET

Target Register
address_offset : 0xC384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT135_CLR

Target Register
address_offset : 0xC388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT135_TOG

Target Register
address_offset : 0xC38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC135

Miscellaneous Register
address_offset : 0xC390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT135_SET

Miscellaneous Register
address_offset : 0xC394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT135_CLR

Miscellaneous Register
address_offset : 0xC398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT135_TOG

Miscellaneous Register
address_offset : 0xC39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST135

Post Divider Register
address_offset : 0xC3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT135_SET

Post Divider Register
address_offset : 0xC3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT135_CLR

Post Divider Register
address_offset : 0xC3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT135_TOG

Post Divider Register
address_offset : 0xC3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE135

Pre Divider Register
address_offset : 0xC3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT135_SET

Pre Divider Register
address_offset : 0xC3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT135_CLR

Pre Divider Register
address_offset : 0xC3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT135_TOG

Pre Divider Register
address_offset : 0xC3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL135

Access Control Register
address_offset : 0xC3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT135_SET

Access Control Register
address_offset : 0xC3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT135_CLR

Access Control Register
address_offset : 0xC3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT135_TOG

Access Control Register
address_offset : 0xC3FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT136

Target Register
address_offset : 0xC400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT136_SET

Target Register
address_offset : 0xC404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT136_CLR

Target Register
address_offset : 0xC408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT136_TOG

Target Register
address_offset : 0xC40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC136

Miscellaneous Register
address_offset : 0xC410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT136_SET

Miscellaneous Register
address_offset : 0xC414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT136_CLR

Miscellaneous Register
address_offset : 0xC418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT136_TOG

Miscellaneous Register
address_offset : 0xC41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST136

Post Divider Register
address_offset : 0xC420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT136_SET

Post Divider Register
address_offset : 0xC424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT136_CLR

Post Divider Register
address_offset : 0xC428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT136_TOG

Post Divider Register
address_offset : 0xC42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE136

Pre Divider Register
address_offset : 0xC430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT136_SET

Pre Divider Register
address_offset : 0xC434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT136_CLR

Pre Divider Register
address_offset : 0xC438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

CCGR46

CCM Clock Gating Register
address_offset : 0xC4390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PRE_ROOT136_TOG

Pre Divider Register
address_offset : 0xC43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

CCGR46_SET

CCM Clock Gating Register
address_offset : 0xC4450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR46_CLR

CCM Clock Gating Register
address_offset : 0xC4510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR46_TOG

CCM Clock Gating Register
address_offset : 0xC45D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL136

Access Control Register
address_offset : 0xC470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT136_SET

Access Control Register
address_offset : 0xC474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT136_CLR

Access Control Register
address_offset : 0xC478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT136_TOG

Access Control Register
address_offset : 0xC47C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT137

Target Register
address_offset : 0xC480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT137_SET

Target Register
address_offset : 0xC484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT137_CLR

Target Register
address_offset : 0xC488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT137_TOG

Target Register
address_offset : 0xC48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC137

Miscellaneous Register
address_offset : 0xC490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT137_SET

Miscellaneous Register
address_offset : 0xC494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT137_CLR

Miscellaneous Register
address_offset : 0xC498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT137_TOG

Miscellaneous Register
address_offset : 0xC49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST137

Post Divider Register
address_offset : 0xC4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT137_SET

Post Divider Register
address_offset : 0xC4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT137_CLR

Post Divider Register
address_offset : 0xC4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT137_TOG

Post Divider Register
address_offset : 0xC4AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE137

Pre Divider Register
address_offset : 0xC4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT137_SET

Pre Divider Register
address_offset : 0xC4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT137_CLR

Pre Divider Register
address_offset : 0xC4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT137_TOG

Pre Divider Register
address_offset : 0xC4BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL137

Access Control Register
address_offset : 0xC4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT137_SET

Access Control Register
address_offset : 0xC4F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT137_CLR

Access Control Register
address_offset : 0xC4F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT137_TOG

Access Control Register
address_offset : 0xC4FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT138

Target Register
address_offset : 0xC500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT138_SET

Target Register
address_offset : 0xC504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT138_CLR

Target Register
address_offset : 0xC508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT138_TOG

Target Register
address_offset : 0xC50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC138

Miscellaneous Register
address_offset : 0xC510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT138_SET

Miscellaneous Register
address_offset : 0xC514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT138_CLR

Miscellaneous Register
address_offset : 0xC518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT138_TOG

Miscellaneous Register
address_offset : 0xC51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST138

Post Divider Register
address_offset : 0xC520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT138_SET

Post Divider Register
address_offset : 0xC524 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT138_CLR

Post Divider Register
address_offset : 0xC528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT138_TOG

Post Divider Register
address_offset : 0xC52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE138

Pre Divider Register
address_offset : 0xC530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT138_SET

Pre Divider Register
address_offset : 0xC534 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT138_CLR

Pre Divider Register
address_offset : 0xC538 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT138_TOG

Pre Divider Register
address_offset : 0xC53C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL138

Access Control Register
address_offset : 0xC570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT138_SET

Access Control Register
address_offset : 0xC574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT138_CLR

Access Control Register
address_offset : 0xC578 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT138_TOG

Access Control Register
address_offset : 0xC57C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT139

Target Register
address_offset : 0xC580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT139_SET

Target Register
address_offset : 0xC584 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT139_CLR

Target Register
address_offset : 0xC588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT139_TOG

Target Register
address_offset : 0xC58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC139

Miscellaneous Register
address_offset : 0xC590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT139_SET

Miscellaneous Register
address_offset : 0xC594 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT139_CLR

Miscellaneous Register
address_offset : 0xC598 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT139_TOG

Miscellaneous Register
address_offset : 0xC59C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST139

Post Divider Register
address_offset : 0xC5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT139_SET

Post Divider Register
address_offset : 0xC5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT139_CLR

Post Divider Register
address_offset : 0xC5A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT139_TOG

Post Divider Register
address_offset : 0xC5AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE139

Pre Divider Register
address_offset : 0xC5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT139_SET

Pre Divider Register
address_offset : 0xC5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT139_CLR

Pre Divider Register
address_offset : 0xC5B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT139_TOG

Pre Divider Register
address_offset : 0xC5BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

ACCESS_CTRL139

Access Control Register
address_offset : 0xC5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT139_SET

Access Control Register
address_offset : 0xC5F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT139_CLR

Access Control Register
address_offset : 0xC5F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT139_TOG

Access Control Register
address_offset : 0xC5FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT140

Target Register
address_offset : 0xC600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT140_SET

Target Register
address_offset : 0xC604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT140_CLR

Target Register
address_offset : 0xC608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT140_TOG

Target Register
address_offset : 0xC60C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC140

Miscellaneous Register
address_offset : 0xC610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT140_SET

Miscellaneous Register
address_offset : 0xC614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT140_CLR

Miscellaneous Register
address_offset : 0xC618 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT140_TOG

Miscellaneous Register
address_offset : 0xC61C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST140

Post Divider Register
address_offset : 0xC620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT140_SET

Post Divider Register
address_offset : 0xC624 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT140_CLR

Post Divider Register
address_offset : 0xC628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT140_TOG

Post Divider Register
address_offset : 0xC62C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE140

Pre Divider Register
address_offset : 0xC630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT140_SET

Pre Divider Register
address_offset : 0xC634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT140_CLR

Pre Divider Register
address_offset : 0xC638 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT140_TOG

Pre Divider Register
address_offset : 0xC63C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PLL_CTRL21

CCM PLL Control Register
address_offset : 0xC670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL140

Access Control Register
address_offset : 0xC670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT140_SET

Access Control Register
address_offset : 0xC674 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT140_CLR

Access Control Register
address_offset : 0xC678 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT140_TOG

Access Control Register
address_offset : 0xC67C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

TARGET_ROOT141

Target Register
address_offset : 0xC680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT141_SET

Target Register
address_offset : 0xC684 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT141_CLR

Target Register
address_offset : 0xC688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divider divide the number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

TARGET_ROOT141_TOG

Target Register
address_offset : 0xC68C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

PRE_PODF : Pre divide divide number Divider value is n+1 This field does not apply for CORE, DRAM, DRAM_PHYM
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_0

Divide by 1

0x1 : PRE_PODF_1

Divide by 2

0x2 : PRE_PODF_2

Divide by 3

0x3 : PRE_PODF_3

Divide by 4

0x4 : PRE_PODF_4

Divide by 5

0x5 : PRE_PODF_5

Divide by 6

0x6 : PRE_PODF_6

Divide by 7

0x7 : PRE_PODF_7

Divide by 8

End of enumeration elements list.

MUX : Selection of clock sources This field is 1 bit long for DRAM and CORE
bits : 24 - 26 (3 bit)
access : read-write

ENABLE : Enable this clock
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLE_0

clock root is OFF

0x1 : ENABLE_1

clock root is ON

End of enumeration elements list.

MISC141

Miscellaneous Register
address_offset : 0xC690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT141_SET

Miscellaneous Register
address_offset : 0xC694 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT141_CLR

Miscellaneous Register
address_offset : 0xC698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

MISC_ROOT141_TOG

Miscellaneous Register
address_offset : 0xC69C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTHEN_FAIL : This sticky bit reflects access restricted by access control of this clock
bits : 0 - 0 (1 bit)
access : read-write

TIMEOUT : This sticky bit reflects time out happened during accessing this clock
bits : 4 - 4 (1 bit)
access : read-write

VIOLATE : This sticky bit reflects access violation in normal interface of this clock
bits : 8 - 8 (1 bit)
access : read-write

POST141

Post Divider Register
address_offset : 0xC6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT141_SET

Post Divider Register
address_offset : 0xC6A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT141_CLR

Post Divider Register
address_offset : 0xC6A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide the number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

POST_ROOT141_TOG

Post Divider Register
address_offset : 0xC6AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POST_PODF : Post divider divide number Divider value is n + 1 For CORE, this field is 3 bit long
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : POST_PODF_0

Divide by 1

0x1 : POST_PODF_1

Divide by 2

0x2 : POST_PODF_2

Divide by 3

0x3 : POST_PODF_3

Divide by 4

0x4 : POST_PODF_4

Divide by 5

0x5 : POST_PODF_5

Divide by 6

0x3F : POST_PODF_63

Divide by 64

End of enumeration elements list.

BUSY1 : Post divider is applying new set value
bits : 7 - 7 (1 bit)
access : read-only

SELECT : Selection of pre clock branches This field is not applied in IP
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SELECT_0

select branch A

0x1 : SELECT_1

select branch B

End of enumeration elements list.

BUSY2 : Clock switching multiplexer is applying new setting
bits : 31 - 31 (1 bit)
access : read-only

PRE141

Pre Divider Register
address_offset : 0xC6B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT141_SET

Pre Divider Register
address_offset : 0xC6B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applying field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT141_CLR

Pre Divider Register
address_offset : 0xC6B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch A is applied This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PRE_ROOT141_TOG

Pre Divider Register
address_offset : 0xC6BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRE_PODF_B : Pre divider divide number for branch B Divider value is n + 1
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_B_0

Divide by 1

0x1 : PRE_PODF_B_1

Divide by 2

0x2 : PRE_PODF_B_2

Divide by 3

0x3 : PRE_PODF_B_3

Divide by 4

0x4 : PRE_PODF_B_4

Divide by 5

0x5 : PRE_PODF_B_5

Divide by 6

0x6 : PRE_PODF_B_6

Divide by 7

0x7 : PRE_PODF_B_7

Divide by 8

End of enumeration elements list.

BUSY0 : Pre divider value for branch a is applied field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 3 - 3 (1 bit)
access : read-only

MUX_B : Selection control of multiplexer of branch B This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 8 - 10 (3 bit)
access : read-write

EN_B : Branch B clock gate control This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EN_B_0

Clock shutdown

0x1 : EN_B_1

Clock ON

End of enumeration elements list.

BUSY1 : EN_B is applied to field This field does not apply for CORE, IP,DRAM, DRAM_PHYM
bits : 15 - 15 (1 bit)
access : read-only

PRE_PODF_A : Pre divider divide number for branch A Divider value is n + 1
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : PRE_PODF_A_0

Divide by 1

0x1 : PRE_PODF_A_1

Divide by 2

0x2 : PRE_PODF_A_2

Divide by 3

0x3 : PRE_PODF_A_3

Divide by 4

0x4 : PRE_PODF_A_4

Divide by 5

0x5 : PRE_PODF_A_5

Divide by 6

0x6 : PRE_PODF_A_6

Divide by 7

0x7 : PRE_PODF_A_7

Divide by 8

End of enumeration elements list.

BUSY3 : Pre divider value for branch A is applied This field applies to DRAM and DRAM_PHYM
bits : 19 - 19 (1 bit)
access : read-only

MUX_A : Selection control of multiplexer of branch A This field applies to DRAM and DRAM_PHYM
bits : 24 - 26 (3 bit)
access : read-write

EN_A : Branch A clock gate control This field applies to DRAM and DRAM_PHYM
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : EN_A_0

Clock shutdown

0x1 : EN_A_1

clock ON

End of enumeration elements list.

BUSY4 : EN_A field is applied to field This field applies to DRAM and DRAM_PHYM
bits : 31 - 31 (1 bit)
access : read-only

PLL_CTRL21_SET

CCM PLL Control Register
address_offset : 0xC6CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

ACCESS_CTRL141

Access Control Register
address_offset : 0xC6F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT141_SET

Access Control Register
address_offset : 0xC6F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT141_CLR

Access Control Register
address_offset : 0xC6F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

ACCESS_CTRL_ROOT141_TOG

Access Control Register
address_offset : 0xC6FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOMAIN0_INFO : Information from domain 0 to pass to others This field can only be changed by domain 0
bits : 0 - 3 (4 bit)
access : read-write

DOMAIN1_INFO : Information from domain 1 to pass to others This field can only be changed by domain 1
bits : 4 - 7 (4 bit)
access : read-write

DOMAIN2_INFO : Information from domain 2 to pass to others This field can only be changed by domain 2
bits : 8 - 11 (4 bit)
access : read-write

DOMAIN3_INFO : Information from domain 3 to pass to others This field can only be changed by domain 3
bits : 12 - 15 (4 bit)
access : read-write

OWNER_ID : Current domain that owns semaphore This field is meaningless when MUTEX is 0
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0 : OWNER_ID_0

domaino

0x1 : OWNER_ID_1

domain1

0x2 : OWNER_ID_2

domain2

0x3 : OWNER_ID_3

domain3

End of enumeration elements list.

MUTEX : Semaphore to control access
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MUTEX_0

Semaphore is free to take

0x1 : MUTEX_1

Semaphore is taken

End of enumeration elements list.

DOMAIN0_WHITELIST : White list of domains that can change setting of this clock root
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN0_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN0_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN1_WHITELIST : White list of domains that can change setting of this clock root
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN1_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN1_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN2_WHITELIST : White list of domains that can change setting of this clock root
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN2_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN2_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

DOMAIN3_WHITELIST : White list of domains that can change setting of this clock root
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DOMAIN3_WHITELIST_0

Domain cannot change the setting

0x1 : DOMAIN3_WHITELIST_1

Domain can change the setting

End of enumeration elements list.

SEMA_EN : Enable internal semaphore This field cannot be changed when lock bit is 1
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SEMA_EN_0

Disable

0x1 : SEMA_EN_1

Enable

End of enumeration elements list.

LOCK : Lock this clock root to use access control This bit can be set to 1 by software, and can be cleared only by system reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : LOCK_0

Access control inactive

0x1 : LOCK_1

Access control active

End of enumeration elements list.

PLL_CTRL21_CLR

CCM PLL Control Register
address_offset : 0xC728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL21_TOG

CCM PLL Control Register
address_offset : 0xC784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR47

CCM Clock Gating Register
address_offset : 0xC8680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR47_SET

CCM Clock Gating Register
address_offset : 0xC8744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR47_CLR

CCM Clock Gating Register
address_offset : 0xC8808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR47_TOG

CCM Clock Gating Register
address_offset : 0xC88CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR48

CCM Clock Gating Register
address_offset : 0xCC980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR48_SET

CCM Clock Gating Register
address_offset : 0xCCA48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR48_CLR

CCM Clock Gating Register
address_offset : 0xCCB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR48_TOG

CCM Clock Gating Register
address_offset : 0xCCBD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL22

CCM PLL Control Register
address_offset : 0xCFD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL22_SET

CCM PLL Control Register
address_offset : 0xD030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL22_CLR

CCM PLL Control Register
address_offset : 0xD090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR49

CCM Clock Gating Register
address_offset : 0xD0C90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR49_SET

CCM Clock Gating Register
address_offset : 0xD0D5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR49_CLR

CCM Clock Gating Register
address_offset : 0xD0E28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR49_TOG

CCM Clock Gating Register
address_offset : 0xD0EF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL22_TOG

CCM PLL Control Register
address_offset : 0xD0F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR50

CCM Clock Gating Register
address_offset : 0xD4FB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR50_SET

CCM Clock Gating Register
address_offset : 0xD5080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR50_CLR

CCM Clock Gating Register
address_offset : 0xD5150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR50_TOG

CCM Clock Gating Register
address_offset : 0xD5220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR51

CCM Clock Gating Register
address_offset : 0xD92E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR51_SET

CCM Clock Gating Register
address_offset : 0xD93B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL23

CCM PLL Control Register
address_offset : 0xD940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR51_CLR

CCM Clock Gating Register
address_offset : 0xD9488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR51_TOG

CCM Clock Gating Register
address_offset : 0xD955C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL23_SET

CCM PLL Control Register
address_offset : 0xD9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL23_CLR

CCM PLL Control Register
address_offset : 0xDA08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL23_TOG

CCM PLL Control Register
address_offset : 0xDA6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR52

CCM Clock Gating Register
address_offset : 0xDD620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR52_SET

CCM Clock Gating Register
address_offset : 0xDD6F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR52_CLR

CCM Clock Gating Register
address_offset : 0xDD7D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR52_TOG

CCM Clock Gating Register
address_offset : 0xDD8A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR53

CCM Clock Gating Register
address_offset : 0xE1970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR53_SET

CCM Clock Gating Register
address_offset : 0xE1A4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR53_CLR

CCM Clock Gating Register
address_offset : 0xE1B28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR53_TOG

CCM Clock Gating Register
address_offset : 0xE1C04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL24

CCM PLL Control Register
address_offset : 0xE2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL24_SET

CCM PLL Control Register
address_offset : 0xE328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL24_CLR

CCM PLL Control Register
address_offset : 0xE390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL24_TOG

CCM PLL Control Register
address_offset : 0xE3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR54

CCM Clock Gating Register
address_offset : 0xE5CD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR54_SET

CCM Clock Gating Register
address_offset : 0xE5DB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR54_CLR

CCM Clock Gating Register
address_offset : 0xE5E90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR54_TOG

CCM Clock Gating Register
address_offset : 0xE5F70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR55

CCM Clock Gating Register
address_offset : 0xEA040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR55_SET

CCM Clock Gating Register
address_offset : 0xEA124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR55_CLR

CCM Clock Gating Register
address_offset : 0xEA208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR55_TOG

CCM Clock Gating Register
address_offset : 0xEA2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL25

CCM PLL Control Register
address_offset : 0xEC50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL25_SET

CCM PLL Control Register
address_offset : 0xECBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL25_CLR

CCM PLL Control Register
address_offset : 0xED28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL25_TOG

CCM PLL Control Register
address_offset : 0xED94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR56

CCM Clock Gating Register
address_offset : 0xEE3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR56_SET

CCM Clock Gating Register
address_offset : 0xEE4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR56_CLR

CCM Clock Gating Register
address_offset : 0xEE590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR56_TOG

CCM Clock Gating Register
address_offset : 0xEE678 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR57

CCM Clock Gating Register
address_offset : 0xF2750 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR57_SET

CCM Clock Gating Register
address_offset : 0xF283C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR57_CLR

CCM Clock Gating Register
address_offset : 0xF2928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR57_TOG

CCM Clock Gating Register
address_offset : 0xF2A14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL26

CCM PLL Control Register
address_offset : 0xF5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL26_SET

CCM PLL Control Register
address_offset : 0xF660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR58

CCM Clock Gating Register
address_offset : 0xF6AF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR58_SET

CCM Clock Gating Register
address_offset : 0xF6BE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR58_CLR

CCM Clock Gating Register
address_offset : 0xF6CD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL26_CLR

CCM PLL Control Register
address_offset : 0xF6D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR58_TOG

CCM Clock Gating Register
address_offset : 0xF6DC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL26_TOG

CCM PLL Control Register
address_offset : 0xF740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR59

CCM Clock Gating Register
address_offset : 0xFAEA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR59_SET

CCM Clock Gating Register
address_offset : 0xFAF94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR59_CLR

CCM Clock Gating Register
address_offset : 0xFB088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR59_TOG

CCM Clock Gating Register
address_offset : 0xFB17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR60

CCM Clock Gating Register
address_offset : 0xFF260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR60_SET

CCM Clock Gating Register
address_offset : 0xFF358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR60_CLR

CCM Clock Gating Register
address_offset : 0xFF450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

CCGR60_TOG

CCM Clock Gating Register
address_offset : 0xFF548 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

PLL_CTRL27

CCM PLL Control Register
address_offset : 0xFFA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETTING0 : Clock gate control setting for domain 0. This field can only be written by domain 0.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : SETTING0_0

Domain clocks not needed

0x1 : SETTING0_1

Domain clocks needed when in RUN

0x2 : SETTING0_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING0_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING1 : Clock gate control setting for domain 1. This field can only be written by domain 1.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : SETTING1_0

Domain clocks not needed

0x1 : SETTING1_1

Domain clocks needed when in RUN

0x2 : SETTING1_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING1_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING2 : Clock gate control setting for domain 2. This field can only be written by domain 2
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : SETTING2_0

Domain clocks not needed

0x1 : SETTING2_1

Domain clocks needed when in RUN

0x2 : SETTING2_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING2_3

Domain clocks needed all the time

End of enumeration elements list.

SETTING3 : Clock gate control setting for domain 3. This field can only be written by domain 3
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : SETTING3_0

Domain clocks not needed

0x1 : SETTING3_1

Domain clocks needed when in RUN

0x2 : SETTING3_2

Domain clocks needed when in RUN and WAIT

0x3 : SETTING3_3

Domain clocks needed all the time

End of enumeration elements list.

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ChipSelect

CCM

Peripheral Memory Blocks

Registers

GPR0

PLL_CTRL0

PLL_CTRL27_SET

CCGR2

CCGR2_SET

CCGR2_CLR

CCGR2_TOG

PLL_CTRL0_SET

PLL_CTRL27_CLR

PLL_CTRL27_TOG

PLL_CTRL0_CLR

PLL_CTRL0_TOG

CCGR61

CCGR61_SET

CCGR61_CLR

CCGR61_TOG

CCGR62

CCGR62_SET

CCGR62_CLR

CCGR62_TOG

PLL_CTRL28

PLL_CTRL28_SET

PLL_CTRL28_CLR

PLL_CTRL28_TOG

CCGR63

CCGR63_SET

CCGR63_CLR

CCGR63_TOG

CCGR64

CCGR64_SET

CCGR64_CLR

CCGR64_TOG

PLL_CTRL29

PLL_CTRL29_SET

PLL_CTRL29_CLR

CCGR65

CCGR65_SET

CCGR65_CLR

CCGR65_TOG

PLL_CTRL29_TOG

CCGR66

CCGR66_SET

CCGR66_CLR

CCGR66_TOG

CCGR67

CCGR67_SET

CCGR67_CLR

PLL_CTRL30

CCGR67_TOG

PLL_CTRL30_SET

PLL_CTRL30_CLR

PLL_CTRL30_TOG

CCGR68

CCGR68_SET

CCGR68_CLR

CCGR68_TOG

CCGR69

CCGR69_SET

CCGR69_CLR

CCGR69_TOG

PLL_CTRL31

PLL_CTRL31_SET

PLL_CTRL31_CLR

PLL_CTRL31_TOG

CCGR70

CCGR70_SET

CCGR70_CLR

CCGR70_TOG

CCGR71

CCGR71_SET

CCGR71_CLR

CCGR71_TOG

PLL_CTRL32

PLL_CTRL32_SET

PLL_CTRL32_CLR

CCGR72