DDRC_REGS

ddr3 : Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3.
bits : 0 - 0 (1 bit)
access : read-write

lpddr2 : Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to support LPDDR2.
bits : 2 - 2 (1 bit)
access : read-write

lpddr3 : Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to support LPDDR3.
bits : 3 - 3 (1 bit)
access : read-write

ddr4 : Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support DDR4.
bits : 4 - 4 (1 bit)
access : read-write

lpddr4 : Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to support LPDDR4.
bits : 5 - 5 (1 bit)
access : read-write

burstchop : When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (DDRC_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. Burst Chop for Writes is exercised only if Partial Writes enabled (DDRC_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0'. BC4 (fixed) mode is not supported.
bits : 9 - 9 (1 bit)
access : read-write

en_2t_timing_mode : If 1, then DDRC uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T timing is not supported in DDR4 geardown mode. Note: 2T timing is not supported in Shared-AC dual channel mode and the register value is don't care.
bits : 10 - 10 (1 bit)
access : read-write

geardown_mode : 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed, only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: Geardown mode is not supported if the configuration parameter DDRC_SHARED_AC is set (in Shared-AC mode) and the register value is don't care
bits : 11 - 11 (1 bit)
access : read-write

data_bus_width : Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus width is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width).
bits : 12 - 13 (2 bit)
access : read-write

dll_off_mode : Set to 1 when the DDRC and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put DDRC and DRAM in DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and this bit must be set to '0'.
bits : 15 - 15 (1 bit)
access : read-write

burst_rdwr : SDRAM burst length used
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x1 : burst_rdwr_1

Burst length of 2 (only supported for mDDR)

0x2 : burst_rdwr_2

Burst length of 4

0x4 : burst_rdwr_4

Burst length of 8

0x8 : burst_rdwr_8

Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4)

End of enumeration elements list.

frequency_ratio : Selects the Frequency Ratio
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : frequency_ratio_0

1:2 Mode

0x1 : frequency_ratio_1

1:1 Mode

End of enumeration elements list.

active_ranks : Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are present.
bits : 24 - 25 (2 bit)
access : read-write

frequency_mode : Choose which registers are used.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : frequency_mode_0

Original Registers

0x1 : frequency_mode_1

Shadow Registers

End of enumeration elements list.

device_config : Indicates the configuration of the device used in the system.
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

0 : device_config_0

x4 device

0x1 : device_config_1

x8 device

0x2 : device_config_2

x16 device

0x3 : device_config_3

x32 device

End of enumeration elements list.

MRCTRL0

Mode Register Read/Write Control Register 0.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

mr_type : Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : mr_type_0

Write

0x1 : mr_type_1

Read

End of enumeration elements list.

mpr_en : Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4).
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : mpr_en_0

MRS

0x1 : mpr_en_1

WR/RD for MPR

End of enumeration elements list.

pda_en : Indicates whether the mode register operation is MRS in PDA mode or not.Note that when pba_mode=1, PBA access is initiated instead of PDA access.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : pda_en_0

MRS

0x1 : pda_en_1

MRS in Per DRAM Addressability

End of enumeration elements list.

sw_init_int : Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. For DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit can be used to program additional mode registers before automatic SDRAM initialization if necessary. In LPDDR4 independent channel mode, note that this must be programmed to both channels beforehand. Note that this must be cleared to 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : sw_init_int_0

Software intervention is not allowed

0x1 : sw_init_int_1

Software intervention is allowed

End of enumeration elements list.

mr_rank : Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. Examples (assume DDRC is configured for 4 ranks):0x1 - select rank 0 onlyselect rank 1 onlyselect ranks 0 and 2select ranks 1 and 3select ranks 0, 1, 2 and 3
bits : 4 - 5 (2 bit)
access : read-write

mr_addr : Address of the mode register that is to be written to.
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

0 : mr_addr_0

MR0

0x1 : mr_addr_1

MR1

0x2 : mr_addr_2

MR2

0x3 : mr_addr_3

MR3

0x4 : mr_addr_4

MR4

0x5 : mr_addr_5

MR5

0x6 : mr_addr_6

MR6

0x7 : mr_addr_7

MR7

End of enumeration elements list.

pba_mode : Indicates whether PBA access is executed. When setting this bit to 1 along with setting pda_en to 1, DDRC initiates PBA access instead of PDA access. - 0 - Per DRAM Addressability mode - 1 - Per Buffer Addressability mode The completion of PBA access is confirmed by MRSTAT.pda_done in the same way as PDA.
bits : 30 - 30 (1 bit)
access : read-write

mr_wr : Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRC automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.
bits : 31 - 31 (1 bit)
access : read-write

DRAMTMG0

SDRAM Timing Register 0
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

t_ras_min : tRAS(min): Minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks
bits : 0 - 5 (6 bit)
access : read-write

t_ras_max : tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:2 frequency ratio mode, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of 1024 clocks.
bits : 8 - 14 (7 bit)
access : read-write

t_faw : tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next integer value. In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency mode. Unit: Clocks
bits : 16 - 21 (6 bit)
access : read-write

wr2pre : Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR = Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this parameter. When the controller is operating in 1:2 frequency ratio mode, 1T mode, divide the above value by 2. No rounding up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. Note that, depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency through the LRDIMM.
bits : 24 - 30 (7 bit)
access : read-write

DRAMTMG1

SDRAM Timing Register 1
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

t_rc : tRC: Minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode, program this to (tRC/2) and round up to next integer value. Unit: Clocks.
bits : 0 - 6 (7 bit)
access : read-write

rd2pre : tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP (*). - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 (*) When both DDR4 SDRAM and ST-MRAM are used simultaneously, use SDRAM's tRP value for calculation. When the controller is operating in 1:2 mode, 1T mode, divide the above value by 2. No rounding up. When the controller is operating in 1:2 mode, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. Unit: Clocks.
bits : 8 - 13 (6 bit)
access : read-write

t_xp : tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. When the controller is operating in 1:2 frequency ratio mode, program this to (tXP/2) and round it up to the next integer value. Units: Clocks
bits : 16 - 20 (5 bit)
access : read-write

DRAMTMG2

SDRAM Timing Register 2
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

wr2rd : DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same bank group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to read command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read command delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. When the controller is operating in 1:2 mode, divide the value calculated using the above equation by 2, and round it up to next integer.
bits : 0 - 5 (6 bit)
access : read-write

rd2wr : DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. Please see the relevant PHY databook for details of what should be included here. Unit: Clocks. Where: - WL = write latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. Note that, depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency through the LRDIMM.
bits : 8 - 13 (6 bit)
access : read-write

read_latency : Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust the value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
bits : 16 - 21 (6 bit)
access : read-write

write_latency : Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be set to 1. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust the value of WL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
bits : 24 - 29 (6 bit)
access : read-write

DRAMTMG3

SDRAM Timing Register 3
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

t_mod : tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency applied to mode register writes by the RDIMM/LRDIMM chip. Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller is operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if controller is operating in 1:2 frequency ratio mode.
bits : 0 - 9 (10 bit)
access : read-write

t_mrd : tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command. When the controller is operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead.
bits : 12 - 17 (6 bit)
access : read-write

t_mrw : Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. When the controller is operating in 1:2 frequency ratio mode, program this to the above values divided by 2 and round it up to the next integer value. For LDPDR3, this register is used for the time from a MRW/MRR to a MRW/MRR.
bits : 20 - 29 (10 bit)
access : read-write

DRAMTMG4

SDRAM Timing Register 4
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

t_rp : tRP: Minimum time from precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode, t_rp should be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. When the controller is operating in 1:2 frequency ratio mode in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
bits : 0 - 4 (5 bit)
access : read-write

t_rrd : DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. Others: tRRD: Minimum time between activates from bank "a" to bank "b" When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Unit: Clocks.
bits : 8 - 11 (4 bit)
access : read-write

t_ccd : DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. Unit: clocks.
bits : 16 - 19 (4 bit)
access : read-write

t_rcd : tRCD - tAL: Minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which implies minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio mode. Unit: Clocks.
bits : 24 - 28 (5 bit)
access : read-write

DRAMTMG5

SDRAM Timing Register 5
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

t_cke : Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. When the controller is operating in 1:2 frequency ratio mode, program this to (value described above)/2 and round it up to the next integer value. Unit: Clocks.
bits : 0 - 4 (5 bit)
access : read-write

t_ckesr : Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 (+ PL(parity latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer.
bits : 8 - 13 (6 bit)
access : read-write

t_cksre : This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) (+ PL(parity latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer.
bits : 16 - 19 (4 bit)
access : read-write

t_cksrx : This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer.
bits : 24 - 27 (4 bit)
access : read-write

DRAMTMG6

SDRAM Timing Register 6
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

t_ckcsx : This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
bits : 0 - 3 (4 bit)
access : read-write

t_ckdpdx : This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2 devices.
bits : 16 - 19 (4 bit)
access : read-write

t_ckdpde : This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices.
bits : 24 - 27 (4 bit)
access : read-write

DRAMTMG7

SDRAM Timing Register 7
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

t_ckpdx : This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 When using DDR2/3/4 SDRAM, this register should be set to the same value as DRAMTMG5.t_cksrx. When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
bits : 0 - 3 (4 bit)
access : read-write

t_ckpde : This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL When using DDR2/3/4 SDRAM, this register should be set to the same value as DRAMTMG5.t_cksre. When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
bits : 8 - 11 (4 bit)
access : read-write

DRAMTMG8

SDRAM Timing Register 8
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

t_xs_x32 : tXS: Exit Self Refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and DDR4 SDRAMs.
bits : 0 - 6 (7 bit)
access : read-write

t_xs_dll_x32 : tXSDLL: Exit Self Refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and DDR4 SDRAMs.
bits : 8 - 14 (7 bit)
access : read-write

t_xs_abort_x32 : tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Ensure this is less than or equal to t_xs_x32.
bits : 16 - 22 (7 bit)
access : read-write

t_xs_fast_x32 : tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32.
bits : 24 - 30 (7 bit)
access : read-write

DRAMTMG9

SDRAM Timing Register 9
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

wr2rd_s : CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. This comes directly from the SDRAM specification. When the controller is operating in 1:2 mode, divide the value calculated using the above equation by 2, and round it up to next integer.
bits : 0 - 5 (6 bit)
access : read-write

t_rrd_s : tRRD_S: Minimum time between activates from bank "a" to bank "b" for different bank group. When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks.
bits : 8 - 11 (4 bit)
access : read-write

t_ccd_s : tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank "a" to bank "b"), the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks.
bits : 16 - 18 (3 bit)
access : read-write

ddr4_wr_preamble : DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2
bits : 30 - 30 (1 bit)
access : read-write

DRAMTMG10

SDRAM Timing Register 10
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

t_gear_hold : Geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode, program this to (tGEAR_hold/2) and round it up to the next integer value. Unit: Clocks
bits : 0 - 1 (2 bit)
access : read-write

t_gear_setup : Geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode, program this to (tGEAR_setup/2) and round it up to the next integer value. Unit: Clocks
bits : 2 - 3 (2 bit)
access : read-write

t_cmd_gear : Sync pulse to first valid command. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in 1:2 mode, program this to (tCMD_GEAR/2) and round it up to the next integer value. Unit: Clocks
bits : 8 - 12 (5 bit)
access : read-write

t_sync_gear : Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24+4 = 28 When the controller is operating in 1:2 mode, program this to (tSYNC_GEAR/2) and round it up to the next integer value. Unit: Clocks
bits : 16 - 20 (5 bit)
access : read-write

DRAMTMG11

SDRAM Timing Register 11
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

t_ckmpe : tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer.
bits : 0 - 4 (5 bit)
access : read-write

t_mpx_s : tMPX_S: Minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode, program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks.
bits : 8 - 9 (2 bit)
access : read-write

t_mpx_lh : tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode, program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks.
bits : 16 - 20 (5 bit)
access : read-write

post_mpsm_gap_x32 : tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode, program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Multiples of 32 clocks.
bits : 24 - 30 (7 bit)
access : read-write

DRAMTMG12

SDRAM Timing Register 12
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

t_mrd_pda : tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode, program this to (tMRD_PDA/2) and round it up to the next integer value.
bits : 0 - 4 (5 bit)
access : read-write

t_ckehcmd : tCKEHCMD: Valid command requirement after CKE input HIGH. When the controller is operating in 1:2 frequency ratio mode, program this to (tCKEHCMD/2) and round it up to the next integer value.
bits : 8 - 11 (4 bit)
access : read-write

t_cmdcke : tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode, program this to (max(tESCKE, tCMDCKE)/2) and round it up to the next integer value.
bits : 16 - 17 (2 bit)
access : read-write

DRAMTMG13

SDRAM Timing Register 13
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

t_ppd : LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode, program this to (tPPD/2) and round it up to the next integer value. Unit: Clocks.
bits : 0 - 2 (3 bit)
access : read-write

t_ccd_mw : LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode, program this to (tCCDMW/2) and round it up to the next integer value. Unit: Clocks.
bits : 16 - 21 (6 bit)
access : read-write

odtloff : LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference. When the controller is operating in 1:2 frequency ratio mode, program this to (tODTLoff/2) and round it up to the next integer value. Unit: Clocks.
bits : 24 - 30 (7 bit)
access : read-write

DRAMTMG14

SDRAM Timing Register 14
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

t_xsr : tXSR: Exit Self Refresh to any command. When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value. Note: Used only for mDDR/LPDDR2/LPDDR3/LPDDR4 mode.
bits : 0 - 11 (12 bit)
access : read-write

DRAMTMG15

SDRAM Timing Register 15
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

t_stab_x32 : tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM : - when exiting power saving mode, if the clock was stopped, after re-enabling it the clock must be stable for a time specified by tSTAB - in the case of input clock frequency change (DDR4) - after issuing control words that refers to clock timing (Specification: 6us for DDR3, 5us for DDR4) When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. Unit: Multiples of 32 clock cycles.
bits : 0 - 7 (8 bit)
access : read-write

en_dfi_lp_t_stab : Enable DFI tSTAB
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : en_dfi_lp_t_stab_0

Disable using tSTAB when exiting DFI LP

0x1 : en_dfi_lp_t_stab_1

Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power.

End of enumeration elements list.

MRCTRL1

Mode Register Read/Write Control Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

mr_data : Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. For LPDDR2/LPDDR3/LPDDR4, MRCTRL1[15:0] are interpreted as [15:8] MR Address [7:0] MR data for writes, don't care for reads. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations.
bits : 0 - 17 (18 bit)
access : read-write

MRSTAT

Mode Register Read/Write Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

mr_wr_busy : The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRC accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when 'MRSTAT.mr_wr_busy' is high.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : mr_wr_busy_0

Indicates that the SoC core can initiate a mode register write operation

0x1 : mr_wr_busy_1

Indicates that mode register write operation is in progress

End of enumeration elements list.

pda_done : The SoC core may initiate a MR write operation in PDA/PBA mode only if this signal is low. This signal goes high when three consecutive MRS commands related to the PDA/PBA mode are issued to the SDRAM. This signal goes low when MRCTRL0.pda_en becomes 0. Therefore, it is recommended to write MRCTRL0.pda_en to 0 after this signal goes high in order to prepare to perform PDA operation next time
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

0 : pda_done_0

Indicates that mode register write operation related to PDA/PBA is in progress or has not started yet.

0x1 : pda_done_1

Indicates that mode register write operation related to PDA/PBA has competed.

End of enumeration elements list.

ZQCTL0

ZQ Control Register 0
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

t_zq_short_nop : tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
bits : 0 - 9 (10 bit)
access : read-write

t_zq_long_nop : tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode: DDR3/DDR4: program this to tZQoper/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer value. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
bits : 16 - 26 (11 bit)
access : read-write

dis_mpsmx_zqcl : Do not issue ZQCL command at Maximum Power Save Mode exit if the DDRC_SHARED_AC configuration parameter is set. Program it to 1'b1. The software can send ZQCS after exiting MPSM mode.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : dis_mpsmx_zqcl_0

Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for designs supporting DDR4 devices.

0x1 : dis_mpsmx_zqcl_1

Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode.

End of enumeration elements list.

zq_resistor_shared : ZQ resistor sharing
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : zq_resistor_shared_0

ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.

0x1 : zq_resistor_shared_1

Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap.

End of enumeration elements list.

dis_srx_zqcl : Disable ZQCL/MPC
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : dis_srx_zqcl_0

Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.

0x1 : dis_srx_zqcl_1

Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode.

End of enumeration elements list.

dis_auto_zq : Disable Auto ZQCS/MPC
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : dis_auto_zq_0

Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024.

0x1 : dis_auto_zq_1

Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module.

End of enumeration elements list.

ZQCTL1

ZQ Control Register 1
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

t_zq_short_interval_x1024 : Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 DFI clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
bits : 0 - 19 (20 bit)
access : read-write

t_zq_reset_nop : tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode, program this to tZQReset/2 and round it up to the next integer value. This is only present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
bits : 20 - 29 (10 bit)
access : read-write

ZQCTL2

ZQ Control Register 2
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

zq_reset : Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRC automatically clears this bit. It is recommended NOT to set this signal if in Init, Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. This is only present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
bits : 0 - 0 (1 bit)
access : read-write

ZQSTAT

ZQ Status Register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

zq_reset_busy : SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRC accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : zq_reset_busy_0

Indicates that the SoC core can initiate a ZQ Reset operation

0x1 : zq_reset_busy_1

Indicates that ZQ Reset operation is in progress

End of enumeration elements list.

DFITMG0

DFI Timing Register 0
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dfi_tphy_wrlat : Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to use the adjusted value of CL in the calculation of tphy_wrlat. This is to compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY clock cycles, depending on DFITMG0.dfi_wrdata_use_sdr.
bits : 0 - 5 (6 bit)
access : read-write

dfi_tphy_wrdata : Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. Unit: DFI clock cycles or DFI PHY clock cycles, depending on DFITMG0.dfi_wrdata_use_sdr.
bits : 8 - 13 (6 bit)
access : read-write

dfi_wrdata_use_sdr : Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles - 0 in terms of HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct value.
bits : 15 - 15 (1 bit)
access : read-write

dfi_t_rddata_en : Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to use the adjusted value of CL in the calculation of trddata_en. This is to compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY clock cycles, depending on DFITMG0.dfi_rddata_use_sdr.
bits : 16 - 22 (7 bit)
access : read-write

dfi_rddata_use_sdr : Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles: - 0 in terms of HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct value.
bits : 23 - 23 (1 bit)
access : read-write

dfi_t_ctrl_delay : Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM's/LRDIMM's extra cycle of latency in terms of DFI clock.
bits : 24 - 28 (5 bit)
access : read-write

DFITMG1

DFI Timing Register 1
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dfi_t_dram_clk_enable : Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.
bits : 0 - 4 (5 bit)
access : read-write

dfi_t_dram_clk_disable : Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.
bits : 8 - 12 (5 bit)
access : read-write

dfi_t_wrdata_delay : Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks
bits : 16 - 20 (5 bit)
access : read-write

dfi_t_parin_lat : Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven.
bits : 24 - 25 (2 bit)
access : read-write

dfi_t_cmd_lat : Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
bits : 28 - 31 (4 bit)
access : read-write

DFILPCFG0

DFI Low Power Configuration Register 0
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dfi_lp_en_pd : Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled
bits : 0 - 0 (1 bit)
access : read-write

dfi_lp_wakeup_pd : Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time:
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0 : dfi_lp_wakeup_pd_0

16 cycles

0x1 : dfi_lp_wakeup_pd_1

32 cycles

0x2 : dfi_lp_wakeup_pd_2

64 cycles

0x3 : dfi_lp_wakeup_pd_3

128 cycles

0x4 : dfi_lp_wakeup_pd_4

256 cycles

0x5 : dfi_lp_wakeup_pd_5

512 cycles

0x6 : dfi_lp_wakeup_pd_6

1024 cycles

0x7 : dfi_lp_wakeup_pd_7

2048 cycles

0x8 : dfi_lp_wakeup_pd_8

4096 cycles

0x9 : dfi_lp_wakeup_pd_9

8192 cycles

0xA : dfi_lp_wakeup_pd_10

16384 cycles

0xB : dfi_lp_wakeup_pd_11

32768 cycles

0xC : dfi_lp_wakeup_pd_12

65536 cycles

0xD : dfi_lp_wakeup_pd_13

131072 cycles

0xE : dfi_lp_wakeup_pd_14

262144 cycles

0xF : dfi_lp_wakeup_pd_15

Unlimited cycles

End of enumeration elements list.

dfi_lp_en_sr : Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : dfi_lp_en_sr_0

Disabled

0x1 : dfi_lp_en_sr_1

Enabled

End of enumeration elements list.

dfi_lp_wakeup_sr : Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time:
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

0 : dfi_lp_wakeup_sr_0

16 cycles

0x1 : dfi_lp_wakeup_sr_1

32 cycles

0x2 : dfi_lp_wakeup_sr_2

64 cycles

0x3 : dfi_lp_wakeup_sr_3

128 cycles

0x4 : dfi_lp_wakeup_sr_4

256 cycles

0x5 : dfi_lp_wakeup_sr_5

512 cycles

0x6 : dfi_lp_wakeup_sr_6

1024 cycles

0x7 : dfi_lp_wakeup_sr_7

2048 cycles

0x8 : dfi_lp_wakeup_sr_8

4096 cycles

0x9 : dfi_lp_wakeup_sr_9

8192 cycles

0xA : dfi_lp_wakeup_sr_10

16384 cycles

0xB : dfi_lp_wakeup_sr_11

32768 cycles

0xC : dfi_lp_wakeup_sr_12

65536 cycles

0xD : dfi_lp_wakeup_sr_13

131072 cycles

0xE : dfi_lp_wakeup_sr_14

262144 cycles

0xF : dfi_lp_wakeup_sr_15

Unlimited cycles

End of enumeration elements list.

dfi_lp_en_dpd : Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices.
bits : 16 - 16 (1 bit)
access : read-write

dfi_lp_wakeup_dpd : Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices.
bits : 20 - 23 (4 bit)
access : read-write

Enumeration:

0 : dfi_lp_wakeup_dpd_0

16 cycles

0x1 : dfi_lp_wakeup_dpd_1

32 cycles

0x2 : dfi_lp_wakeup_dpd_2

64 cycles

0x3 : dfi_lp_wakeup_dpd_3

128 cycles

0x4 : dfi_lp_wakeup_dpd_4

256 cycles

0x5 : dfi_lp_wakeup_dpd_5

512 cycles

0x6 : dfi_lp_wakeup_dpd_6

1024 cycles

0x7 : dfi_lp_wakeup_dpd_7

2048 cycles

0x8 : dfi_lp_wakeup_dpd_8

4096 cycles

0x9 : dfi_lp_wakeup_dpd_9

8192 cycles

0xA : dfi_lp_wakeup_dpd_10

16384 cycles

0xB : dfi_lp_wakeup_dpd_11

32768 cycles

0xC : dfi_lp_wakeup_dpd_12

65536 cycles

0xD : dfi_lp_wakeup_dpd_13

131072 cycles

0xE : dfi_lp_wakeup_dpd_14

262144 cycles

0xF : dfi_lp_wakeup_dpd_15

Unlimited cycles

End of enumeration elements list.

dfi_tlp_resp : Setting in DFI clock cycles for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always.
bits : 24 - 28 (5 bit)
access : read-write

DFILPCFG1

DFI Low Power Configuration Register 1
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dfi_lp_en_mpsm : Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting DDR4 devices.
bits : 0 - 0 (1 bit)
access : read-write

dfi_lp_wakeup_mpsm : Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time:
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0 : dfi_lp_wakeup_mpsm_0

16 cycles

0x1 : dfi_lp_wakeup_mpsm_1

32 cycles

0x2 : dfi_lp_wakeup_mpsm_2

64 cycles

0x3 : dfi_lp_wakeup_mpsm_3

128 cycles

0x4 : dfi_lp_wakeup_mpsm_4

256 cycles

0x5 : dfi_lp_wakeup_mpsm_5

512 cycles

0x6 : dfi_lp_wakeup_mpsm_6

1024 cycles

0x7 : dfi_lp_wakeup_mpsm_7

2048 cycles

0x8 : dfi_lp_wakeup_mpsm_8

4096 cycles

0x9 : dfi_lp_wakeup_mpsm_9

8192 cycles

0xA : dfi_lp_wakeup_mpsm_10

16384 cycles

0xB : dfi_lp_wakeup_mpsm_11

32768 cycles

0xC : dfi_lp_wakeup_mpsm_12

65536 cycles

0xD : dfi_lp_wakeup_mpsm_13

131072 cycles

0xE : dfi_lp_wakeup_mpsm_14

262144 cycles

0xF : dfi_lp_wakeup_mpsm_15

Unlimited cycles

End of enumeration elements list.

DFIUPD0

DFI Update Register 0
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dfi_t_ctrlup_min : Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRC expects the PHY to respond within this time. If the PHY does not respond, the DDRC will de-assert dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3.
bits : 0 - 9 (10 bit)
access : read-write

dfi_t_ctrlup_max : Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40.
bits : 16 - 25 (10 bit)
access : read-write

ctrlupd_pre_srx : Selects dfi_ctrlupd_req requirements at SRX: - 0 : send ctrlupd after SRX - 1 : send ctrlupd before SRX If DFIUPD0.dis_auto_ctrlupd_srx=1, this register has no impact, because no dfi_ctrlupd_req will be issued when SRX.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : ctrlupd_pre_srx_0

send ctrlupd after SRX

0x1 : ctrlupd_pre_srx_1

send ctrlupd before SRX

End of enumeration elements list.

dis_auto_ctrlupd_srx : Auto ctrlupd request generation
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : dis_auto_ctrlupd_srx_0

DDRC issues a dfi_ctrlupd_req before or after exiting self-refresh, depending on DFIUPD0.ctrlupd_pre_srx.

0x1 : dis_auto_ctrlupd_srx_1

disable the automatic dfi_ctrlupd_req generation by the DDRC at self-refresh exit.

End of enumeration elements list.

dis_auto_ctrlupd : automatic dfi_ctrlupd_req generation by the DDRC
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : dis_auto_ctrlupd_0

DDRC issues dfi_ctrlupd_req periodically.

0x1 : dis_auto_ctrlupd_1

disable the automatic dfi_ctrlupd_req generation by the DDRC. The core must issue the dfi_ctrlupd_req signal using register reg_ddrc_ctrlupd.

End of enumeration elements list.

DFIUPD1

DFI Update Register 1
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dfi_t_ctrlupd_interval_max_x1024 : This is the maximum amount of time between DDRC initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 DFI clock cycles
bits : 0 - 7 (8 bit)
access : read-write

dfi_t_ctrlupd_interval_min_x1024 : This is the minimum amount of time between DDRC initiated DFI update requests (which is executed whenever the DDRC is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRC is idle. Minimum allowed value for this field is 1. Unit: 1024 DFI clock cycles
bits : 16 - 23 (8 bit)
access : read-write

DFIUPD2

DFI Update Register 2
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dfi_phyupd_en : Enables the support for acknowledging PHY-initiated updates:
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : dfi_phyupd_en_0

Disabled

0x1 : dfi_phyupd_en_1

Enabled

End of enumeration elements list.

DFIMISC

DFI Miscellaneous Control Register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dfi_init_complete_en : PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisation
bits : 0 - 0 (1 bit)
access : read-write

phy_dbi_mode : DBI implemented in DDRC or PHY. Present only in designs configured to support DDR4 and LPDDR4.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : phy_dbi_mode_0

DDRC implements DBI functionality.

0x1 : phy_dbi_mode_1

PHY implements DBI functionality.

End of enumeration elements list.

dfi_data_cs_polarity : Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : dfi_data_cs_polarity_0

Signals are active low

0x1 : dfi_data_cs_polarity_1

Signals are active high

End of enumeration elements list.

ctl_idle_en : Enables support of ctl_idle signal, which is non-DFI related pin specific to certain PHYs. See signal description of ctl_idle signal for further details of ctl_idle functionality.
bits : 4 - 4 (1 bit)
access : read-write

dfi_init_start : PHY init start request signal.When asserted it triggers the PHY init start request
bits : 5 - 5 (1 bit)
access : read-write

dfi_frequency : Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY.
bits : 8 - 12 (5 bit)
access : read-write

DFITMG2

DFI Timing Register 2
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dfi_tphy_wrcslat : Number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.
bits : 0 - 5 (6 bit)
access : read-write

dfi_tphy_rdcslat : Number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.
bits : 8 - 14 (7 bit)
access : read-write

DFITMG3

DFI Timing Register 3
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dfi_t_geardown_delay : The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode, program this to (tgeardown_delay/2) and round it up to the next integer value. Unit: Clocks
bits : 0 - 4 (5 bit)
access : read-write

DFISTAT

DFI Status Register
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

dfi_init_complete : The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done.
bits : 0 - 0 (1 bit)
access : read-only

dfi_lp_ack : Stores the value of the dfi_lp_ack input to the controller.
bits : 1 - 1 (1 bit)
access : read-only

MRCTRL2

Mode Register Read/Write Control Register 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

mr_device_sel : Indicates the device(s) to be selected during the MRS that happens in PDA mode. Each bit is associated with one device. For example, bit[0] corresponds to Device 0, bit[1] to Device 1 etc. A '1' should be programmed to indicate that the MRS command should be applied to that device. A '0' indicates that the MRS commands should be skipped for that device.
bits : 0 - 31 (32 bit)
access : read-write

DBICTL

DM/DBI Control Register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dm_en : DM enable signal in DDRC. This signal must be set the same logical value as DRAM's mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR4: Set this to inverted value of MR13[5] which is opposite polarity from this signal
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : dm_en_0

DM is disabled

0x1 : dm_en_1

DM is enabled

End of enumeration elements list.

wr_dbi_en : This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : wr_dbi_en_0

Write DBI is disabled

0x1 : wr_dbi_en_1

Write DBI is enabled.

End of enumeration elements list.

rd_dbi_en : Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]
bits : 2 - 2 (1 bit)
access : read-write

DERATEEN

Temperature Derate Enable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

derate_enable : Enables derating. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : derate_enable_0

Timing parameter derating is disabled

0x1 : derate_enable_1

Timing parameter derating is enabled using MR4 read value.

End of enumeration elements list.

derate_value : Derate value. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this register field should be set to 1; otherwise it should be set to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : derate_value_0

Derating uses +1

0x1 : derate_value_1

Derating uses +2

End of enumeration elements list.

derate_byte : Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.
bits : 4 - 7 (4 bit)
access : read-write

rc_derate_value : Derate value of tRC for LPDDR4. Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : rc_derate_value_0

Derating uses +1

0x1 : rc_derate_value_1

Derating uses +2

0x2 : rc_derate_value_2

Derating uses +3

0x3 : rc_derate_value_3

Derating uses +4

End of enumeration elements list.

ADDRMAP0

Address Map Register 0
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

addrmap_cs_bit0 : Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 28, and 31 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0.
bits : 0 - 4 (5 bit)
access : read-write

DERATEEN_SHADOW

[SHADOW] Temperature Derate Enable Register
address_offset : 0x2020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

derate_enable : Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
bits : 0 - 0 (1 bit)
access : read-write

derate_value : Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this register field should be set to 1; otherwise it should be set to 0.
bits : 1 - 1 (1 bit)
access : read-write

rc_derate_value : Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer.
bits : 8 - 9 (2 bit)
access : read-write

DERATEINT_SHADOW

[SHADOW] Temperature Derate Interval Register
address_offset : 0x2024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

mr4_read_interval : Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycle.
bits : 0 - 31 (32 bit)
access : read-write

ADDRMAP1

Address Map Register 1
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

addrmap_bank_b0 : Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 31 Internal Base: 2 The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field.
bits : 0 - 4 (5 bit)
access : read-write

addrmap_bank_b1 : Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 31 Internal Base: 3 The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field.
bits : 8 - 12 (5 bit)
access : read-write

addrmap_bank_b2 : Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 30 and 31 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0.
bits : 16 - 20 (5 bit)
access : read-write

RFSHCTL0_SHADOW

[SHADOW] Refresh Control Register 0
address_offset : 0x2050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

per_bank_refresh : - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
bits : 2 - 2 (1 bit)
access : read-write

refresh_burst : The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to section 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiated update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY-initiated update is complete.
bits : 4 - 8 (5 bit)
access : read-write

refresh_to_x32 : If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRC. FOR PERFORMANCE ONLY. Unit: Multiples of 32 DFI clocks.
bits : 12 - 16 (5 bit)
access : read-write

refresh_margin : Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 DFI clocks.
bits : 20 - 23 (4 bit)
access : read-write

RFSHTMG_SHADOW

[SHADOW] Refresh Timing Register
address_offset : 0x2064 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

t_rfc_min : tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode, t_rfc_min should be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if using per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the appropriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks.
bits : 0 - 9 (10 bit)
access : read-write

lpddr3_trefbw_en : Used only when LPDDR3 memory type is connected. Should only be changed when DDRC is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 - tREFBW parameter used
bits : 15 - 15 (1 bit)
access : read-write

t_rfc_nom_x32 : tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should be set to tREFIpb When the controller is operating in 1:2 frequency ratio mode, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI value is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater than 0x1. - Non-DDR4 or DDR4 Fixed 1x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0xFFE. - DDR4 Fixed 2x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x7FF. - DDR4 Fixed 4x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x3FF. Unit: Multiples of 32 clocks.
bits : 16 - 27 (12 bit)
access : read-write

ADDRMAP2

Address Map Register 2
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

addrmap_col_b2 : - Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF address bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this field. Note, if DDRC_INCL_ARB=1 and MEMC_BURST_LENGTH=8, it is required to program this to 0 unless: - in Half or Quarter bus width (MSTR.data_bus_width!=00) and - PCCFG.bl_exp_mode==1 and either - In DDR4 and ADDRMAP8.addrmap_bg_b0==0 or - In LPDDR4 and ADDRMAP1.addrmap_bank_b0==0 If DDRC_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0 unless: - in Half or Quarter bus width (MSTR.data_bus_width!=00) and - PCCFG.bl_exp_mode==1 and - In DDR4 and ADDRMAP8.addrmap_bg_b0==0 Otherwise, if MEMC_BURST_LENGTH=8 and Full Bus Width (MSTR.data_bus_width==00), it is recommended to program this to 0 so that HIF[2] maps to column address bit 2. If MEMC_BURST_LENGTH=16 and Full Bus Width (MSTR.data_bus_width==00), it is recommended to program this to 0 so that HIF[2] maps to column address bit 2. If MEMC_BURST_LENGTH=16 and Half Bus Width (MSTR.data_bus_width==01), it is recommended to program this to 0 so that HIF[2] maps to column address bit 3.
bits : 0 - 3 (4 bit)
access : read-write

addrmap_col_b3 : - Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF address bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this field. Note, if DDRC_INCL_ARB=1, MEMC_BURST_LENGTH=16, Full bus width (MSTR.data_bus_width=00) and BL16 (MSTR.burst_rdwr=1000), it is recommended to program this to 0.
bits : 8 - 11 (4 bit)
access : read-write

addrmap_col_b4 : - Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF address bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0.
bits : 16 - 19 (4 bit)
access : read-write

addrmap_col_b5 : - Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF address bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0.
bits : 24 - 27 (4 bit)
access : read-write

ADDRMAP3

Address Map Register 3
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

addrmap_col_b6 : - Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF address bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0.
bits : 0 - 3 (4 bit)
access : read-write

addrmap_col_b7 : - Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF address bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0.
bits : 8 - 11 (4 bit)
access : read-write

addrmap_col_b8 : - Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF address bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.
bits : 16 - 19 (4 bit)
access : read-write

addrmap_col_b9 : - Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.
bits : 24 - 27 (4 bit)
access : read-write

INIT3_SHADOW

[SHADOW] SDRAM Initialization Register 3
address_offset : 0x20DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

emr : DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRC sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by the DDRC during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR2 register
bits : 0 - 15 (16 bit)
access : read-write

mr : DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRC sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 register
bits : 16 - 31 (16 bit)
access : read-write

INIT4_SHADOW

[SHADOW] SDRAM Initialization Register 4
address_offset : 0x20E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

emr3 : DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 register
bits : 0 - 15 (16 bit)
access : read-write

emr2 : DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unused
bits : 16 - 31 (16 bit)
access : read-write

INIT6_SHADOW

[SHADOW] SDRAM Initialization Register 6
address_offset : 0x20E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

mr5 : DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.
bits : 0 - 15 (16 bit)
access : read-write

mr4 : DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.
bits : 16 - 31 (16 bit)
access : read-write

INIT7_SHADOW

[SHADOW] SDRAM Initialization Register 7
address_offset : 0x20EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

mr6 : DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.
bits : 16 - 31 (16 bit)
access : read-write

ADDRMAP4

Address Map Register 4
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

addrmap_col_b10 : - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.
bits : 0 - 3 (4 bit)
access : read-write

addrmap_col_b11 : - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.
bits : 8 - 11 (4 bit)
access : read-write

DRAMTMG0_SHADOW

[SHADOW] SDRAM Timing Register 0
address_offset : 0x2100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRAMTMG1_SHADOW

[SHADOW] SDRAM Timing Register 1
address_offset : 0x2104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRAMTMG2_SHADOW

[SHADOW] SDRAM Timing Register 2
address_offset : 0x2108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRAMTMG3_SHADOW

[SHADOW] SDRAM Timing Register 3
address_offset : 0x210C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRAMTMG4_SHADOW

[SHADOW] SDRAM Timing Register 4
address_offset : 0x2110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRAMTMG5_SHADOW

[SHADOW] SDRAM Timing Register 5
address_offset : 0x2114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRAMTMG6_SHADOW

[SHADOW] SDRAM Timing Register 6
address_offset : 0x2118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRAMTMG7_SHADOW

[SHADOW] SDRAM Timing Register 7
address_offset : 0x211C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRAMTMG8_SHADOW

[SHADOW] SDRAM Timing Register 8
address_offset : 0x2120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRAMTMG9_SHADOW

[SHADOW] SDRAM Timing Register 9
address_offset : 0x2124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ddr4_wr_preamble : DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2
bits : 30 - 30 (1 bit)
access : read-write

DRAMTMG10_SHADOW

[SHADOW] SDRAM Timing Register 10
address_offset : 0x2128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRAMTMG11_SHADOW

[SHADOW] SDRAM Timing Register 11
address_offset : 0x212C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRAMTMG12_SHADOW

[SHADOW] SDRAM Timing Register 12
address_offset : 0x2130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRAMTMG13_SHADOW

[SHADOW] SDRAM Timing Register 13
address_offset : 0x2134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRAMTMG14_SHADOW

[SHADOW] SDRAM Timing Register 14
address_offset : 0x2138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRAMTMG15_SHADOW

[SHADOW] SDRAM Timing Register 15
address_offset : 0x213C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

en_dfi_lp_t_stab : - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP
bits : 31 - 31 (1 bit)
access : read-write

ADDRMAP5

Address Map Register 5
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

addrmap_row_b0 : Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field.
bits : 0 - 3 (4 bit)
access : read-write

addrmap_row_b1 : Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field.
bits : 8 - 11 (4 bit)
access : read-write

addrmap_row_b2_10 : Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. When value 15 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.
bits : 16 - 19 (4 bit)
access : read-write

addrmap_row_b11 : Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0.
bits : 24 - 27 (4 bit)
access : read-write

ADDRMAP6

Address Map Register 6
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

addrmap_row_b12 : Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0.
bits : 0 - 3 (4 bit)
access : read-write

addrmap_row_b13 : Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0.
bits : 8 - 11 (4 bit)
access : read-write

addrmap_row_b14 : Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0.
bits : 16 - 19 (4 bit)
access : read-write

addrmap_row_b15 : Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0.
bits : 24 - 27 (4 bit)
access : read-write

lpddr3_6gb_12gb : Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present only in designs configured to support LPDDR3.
bits : 31 - 31 (1 bit)
access : read-write

ZQCTL0_SHADOW

[SHADOW] ZQ Control Register 0
address_offset : 0x2180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dis_mpsmx_zqcl : - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for designs supporting DDR4 devices. Note: Do not issue ZQCL command at Maximum Power Save Mode exit if the DDRC_SHARED_AC configuration parameter is set. Program it to 1'b1. The software can send ZQCS after exiting MPSM mode.
bits : 28 - 28 (1 bit)
access : read-write

zq_resistor_shared : - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
bits : 29 - 29 (1 bit)
access : read-write

dis_srx_zqcl : - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
bits : 30 - 30 (1 bit)
access : read-write

dis_auto_zq : - 1 - Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
bits : 31 - 31 (1 bit)
access : read-write

DFITMG0_SHADOW

[SHADOW] DFI Timing Register 0
address_offset : 0x2190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFITMG1_SHADOW

[SHADOW] DFI Timing Register 1
address_offset : 0x2194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFITMG2_SHADOW

[SHADOW] DFI Timing Register 2
address_offset : 0x21B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFITMG3_SHADOW

[SHADOW] DFI Timing Register 3
address_offset : 0x21B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDRMAP7

Address Map Register 7
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

addrmap_row_b16 : Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0.
bits : 0 - 3 (4 bit)
access : read-write

addrmap_row_b17 : Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0.
bits : 8 - 11 (4 bit)
access : read-write

ADDRMAP8

Address Map Register 8
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

addrmap_bg_b0 : Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 31 Internal Base: 2 The selected HIF address bit for each of the bank group address bits is determined by adding the internal base to the value of this field.
bits : 0 - 4 (5 bit)
access : read-write

addrmap_bg_b1 : Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 31, and 63 Internal Base: 3 The selected HIF address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If set to 63, bank group address bit 1 is set to 0.
bits : 8 - 13 (6 bit)
access : read-write

ADDRMAP9

Address Map Register 9
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

addrmap_row_b2 : Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
bits : 0 - 3 (4 bit)
access : read-write

addrmap_row_b3 : Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
bits : 8 - 11 (4 bit)
access : read-write

addrmap_row_b4 : Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
bits : 16 - 19 (4 bit)
access : read-write

addrmap_row_b5 : Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
bits : 24 - 27 (4 bit)
access : read-write

ODTCFG_SHADOW

[SHADOW] ODT Configuration Register
address_offset : 0x2240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

rd_odt_delay : The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRC. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), DDRC does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, DDRC does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)
bits : 2 - 6 (5 bit)
access : read-write

rd_odt_hold : DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK)
bits : 8 - 11 (4 bit)
access : read-write

wr_odt_delay : The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRC. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), DDRC does not support ODT for write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))
bits : 16 - 20 (5 bit)
access : read-write

wr_odt_hold : DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
bits : 24 - 27 (4 bit)
access : read-write

ADDRMAP10

Address Map Register 10
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

addrmap_row_b6 : Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
bits : 0 - 3 (4 bit)
access : read-write

addrmap_row_b7 : Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
bits : 8 - 11 (4 bit)
access : read-write

addrmap_row_b8 : Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
bits : 16 - 19 (4 bit)
access : read-write

addrmap_row_b9 : Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
bits : 24 - 27 (4 bit)
access : read-write

ADDRMAP11

Address Map Register 11
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

addrmap_row_b10 : Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
bits : 0 - 3 (4 bit)
access : read-write

DERATEINT

Temperature Derate Interval Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ODTCFG

ODT Configuration Register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ODTMAP

ODT/Rank Map Register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

rank0_wr_odt : Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each rank, set its bit to 1 to enable its ODT.
bits : 0 - 1 (2 bit)
access : read-write

rank0_rd_odt : Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each rank, set its bit to 1 to enable its ODT.
bits : 4 - 5 (2 bit)
access : read-write

rank1_wr_odt : Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks
bits : 8 - 9 (2 bit)
access : read-write

rank1_rd_odt : Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks
bits : 12 - 13 (2 bit)
access : read-write

SCHED

Scheduler Control Register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

force_low_pri_n : Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Priority Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write side, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY.
bits : 0 - 0 (1 bit)
access : read-write

prefer_write : If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.
bits : 1 - 1 (1 bit)
access : read-write

pageclose : If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a need to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open page policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose feature provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY.
bits : 2 - 2 (1 bit)
access : read-write

lpr_num_entries : Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one less than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests arising out of single bit error correction RMW operation.
bits : 8 - 12 (5 bit)
access : read-write

go2critical_hysteresis : UNUSED
bits : 16 - 23 (8 bit)
access : read-write

rdwr_idle_gap : When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this register. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. FOR PERFORMANCE ONLY
bits : 24 - 30 (7 bit)
access : read-write

SCHED1

Scheduler Control Register 1
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pageclose_timer : This field works in conjunction with SCHED.pageclose. It only has meaning if SCHED.pageclose==1. If SCHED.pageclose==1 and pageclose_timer==0, then an auto-precharge may be scheduled for last read or write command in the CAM with a bank and page hit. Note, sometimes an explicit precharge is scheduled instead of the auto-precharge. See SCHED.pageclose for details of when this may happen. If SCHED.pageclose==1 and pageclose_timer>0, then an auto-precharge is not scheduled for last read or write command in the CAM with a bank and page hit. Instead, a timer is started, with pageclose_timer as the initial value. There is a timer on a per bank basis. The timer decrements unless the next read or write in the CAM to a bank is a page hit. It gets reset to pageclose_timer value if the next read or write in the CAM to a bank is a page hit. Once the timer has reached zero, an explcit precharge will be attempted to be scheduled.
bits : 0 - 7 (8 bit)
access : read-write

PERFHPR1

High Priority Read CAM Register 1
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

hpr_max_starve : Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. FOR PERFORMANCE ONLY.
bits : 0 - 15 (16 bit)
access : read-write

hpr_xact_run_length : Number of transactions that are serviced once the HPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.
bits : 24 - 31 (8 bit)
access : read-write

PERFLPR1

Low Priority Read CAM Register 1
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

lpr_max_starve : Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. FOR PERFORMANCE ONLY.
bits : 0 - 15 (16 bit)
access : read-write

lpr_xact_run_length : Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.
bits : 24 - 31 (8 bit)
access : read-write

PERFWR1

Write CAM Register 1
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

w_max_starve : Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. FOR PERFORMANCE ONLY.
bits : 0 - 15 (16 bit)
access : read-write

w_xact_run_length : Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.
bits : 24 - 31 (8 bit)
access : read-write

PWRCTL

Low Power Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

selfref_en : If true then the DDRC puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation.
bits : 0 - 0 (1 bit)
access : read-write

powerdown_en : If true then the DDRC goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation.
bits : 1 - 1 (1 bit)
access : read-write

deeppowerdown_en : When this is 1, DDRC puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be reset to '0' to bring DDRC out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down exit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this register should not be set to 1. FOR PERFORMANCE ONLY.
bits : 2 - 2 (1 bit)
access : read-write

en_dfi_dram_clk_disable : Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. Assertion of dfi_dram_clk_disable is as follows:In DDR2/DDR3, can only be asserted in Self Refresh.In DDR4, can be asserted in following:in Self Refreshin Maximum Power Saving ModeIn mDDR/LPDDR2/LPDDR3, can be asserted in following:in Self Refreshin Power Downin Deep Power Downduring Normal operation (Clock Stop)In LPDDR4, can be asserted in following:in Self Refresh Power Down in Power Downduring Normal operation (Clock Stop)
bits : 3 - 3 (1 bit)
access : read-write

mpsm_en : When this is 1, the DDRC puts the SDRAM into maximum power saving mode when the transaction store is empty. This register must be reset to '0' to bring DDRC out of maximum power saving mode. Present only in designs configured to support DDR4. For non-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DDR PHY, if the PHY parameter DDRC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY.
bits : 4 - 4 (1 bit)
access : read-write

selfref_sw : A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : selfref_sw_0

Software Exit from Self Refresh

0x1 : selfref_sw_1

Software Entry to Self Refresh

End of enumeration elements list.

stay_in_selfref : Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state for LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 0 - Allow transition from Self refresh state
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : stay_in_selfref_0

no description available

0x1 : stay_in_selfref_1

no description available

End of enumeration elements list.

DBG0

Debug Register 0
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dis_wc : When 1, disable write combine. FOR DEBUG ONLY
bits : 0 - 0 (1 bit)
access : read-write

dis_rd_bypass : Only present in designs supporting read bypass. When 1, disable bypass path for high priority read page hits FOR DEBUG ONLY.
bits : 1 - 1 (1 bit)
access : read-write

dis_act_bypass : Only present in designs supporting activate bypass. When 1, disable bypass path for high priority read activates FOR DEBUG ONLY.
bits : 2 - 2 (1 bit)
access : read-write

dis_collision_page_opt : When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY.
bits : 4 - 4 (1 bit)
access : read-write

DBG1

Debug Register 1
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dis_dq : When 1, DDRC will not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. This bit may be used to prevent reads or writes being issued by the DDRC, which makes it safe to modify certain register fields associated with reads and writes (see User Guide for details). After setting this bit, it is strongly recommended to poll DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty, before making changes to any registers which affect reads and writes. This will ensure that the relevant logic in the DDRC is idle. This bit is intended to be switched on-the-fly.
bits : 0 - 0 (1 bit)
access : read-write

dis_hif : When 1, DDRC asserts the HIF command signal hif_cmd_stall. DDRC will ignore the hif_cmd_valid and all other associated request signals. This bit is intended to be switched on-the-fly.
bits : 1 - 1 (1 bit)
access : read-write

DBGCAM

CAM Debug Register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

dbg_hpr_q_depth : High priority read queue depth FOR DEBUG ONLY
bits : 0 - 5 (6 bit)
access : read-only

dbg_lpr_q_depth : Low priority read queue depth The last entry of Lpr queue is reserved for ECC SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY
bits : 8 - 13 (6 bit)
access : read-only

dbg_w_q_depth : Write queue depth The last entry of WR queue is reserved for ECC SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY
bits : 16 - 21 (6 bit)
access : read-only

dbg_stall : Stall FOR DEBUG ONLY
bits : 24 - 24 (1 bit)
access : read-only

dbg_rd_q_empty : When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. An example use-case scenario: When Controller enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time. FOR DEBUG ONLY
bits : 25 - 25 (1 bit)
access : read-only

dbg_wr_q_empty : When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. An example use-case scenario: When Controller enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time. FOR DEBUG ONLY
bits : 26 - 26 (1 bit)
access : read-only

rd_data_pipeline_empty : This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed.
bits : 28 - 28 (1 bit)
access : read-only

wr_data_pipeline_empty : This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed.
bits : 29 - 29 (1 bit)
access : read-only

dbg_stall_wr : Stall for Write channel FOR DEBUG ONLY
bits : 30 - 30 (1 bit)
access : read-only

dbg_stall_rd : Stall for Read channel FOR DEBUG ONLY
bits : 31 - 31 (1 bit)
access : read-only

DBGCMD

Command Debug Register
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

rank0_refresh : Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRC. For 3DS configuration, refresh is sent to rank index 0. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode.
bits : 0 - 0 (1 bit)
access : read-write

rank1_refresh : Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in DDRC. For 3DS configuration, refresh is sent to rank index 1. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode.
bits : 1 - 1 (1 bit)
access : read-write

zq_calib_short : Setting this register bit to 1 indicates to the DDRC to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRC, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mode.
bits : 4 - 4 (1 bit)
access : read-write

ctrlupd : Setting this register bit to 1 indicates to the DDRC to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRC, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.
bits : 5 - 5 (1 bit)
access : read-write

DBGSTAT

Status Debug Register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

rank0_refresh_busy : SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRC. It is recommended not to perform rank0_refresh operations when this signal is high. - 0 - Indicates that the SoC core can initiate a rank0_refresh operation - 1 - Indicates that rank0_refresh operation has not been stored yet in the DDRC
bits : 0 - 0 (1 bit)
access : read-only

rank1_refresh_busy : SoC core may initiate a rank1_refresh operation (refresh operation to rank 1) only if this signal is low. This signal goes high in the clock after DBGCMD.rank1_refresh is set to one. It goes low when the rank1_refresh operation is stored in the DDRC. It is recommended not to perform rank1_refresh operations when this signal is high. - 0 - Indicates that the SoC core can initiate a rank1_refresh operation - 1 - Indicates that rank1_refresh operation has not been stored yet in the DDRC
bits : 1 - 1 (1 bit)
access : read-only

zq_calib_short_busy : SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRC accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRC. It is recommended not to perform ZQCS operations when this signal is high. - 0 - Indicates that the SoC core can initiate a ZQCS operation - 1 - Indicates that ZQCS operation has not been initiated yet in the DDRC
bits : 4 - 4 (1 bit)
access : read-only

ctrlupd_busy : SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRC accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRC. It is recommended not to perform ctrlupd operations when this signal is high. - 0 - Indicates that the SoC core can initiate a ctrlupd operation - 1 - Indicates that ctrlupd operation has not been initiated yet in the DDRC
bits : 5 - 5 (1 bit)
access : read-only

SWCTL

Software Register Programming Control Enable
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

sw_done : Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done.
bits : 0 - 0 (1 bit)
access : read-write

SWSTAT

Software Register Programming Control Status
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

sw_done_ack : Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains.
bits : 0 - 0 (1 bit)
access : read-only

PWRTMG

Low Power Timing Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

powerdown_to_x32 : After this many clocks of the DDRC command channel being idle the DDRC automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. Unit: Multiples of 32 DFI clocks FOR PERFORMANCE ONLY.
bits : 0 - 4 (5 bit)
access : read-write

t_dpd_x4096 : Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Multiples of 4096 DFI clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY.
bits : 8 - 15 (8 bit)
access : read-write

selfref_to_x32 : After this many clocks of the DDRC command channel being idle the DDRC automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. Unit: Multiples of 32 DFI clocks. FOR PERFORMANCE ONLY.
bits : 16 - 23 (8 bit)
access : read-write

POISONCFG

AXI Poison Configuration Register.
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

wr_poison_slverr_en : If set to 1, enables SLVERR response for write transaction poisoning
bits : 0 - 0 (1 bit)
access : read-write

wr_poison_intr_en : If set to 1, enables interrupts for write transaction poisoning
bits : 4 - 4 (1 bit)
access : read-write

wr_poison_intr_clr : Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts.
bits : 8 - 8 (1 bit)
access : read-write

rd_poison_slverr_en : If set to 1, enables SLVERR response for read transaction poisoning
bits : 16 - 16 (1 bit)
access : read-write

rd_poison_intr_en : If set to 1, enables interrupts for read transaction poisoning
bits : 20 - 20 (1 bit)
access : read-write

rd_poison_intr_clr : Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts.
bits : 24 - 24 (1 bit)
access : read-write

POISONSTAT

AXI Poison Status Register
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

wr_poison_intr_0 : Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock.
bits : 0 - 0 (1 bit)
access : read-only

rd_poison_intr_0 : Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock.
bits : 16 - 16 (1 bit)
access : read-only

HWLPCTL

Hardware Low Power Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

hw_lp_en : Enable for Hardware Low Power Interface.
bits : 0 - 0 (1 bit)
access : read-write

hw_lp_exit_idle_en : When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it will not cause exit of Self-Refresh that was caused by Hardware Low Power Interface and/or Software (PWRCTL.selfref_sw).
bits : 1 - 1 (1 bit)
access : read-write

hw_lp_idle_x32 : Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. Unit: Multiples of 32 DFI clocks. FOR PERFORMANCE ONLY.
bits : 16 - 27 (12 bit)
access : read-write

PSTAT

Port Status Register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

rd_port_busy_0 : Indicates if there are outstanding reads for AXI port 0.
bits : 0 - 0 (1 bit)
access : read-only

wr_port_busy_0 : Indicates if there are outstanding writes for AXI port 0.
bits : 16 - 16 (1 bit)
access : read-only

STAT

Operating Mode Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

operating_mode : Operating mode
bits : 0 - 2 (3 bit)
access : read-only

selfref_type : Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not.
bits : 4 - 5 (2 bit)
access : read-only

Enumeration:

0 : selfref_type_0

SDRAM is not in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by CRCPARCTRL1.crc_parity_retry_enable, this also indicates SRE command is still in parity error window or retry is in-progress.

0x2 : selfref_type_2

SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was not caused solely under Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software (reg_ddrc_selfref_sw). If retry is enabled, this guarantees SRE command is executed correctly without parity

0x3 : selfref_type_3

SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was caused by Automatic Self Refresh only. If retry is enabled, this guarantees SRE command is executed correctly without parity error.

End of enumeration elements list.

selfref_state : Self refresh state. This indicates self refresh or self refresh power down state for LPDDR4. This register is used for frequency change and MRR/MRW access during self refresh.
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : selfref_state_0

SDRAM is not in Self Refresh.

0x1 : selfref_state_1

Self refresh 1

0x2 : selfref_state_2

Self refresh power down

0x3 : selfref_state_3

Self refresh

End of enumeration elements list.

PCCFG

Port Common Configuration Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

go2critical_en : If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.
bits : 0 - 0 (1 bit)
access : read-write

pagematch_limit : Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions.
bits : 4 - 4 (1 bit)
access : read-write

bl_exp_mode : Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to both reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Partial Writes is enabled (DDRC_PARTIAL_WR=1), in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd_mw penalty in LPDDR4. Hence, bl_exp_mode=1 is only recommended if DDR4 or LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - DDRC_PARTIAL_WR=0 - DDRC_PARTIAL_WR=1, MSTR.data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.burst_rdwr=1000 (LPDDR4 only) - DDRC_PARTIAL_WR=1, MSTR.data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.burst_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Data Channel Interleave is enabled
bits : 8 - 8 (1 bit)
access : read-write

PCFGR_0

Port n Configuration Read Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

rd_port_priority : Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: The two LSBs of this register field are tied internally to 2'b00.
bits : 0 - 9 (10 bit)
access : read-write

rd_port_aging_en : If set to 1, enables aging function for the read channel of the port.
bits : 12 - 12 (1 bit)
access : read-write

rd_port_urgent_en : If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command).
bits : 13 - 13 (1 bit)
access : read-write

rd_port_pagematch_en : If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register.
bits : 14 - 14 (1 bit)
access : read-write

rdwr_ordered_en : Enable ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the DDRC_RDWR_ORDERED_n parameter.
bits : 16 - 16 (1 bit)
access : read-write

PCFGW_0

Port n Configuration Write Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

wr_port_priority : Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port's priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. Note: The two LSBs of this register field are tied internally to 2'b00.
bits : 0 - 9 (10 bit)
access : read-write

wr_port_aging_en : If set to 1, enables aging function for the write channel of the port.
bits : 12 - 12 (1 bit)
access : read-write

wr_port_urgent_en : If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command).
bits : 13 - 13 (1 bit)
access : read-write

wr_port_pagematch_en : If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register.
bits : 14 - 14 (1 bit)
access : read-write

PCTRL_0

Port n Control Register
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

port_en : Enables AXI port n.
bits : 0 - 0 (1 bit)
access : read-write

PCFGQOS0_0

Port n Read QoS Configuration Register 0
address_offset : 0x494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

rqos_map_level1 : Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinct values.
bits : 0 - 3 (4 bit)
access : read-write

rqos_map_region0 : This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support is disabled (DDRC_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
bits : 16 - 17 (2 bit)
access : read-write

rqos_map_region1 : This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is disabled (DDRC_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
bits : 20 - 21 (2 bit)
access : read-write

PCFGQOS1_0

Port n Read QoS Configuration Register 1
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

rqos_map_timeoutb : Specifies the timeout value for transactions mapped to the blue address queue.
bits : 0 - 10 (11 bit)
access : read-write

rqos_map_timeoutr : Specifies the timeout value for transactions mapped to the red address queue.
bits : 16 - 26 (11 bit)
access : read-write

PCFGWQOS0_0

Port n Write QoS Configuration Register 0
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

wqos_map_level : Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which corresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value corresponds to higher port priority.
bits : 0 - 3 (4 bit)
access : read-write

wqos_map_region0 : This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (DDRC_VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
bits : 16 - 17 (2 bit)
access : read-write

wqos_map_region1 : This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (DDRC_VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
bits : 20 - 21 (2 bit)
access : read-write

PCFGWQOS1_0

Port n Write QoS Configuration Register 1
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

wqos_map_timeout : Specifies the timeout value for write transactions.
bits : 0 - 10 (11 bit)
access : read-write

RFSHCTL0

Refresh Control Register 0
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

per_bank_refresh : Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : per_bank_refresh_0

All bank refresh

0x1 : per_bank_refresh_1

Per bank refresh

End of enumeration elements list.

RFSHCTL1

Refresh Control Register 1
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

refresh_timer0_start_value_x32 : Refresh timer start for rank 0 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples of 32 DFI clock cycles. FOR PERFORMANCE ONLY.
bits : 0 - 11 (12 bit)
access : read-write

refresh_timer1_start_value_x32 : Refresh timer start for rank 1 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples of 32 DFI clock cycles. FOR PERFORMANCE ONLY.
bits : 16 - 27 (12 bit)
access : read-write

RFSHCTL3

Refresh Control Register 3
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dis_auto_refresh : When '1', disable auto-refresh generated by the DDRC. When auto-refresh is disabled, the SoC core must generate refreshes using the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the DDRC. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'. (DDR4 only) If FGR mode is enabled (RFSHCTL3.refresh_mode > 0), disable auto-refresh is not supported, and this bit must be set to '0'. This register field is changeable on the fly.
bits : 0 - 0 (1 bit)
access : read-write

refresh_update_level : Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. refresh_update_level must not be toggled when the DDRC is in reset (core_ddrc_rstn = 0). The refresh register(s) are automatically updated when exiting reset.
bits : 1 - 1 (1 bit)
access : read-write

refresh_mode : Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: Only Fixed 1x mode is supported if RFSHCTL3.dis_auto_refresh = 1. Note: The on-the-fly modes are not supported in this version of the DDRC. Note: This must be set up while the Controller is in reset or while the Controller is in self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in future version of the DDRC. Note: This register field has effect only if a DDR4 SDRAM device is in use (MSTR.ddr4 = 1).
bits : 4 - 6 (3 bit)
access : read-write

RFSHTMG

Refresh Timing Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRCPARCTL0

CRC Parity Control Register0
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dfi_alert_err_int_en : Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input will result in an interrupt being set on CRCPARSTAT.dfi_alert_err_int.
bits : 0 - 0 (1 bit)
access : read-write

dfi_alert_err_int_clr : Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int will be cleared. When the clear operation is complete, the DDRC automatically clears this bit.
bits : 1 - 1 (1 bit)
access : read-write

dfi_alert_err_cnt_clr : DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit will clear the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRC automatically clears this bit.
bits : 2 - 2 (1 bit)
access : read-write

CRCPARCTL1

CRC Parity Control Register1
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

parity_enable : C/A Parity enable register. If RCD's parity error detection or SDRAM's parity detection is enabled, this register should be 1.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : parity_enable_0

Disable generation of C/A parity and disable detection of C/A parity error

0x1 : parity_enable_1

Enable generation of C/A parity and detection of C/A parity error

End of enumeration elements list.

crc_enable : CRC enable Register. The setting of this register should match the CRC mode register setting in the DRAM.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : crc_enable_0

isable generation of CRC

0x1 : crc_enable_1

Enable generation of CRC

End of enumeration elements list.

crc_inc_dm : CRC Calculation setting register. Present only in designs configured to support DDR4.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : crc_inc_dm_0

CRC not includes DM signal

0x1 : crc_inc_dm_1

CRC includes DM signal

End of enumeration elements list.

caparity_disable_before_sr : If DDR4-SDRAM's CA parity is enabled by INIT6.mr5[2:0]!=0 and this register is set to 1, CA parity is automatically disabled before Self-Refresh entry and enabled after Self-Refresh exit by issuing MR5. - 1: CA parity is disabled before Self-Refresh entry - 0: CA parity is not disabled before Self-Refresh entry If Geardown is used by MSTR.geardown_mode=1, this register must be set to 1. If this register set to 0, DRAMTMG5.t_ckesr and DRAMTMG5.t_cksre must be increased by PL(Parity latency)
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : caparity_disable_before_sr_0

CA parity is not disabled before Self-Refresh entry

0x1 : caparity_disable_before_sr_1

CA parity is disabled before Self-Refresh entry

End of enumeration elements list.

CRCPARSTAT

CRC Parity Status Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

dfi_alert_err_cnt : DFI alert error count. If a parity/CRC error is detected on dfi_alert_n, this counter be incremented. This is independent of the setting of CRCPARCTL0.dfi_alert_err_int_en. It will saturate at 0xFFFF, and can be cleared by asserting CRCPARCTL0.dfi_alert_err_cnt_clr.
bits : 0 - 15 (16 bit)
access : read-only

dfi_alert_err_int : DFI alert error interrupt. If a parity/CRC error is detected on dfi_alert_n, and the interrupt is enabled by CRCPARCTL0.dfi_alert_err_int_en, this interrupt bit will be set. It will remain set until cleared by CRCPARCTL0.dfi_alert_err_int_clr
bits : 16 - 16 (1 bit)
access : read-only

INIT0

SDRAM Initialization Register 0
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pre_cke_x1024 : Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 DFI clock cycles. DDR2 specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. For DDR3/DDR4 RDIMMs, this should include the time needed to satisfy tSTAB
bits : 0 - 11 (12 bit)
access : read-write

post_cke_x1024 : Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 DFI clock cycles. DDR2 typically requires a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be programmed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value.
bits : 16 - 25 (10 bit)
access : read-write

skip_dram_init : If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Initialization routine is skipped after power-up. Controller starts up in Normal Mode - 11 - SDRAM Initialization routine is skipped after power-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Initialization routine is run after power-up.
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

0 : skip_dram_init_0

SDRAM Initialization routine is run after power-up

0x1 : skip_dram_init_1

SDRAM Initialization routine is skipped after power-up

0x2 : skip_dram_init_2

SDRAM Initialization routine is run after power-up

0x3 : skip_dram_init_3

SDRAM Initialization routine is skipped after power-up

End of enumeration elements list.

INIT1

SDRAM Initialization Register 1
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

pre_ocd_x32 : Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 DFI clock cycles. There is no known specific requirement for this; it may be set to zero.
bits : 0 - 3 (4 bit)
access : read-write

dram_rstn_x1024 : Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1. When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. Unit: 1024 DFI clock cycles.
bits : 16 - 24 (9 bit)
access : read-write

INIT2

SDRAM Initialization Register 2
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

min_stable_clock_x1 : Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 5 x tCK delay. When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. Unit: DFI clock cycles.
bits : 0 - 3 (4 bit)
access : read-write

idle_after_reset_x32 : Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. Unit: 32 DFI clock cycles.
bits : 8 - 15 (8 bit)
access : read-write

INIT3

SDRAM Initialization Register 3
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INIT4

SDRAM Initialization Register 4
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

emr3 : DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 register
bits : 0 - 15 (16 bit)
access : read-write

emr2 : DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unused
bits : 16 - 31 (16 bit)
access : read-write

INIT5

SDRAM Initialization Register 5
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

max_auto_init_x1024 : Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 10 us. Unit: 1024 DFI clock cycles.
bits : 0 - 9 (10 bit)
access : read-write

dev_zqinit_x32 : ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. DDR3 typically requires 512 SDRAM clock cycles. DDR4 requires 1024 SDRAM clock cycles. LPDDR2/LPDDR3 requires 1 us. When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. Unit: 32 DFI clock cycles.
bits : 16 - 23 (8 bit)
access : read-write

INIT6

SDRAM Initialization Register 6
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

mr5 : DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.
bits : 0 - 15 (16 bit)
access : read-write

mr4 : DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.
bits : 16 - 31 (16 bit)
access : read-write

INIT7

SDRAM Initialization Register 7
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

mr6 : DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.
bits : 16 - 31 (16 bit)
access : read-write

DIMMCTL

DIMM Control Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

dimm_stagger_cs_en : Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs.Even if this bit is set it does not take care of software driven MR commands (via MRCTRL0/MRCTRL1), where software is responsible to send them to separate ranks as appropriate.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : dimm_stagger_cs_en_0

Do not stagger accesses

0x1 : dimm_stagger_cs_en_1

(non-DDR4) Send all commands to even and odd ranks separately

End of enumeration elements list.

dimm_addr_mirr_en : Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures that, for mode register accesses during the automatic initialization routine, these bits are swapped within the DDRC to compensate for this UDIMM/RDIMM/LRDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM/LRDIMM, they are swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : dimm_addr_mirr_en_0

Do not implement address mirroring

0x1 : dimm_addr_mirr_en_1

For odd ranks, implement address mirroring for MRS commands to during initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM/LRDIMM implements address mirroring)

End of enumeration elements list.

dimm_output_inv_en : Output Inversion Enable (for DDR4 RDIMM/LRDIMM implementations only). DDR4 RDIMM/LRDIMM implements the Output Inversion feature by default, which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the DDRC during the automatic initialization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. For B-side mode register accesses, these bits are inverted within the DDRC to compensate for this RDIMM/LRDIMM inversion. It is recommended to set this bit always, if using DDR4 RDIMMs/LRDIMMs. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : dimm_output_inv_en_0

Do not implement output inversion for B-side DRAMs.

0x1 : dimm_output_inv_en_1

Implement output inversion for B-side DRAMs.

End of enumeration elements list.

mrs_a17_en : Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, this must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : mrs_a17_en_0

Disabled

0x1 : mrs_a17_en_1

Enabled

End of enumeration elements list.

mrs_bg1_en : Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output Inversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is enabled, this is applied to BG1 of even ranks and BG0 of odd ranks.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : mrs_bg1_en_0

Disabled

0x1 : mrs_bg1_en_1

Enabled

End of enumeration elements list.

dimm_dis_bg_mirroring : Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enabled. This will be required for DDR4 DIMMs with x16 devices.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : dimm_dis_bg_mirroring_0

BG0 and BG1 are swapped if address mirroring is enabled.

0x1 : dimm_dis_bg_mirroring_1

BG0 and BG1 are NOT swapped.

End of enumeration elements list.

lrdimm_bcom_cmd_prot : Protects the timing restrictions (tBCW/tMRC) between consecutive BCOM commands defined in the Data Buffer specification. When using DDR4 LRDIMM, this bit must be set to 1. Otherwise, this bit must be set to 0.
bits : 6 - 6 (1 bit)
access : read-write

RANKCTL

Rank Control Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

max_rank_rd : Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus contention as well as to give PHY enough time to switch the delay when changing ranks. The DDRC arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_rank_rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutively to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as long as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0xF. FOR PERFORMANCE ONLY.
bits : 0 - 3 (4 bit)
access : read-write

diff_rank_rd_gap : Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should consider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing requirement when switching ranks during reads. When the controller is operating in 1:1 mode, program this to the larger of PHY requirement or ODT requirement. When the controller is operating in 1:2 mode, program this to the larger value divided by two and round it up to the next integer. Note that, if using DDR4-LRDIMM, refer to TRDRD timing requirements in JEDEC DDR4 Data Buffer (DDR4DB01) Specification.
bits : 4 - 7 (4 bit)
access : read-write

diff_rank_wr_gap : Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should consider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcsgap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 When the controller is operating in 1:1 mode, program this to the larger of PHY requirement or ODT requirement. When the controller is operating in 1:2 mode, program this to the larger value divided by two and round it up to the next integer. Note that, if using DDR4-LRDIMM, refer to TWRWR timing requirements in JEDEC DDR4 Data Buffer (DDR4DB01) Specification.
bits : 8 - 11 (4 bit)
access : read-write

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DDRC_REGS

Peripheral Memory Blocks

Registers

MSTR

MRCTRL0

DRAMTMG0

DRAMTMG1

DRAMTMG2

DRAMTMG3

DRAMTMG4

DRAMTMG5

DRAMTMG6

DRAMTMG7

DRAMTMG8

DRAMTMG9

DRAMTMG10

DRAMTMG11

DRAMTMG12

DRAMTMG13

DRAMTMG14

DRAMTMG15

MRCTRL1

MRSTAT

ZQCTL0

ZQCTL1

ZQCTL2

ZQSTAT

DFITMG0

DFITMG1

DFILPCFG0

DFILPCFG1

DFIUPD0

DFIUPD1

DFIUPD2

DFIMISC

DFITMG2

DFITMG3

DFISTAT

MRCTRL2

DBICTL

DERATEEN

ADDRMAP0

DERATEEN_SHADOW

DERATEINT_SHADOW

ADDRMAP1

RFSHCTL0_SHADOW

RFSHTMG_SHADOW

ADDRMAP2

ADDRMAP3

INIT3_SHADOW

INIT4_SHADOW

INIT6_SHADOW

INIT7_SHADOW

ADDRMAP4

DRAMTMG0_SHADOW

DRAMTMG1_SHADOW

DRAMTMG2_SHADOW

DRAMTMG3_SHADOW

DRAMTMG4_SHADOW

DRAMTMG5_SHADOW

DRAMTMG6_SHADOW

DRAMTMG7_SHADOW

DRAMTMG8_SHADOW

DRAMTMG9_SHADOW

DRAMTMG10_SHADOW

DRAMTMG11_SHADOW

DRAMTMG12_SHADOW

DRAMTMG13_SHADOW

DRAMTMG14_SHADOW

DRAMTMG15_SHADOW

ADDRMAP5

ADDRMAP6

ZQCTL0_SHADOW

DFITMG0_SHADOW

DFITMG1_SHADOW

DFITMG2_SHADOW

DFITMG3_SHADOW

ADDRMAP7

ADDRMAP8