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PIT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x140 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MCR

TIMER[0]-LDVAL

TIMER[0]-CVAL

TIMER[0]-TCTRL

TIMER[0]-TFLG

TIMER[1]-TIMER[0]-LDVAL

TIMER[1]-TIMER[0]-CVAL

TIMER[1]-TIMER[0]-TCTRL

TIMER[1]-TIMER[0]-TFLG

TIMER[2]-TIMER[1]-TIMER[0]-LDVAL

TIMER[2]-TIMER[1]-TIMER[0]-CVAL

TIMER[2]-TIMER[1]-TIMER[0]-TCTRL

TIMER[2]-TIMER[1]-TIMER[0]-TFLG

TIMER[3]-TIMER[2]-TIMER[1]-TIMER[0]-LDVAL

TIMER[3]-TIMER[2]-TIMER[1]-TIMER[0]-CVAL

TIMER[3]-TIMER[2]-TIMER[1]-TIMER[0]-TCTRL

TIMER[3]-TIMER[2]-TIMER[1]-TIMER[0]-TFLG

LTMR64H

LTMR64L


MCR

PIT Module Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRZ MDIS

FRZ : Freeze
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : FRZ_0

Timers continue to run in Debug mode.

0x1 : FRZ_1

Timers are stopped in Debug mode.

End of enumeration elements list.

MDIS : Module Disable - (PIT section)
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : MDIS_0

Clock for standard PIT timers is enabled.

0x1 : MDIS_1

Clock for standard PIT timers is disabled.

End of enumeration elements list.


TIMER[0]-LDVAL

Timer Load Value Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER[0]-LDVAL TIMER[0]-LDVAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSV

TSV : Timer Start Value
bits : 0 - 31 (32 bit)
access : read-write


TIMER[0]-CVAL

Current Timer Value Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TIMER[0]-CVAL TIMER[0]-CVAL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TVL

TVL : Current Timer Value
bits : 0 - 31 (32 bit)
access : read-only


TIMER[0]-TCTRL

Timer Control Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER[0]-TCTRL TIMER[0]-TCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TIE CHN

TEN : Timer Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : TEN_0

Timer n is disabled.

0x1 : TEN_1

Timer n is enabled.

End of enumeration elements list.

TIE : Timer Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : TIE_0

Interrupt requests from Timer n are disabled.

0x1 : TIE_1

Interrupt will be requested whenever TIF is set.

End of enumeration elements list.

CHN : Chain Mode
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : CHN_0

Timer is not chained.

0x1 : CHN_1

Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.

End of enumeration elements list.


TIMER[0]-TFLG

Timer Flag Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER[0]-TFLG TIMER[0]-TFLG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIF

TIF : Timer Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : TIF_0

Timeout has not yet occurred.

0x1 : TIF_1

Timeout has occurred.

End of enumeration elements list.


TIMER[1]-TIMER[0]-LDVAL

Timer Load Value Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER[1]-TIMER[0]-LDVAL TIMER[1]-TIMER[0]-LDVAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSV

TSV : Timer Start Value
bits : 0 - 31 (32 bit)
access : read-write


TIMER[1]-TIMER[0]-CVAL

Current Timer Value Register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TIMER[1]-TIMER[0]-CVAL TIMER[1]-TIMER[0]-CVAL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TVL

TVL : Current Timer Value
bits : 0 - 31 (32 bit)
access : read-only


TIMER[1]-TIMER[0]-TCTRL

Timer Control Register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER[1]-TIMER[0]-TCTRL TIMER[1]-TIMER[0]-TCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TIE CHN

TEN : Timer Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : TEN_0

Timer n is disabled.

0x1 : TEN_1

Timer n is enabled.

End of enumeration elements list.

TIE : Timer Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : TIE_0

Interrupt requests from Timer n are disabled.

0x1 : TIE_1

Interrupt will be requested whenever TIF is set.

End of enumeration elements list.

CHN : Chain Mode
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : CHN_0

Timer is not chained.

0x1 : CHN_1

Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.

End of enumeration elements list.


TIMER[1]-TIMER[0]-TFLG

Timer Flag Register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER[1]-TIMER[0]-TFLG TIMER[1]-TIMER[0]-TFLG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIF

TIF : Timer Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : TIF_0

Timeout has not yet occurred.

0x1 : TIF_1

Timeout has occurred.

End of enumeration elements list.


TIMER[2]-TIMER[1]-TIMER[0]-LDVAL

Timer Load Value Register
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER[2]-TIMER[1]-TIMER[0]-LDVAL TIMER[2]-TIMER[1]-TIMER[0]-LDVAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSV

TSV : Timer Start Value
bits : 0 - 31 (32 bit)
access : read-write


TIMER[2]-TIMER[1]-TIMER[0]-CVAL

Current Timer Value Register
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TIMER[2]-TIMER[1]-TIMER[0]-CVAL TIMER[2]-TIMER[1]-TIMER[0]-CVAL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TVL

TVL : Current Timer Value
bits : 0 - 31 (32 bit)
access : read-only


TIMER[2]-TIMER[1]-TIMER[0]-TCTRL

Timer Control Register
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER[2]-TIMER[1]-TIMER[0]-TCTRL TIMER[2]-TIMER[1]-TIMER[0]-TCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TIE CHN

TEN : Timer Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : TEN_0

Timer n is disabled.

0x1 : TEN_1

Timer n is enabled.

End of enumeration elements list.

TIE : Timer Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : TIE_0

Interrupt requests from Timer n are disabled.

0x1 : TIE_1

Interrupt will be requested whenever TIF is set.

End of enumeration elements list.

CHN : Chain Mode
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : CHN_0

Timer is not chained.

0x1 : CHN_1

Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.

End of enumeration elements list.


TIMER[2]-TIMER[1]-TIMER[0]-TFLG

Timer Flag Register
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER[2]-TIMER[1]-TIMER[0]-TFLG TIMER[2]-TIMER[1]-TIMER[0]-TFLG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIF

TIF : Timer Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : TIF_0

Timeout has not yet occurred.

0x1 : TIF_1

Timeout has occurred.

End of enumeration elements list.


TIMER[3]-TIMER[2]-TIMER[1]-TIMER[0]-LDVAL

Timer Load Value Register
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER[3]-TIMER[2]-TIMER[1]-TIMER[0]-LDVAL TIMER[3]-TIMER[2]-TIMER[1]-TIMER[0]-LDVAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSV

TSV : Timer Start Value
bits : 0 - 31 (32 bit)
access : read-write


TIMER[3]-TIMER[2]-TIMER[1]-TIMER[0]-CVAL

Current Timer Value Register
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TIMER[3]-TIMER[2]-TIMER[1]-TIMER[0]-CVAL TIMER[3]-TIMER[2]-TIMER[1]-TIMER[0]-CVAL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TVL

TVL : Current Timer Value
bits : 0 - 31 (32 bit)
access : read-only


TIMER[3]-TIMER[2]-TIMER[1]-TIMER[0]-TCTRL

Timer Control Register
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER[3]-TIMER[2]-TIMER[1]-TIMER[0]-TCTRL TIMER[3]-TIMER[2]-TIMER[1]-TIMER[0]-TCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TIE CHN

TEN : Timer Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : TEN_0

Timer n is disabled.

0x1 : TEN_1

Timer n is enabled.

End of enumeration elements list.

TIE : Timer Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : TIE_0

Interrupt requests from Timer n are disabled.

0x1 : TIE_1

Interrupt will be requested whenever TIF is set.

End of enumeration elements list.

CHN : Chain Mode
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : CHN_0

Timer is not chained.

0x1 : CHN_1

Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.

End of enumeration elements list.


TIMER[3]-TIMER[2]-TIMER[1]-TIMER[0]-TFLG

Timer Flag Register
address_offset : 0x46C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER[3]-TIMER[2]-TIMER[1]-TIMER[0]-TFLG TIMER[3]-TIMER[2]-TIMER[1]-TIMER[0]-TFLG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIF

TIF : Timer Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : TIF_0

Timeout has not yet occurred.

0x1 : TIF_1

Timeout has occurred.

End of enumeration elements list.


LTMR64H

PIT Upper Lifetime Timer Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LTMR64H LTMR64H read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTH

LTH : Life Timer value
bits : 0 - 31 (32 bit)
access : read-only


LTMR64L

PIT Lower Lifetime Timer Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LTMR64L LTMR64L read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTL

LTL : Life Timer value
bits : 0 - 31 (32 bit)
access : read-only



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