\n
address_offset : 0x0 Bytes (0x0)
size : 0x800 byte (0x0)
mem_usage : registers
protection : not protected
DSI Host Version Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Version of the DSI Host
bits : 0 - 31 (32 bit)
DSI Host LTDC Color Coding Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COLC : Color Coding
bits : 0 - 3 (4 bit)
LPE : Loosely Packet Enable
bits : 8 - 8 (1 bit)
DSI Host Video Shadow Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable
bits : 0 - 0 (1 bit)
UR : Update Register
bits : 8 - 8 (1 bit)
DSI Host LTDC Current VCID Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VCID : Virtual Channel ID
bits : 0 - 1 (2 bit)
DSI Host LTDC Current Color Coding Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COLC : Color Coding
bits : 0 - 3 (4 bit)
LPE : Loosely Packed Enable
bits : 8 - 8 (1 bit)
DSI Host Low-Power mode Current Configuration Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VLPSIZE : VACT Largest Packet Size
bits : 0 - 7 (8 bit)
LPSIZE : Largest Packet Size
bits : 16 - 23 (8 bit)
DSI Host Video mode Current Configuration Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VMT : Video mode Type
bits : 0 - 1 (2 bit)
LPVSAE : Low-Power Vertical Sync time Enable
bits : 2 - 2 (1 bit)
LPVBPE : Low-power Vertical Back-Porch Enable
bits : 3 - 3 (1 bit)
LPVFPE : Low-power Vertical Front-Porch Enable
bits : 4 - 4 (1 bit)
LPVAE : Low-Power Vertical Active Enable
bits : 5 - 5 (1 bit)
LPHBPE : Low-power Horizontal Back-Porch Enable
bits : 6 - 6 (1 bit)
LPHFE : Low-Power Horizontal Front-Porch Enable
bits : 7 - 7 (1 bit)
FBTAAE : Frame BTA Acknowledge Enable
bits : 8 - 8 (1 bit)
LPCE : Low-Power Command Enable
bits : 9 - 9 (1 bit)
DSI Host Video Packet Current Configuration Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VPSIZE : Video Packet Size
bits : 0 - 13 (14 bit)
DSI Host LTDC Polarity Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEP : Data Enable Polarity
bits : 0 - 0 (1 bit)
VSP : VSYNC Polarity
bits : 1 - 1 (1 bit)
HSP : HSYNC Polarity
bits : 2 - 2 (1 bit)
DSI Host Video Chunks Current Configuration Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NUMC : Number of Chunks
bits : 0 - 12 (13 bit)
DSI Host Video Null Packet Current Configuration Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NPSIZE : Null Packet Size
bits : 0 - 12 (13 bit)
DSI Host Video HSA Current Configuration Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HSA : Horizontal Synchronism Active duration
bits : 0 - 11 (12 bit)
DSI Host Video HBP Current Configuration Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HBP : Horizontal Back-Porch duration
bits : 0 - 11 (12 bit)
DSI Host Video Line Current Configuration Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HLINE : Horizontal Line duration
bits : 0 - 14 (15 bit)
DSI Host Video VSA Current Configuration Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VSA : Vertical Synchronism Active duration
bits : 0 - 9 (10 bit)
DSI Host Video VBP Current Configuration Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VBP : Vertical Back-Porch duration
bits : 0 - 9 (10 bit)
DSI Host Video VFP Current Configuration Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VFP : Vertical Front-Porch duration
bits : 0 - 9 (10 bit)
DSI Host Video VA Current Configuration Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VA : Vertical Active duration
bits : 0 - 13 (14 bit)
DSI Host Low-Power mode Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLPSIZE : VACT Largest Packet Size
bits : 0 - 7 (8 bit)
LPSIZE : Largest Packet Size
bits : 16 - 23 (8 bit)
DSI Host Protocol Configuration Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETTXE : EoTp Transmission Enable
bits : 0 - 0 (1 bit)
ETRXE : EoTp Reception Enable
bits : 1 - 1 (1 bit)
BTAE : Bus Turn Around Enable
bits : 2 - 2 (1 bit)
ECCRXE : ECC Reception Enable
bits : 3 - 3 (1 bit)
CRCRXE : CRC Reception Enable
bits : 4 - 4 (1 bit)
DSI Host Generic VCID Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VCID : Virtual Channel ID
bits : 0 - 1 (2 bit)
DSI Host mode Configuration Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDM : Command mode
bits : 0 - 0 (1 bit)
DSI Host Video mode Configuration Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VMT : Video mode Type
bits : 0 - 1 (2 bit)
LPVSAE : Low-Power Vertical Sync Active Enable
bits : 8 - 8 (1 bit)
LPVBPE : Low-power Vertical Back-Porch Enable
bits : 9 - 9 (1 bit)
LPVFPE : Low-power Vertical Front-porch Enable
bits : 10 - 10 (1 bit)
LPVAE : Low-Power Vertical Active Enable
bits : 11 - 11 (1 bit)
LPHBPE : Low-Power Horizontal Back-Porch Enable
bits : 12 - 12 (1 bit)
LPHFPE : Low-Power Horizontal Front-Porch Enable
bits : 13 - 13 (1 bit)
FBTAAE : Frame Bus-Turn-Around Acknowledge Enable
bits : 14 - 14 (1 bit)
LPCE : Low-Power Command Enable
bits : 15 - 15 (1 bit)
PGE : Pattern Generator Enable
bits : 16 - 16 (1 bit)
PGM : Pattern Generator mode
bits : 20 - 20 (1 bit)
PGO : Pattern Generator Orientation
bits : 24 - 24 (1 bit)
DSI Host Video Packet Configuration Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VPSIZE : Video Packet Size
bits : 0 - 13 (14 bit)
DSI Host Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable
bits : 0 - 0 (1 bit)
DSI Host Video Chunks Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUMC : Number of Chunks
bits : 0 - 12 (13 bit)
DSI Wrapper Configuration Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIM : DSI Mode
bits : 0 - 0 (1 bit)
COLMUX : Color Multiplexing
bits : 1 - 3 (3 bit)
TESRC : TE Source
bits : 4 - 4 (1 bit)
TEPOL : TE Polarity
bits : 5 - 5 (1 bit)
AR : Automatic Refresh
bits : 6 - 6 (1 bit)
VSPOL : VSync Polarity
bits : 7 - 7 (1 bit)
DSI Wrapper Control Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COLM : Color Mode
bits : 0 - 0 (1 bit)
SHTDN : Shutdown
bits : 1 - 1 (1 bit)
LTDCEN : LTDC Enable
bits : 2 - 2 (1 bit)
DSIEN : DSI Enable
bits : 3 - 3 (1 bit)
DSI Wrapper Interrupt Enable Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEIE : Tearing Effect Interrupt Enable
bits : 0 - 0 (1 bit)
ERIE : End of Refresh Interrupt Enable
bits : 1 - 1 (1 bit)
PLLLIE : PLL Lock Interrupt Enable
bits : 9 - 9 (1 bit)
PLLUIE : PLL Unlock Interrupt Enable
bits : 10 - 10 (1 bit)
RRIE : Regulator Ready Interrupt Enable
bits : 13 - 13 (1 bit)
DSI Wrapper Interrupt and Status Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEIF : Tearing Effect Interrupt Flag
bits : 0 - 0 (1 bit)
ERIF : End of Refresh Interrupt Flag
bits : 1 - 1 (1 bit)
BUSY : Busy Flag
bits : 2 - 2 (1 bit)
PLLLS : PLL Lock Status
bits : 8 - 8 (1 bit)
PLLLIF : PLL Lock Interrupt Flag
bits : 9 - 9 (1 bit)
PLLUIF : PLL Unlock Interrupt Flag
bits : 10 - 10 (1 bit)
RRS : Regulator Ready Status
bits : 12 - 12 (1 bit)
RRIF : Regulator Ready Interrupt Flag
bits : 13 - 13 (1 bit)
DSI Wrapper Interrupt Flag Clear Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTEIF : Clear Tearing Effect Interrupt Flag
bits : 0 - 0 (1 bit)
CERIF : Clear End of Refresh Interrupt Flag
bits : 1 - 1 (1 bit)
CPLLLIF : Clear PLL Lock Interrupt Flag
bits : 9 - 9 (1 bit)
CPLLUIF : Clear PLL Unlock Interrupt Flag
bits : 10 - 10 (1 bit)
CRRIF : Clear Regulator Ready Interrupt Flag
bits : 13 - 13 (1 bit)
DSI Wrapper PHY Configuration Register 1
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIX4 : Unit Interval multiplied by 4
bits : 0 - 5 (6 bit)
SWCL : Swap Clock Lane pins
bits : 6 - 6 (1 bit)
SWDL0 : Swap Data Lane 0 pins
bits : 7 - 7 (1 bit)
SWDL1 : Swap Data Lane 1 pins
bits : 8 - 8 (1 bit)
HSICL : Invert Hight-Speed data signal on Clock Lane
bits : 9 - 9 (1 bit)
HSIDL0 : Invert the Hight-Speed data signal on Data Lane 0
bits : 10 - 10 (1 bit)
HSIDL1 : Invert the High-Speed data signal on Data Lane 1
bits : 11 - 11 (1 bit)
FTXSMCL : Force in TX Stop Mode the Clock Lane
bits : 12 - 12 (1 bit)
FTXSMDL : Force in TX Stop Mode the Data Lanes
bits : 13 - 13 (1 bit)
CDOFFDL : Contention Detection OFF on Data Lanes
bits : 14 - 14 (1 bit)
TDDL : Turn Disable Data Lanes
bits : 16 - 16 (1 bit)
PDEN : Pull-Down Enable
bits : 18 - 18 (1 bit)
TCLKPREPEN : custom time for tCLK-PREPARE Enable
bits : 19 - 19 (1 bit)
TCLKZEROEN : custom time for tCLK-ZERO Enable
bits : 20 - 20 (1 bit)
THSPREPEN : custom time for tHS-PREPARE Enable
bits : 21 - 21 (1 bit)
THSTRAILEN : custom time for tHS-TRAIL Enable
bits : 22 - 22 (1 bit)
THSZEROEN : custom time for tHS-ZERO Enable
bits : 23 - 23 (1 bit)
TLPXDEN : custom time for tLPX for Data lanes Enable
bits : 24 - 24 (1 bit)
THSEXITEN : custom time for tHS-EXIT Enable
bits : 25 - 25 (1 bit)
TLPXCEN : custom time for tLPX for Clock lane Enable
bits : 26 - 26 (1 bit)
TCLKPOSTEN : custom time for tCLK-POST Enable
bits : 27 - 27 (1 bit)
DSI Wrapper PHY Configuration Register 2
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSTXDCL : High-Speed Transmission Delay on Clock Lane
bits : 0 - 1 (2 bit)
HSTXDLL : High-Speed Transmission Delay on Data Lanes
bits : 2 - 3 (2 bit)
LPSRCL : Low-Power transmission Slew Rate Compensation on Clock Lane
bits : 6 - 7 (2 bit)
LPSRDL : Low-Power transmission Slew Rate Compensation on Data Lanes
bits : 8 - 9 (2 bit)
SDCC : SDD Control
bits : 12 - 12 (1 bit)
HSTXSRCCL : High-Speed Transmission Slew Rate Control on Clock Lane
bits : 16 - 17 (2 bit)
HSTXSRCDL : High-Speed Transmission Slew Rate Control on Data Lanes
bits : 18 - 19 (2 bit)
FLPRXLPM : Forces LP Receiver in Low-Power Mode
bits : 22 - 22 (1 bit)
LPRXFT : Low-Power RX low-pass Filtering Tuning
bits : 25 - 26 (2 bit)
DSI Wrapper PHY Configuration Register 3
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCLKPREP : tCLK-PREPARE
bits : 0 - 7 (8 bit)
TCLKZEO : tCLK-ZERO
bits : 8 - 15 (8 bit)
THSPREP : tHS-PREPARE
bits : 16 - 23 (8 bit)
THSTRAIL : tHSTRAIL
bits : 24 - 31 (8 bit)
DSI_WPCR4
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THSZERO : tHS-ZERO
bits : 0 - 7 (8 bit)
TLPXD : tLPX for Data lanes
bits : 8 - 15 (8 bit)
THSEXIT : tHSEXIT
bits : 16 - 23 (8 bit)
TLPXC : tLPXC for Clock lane
bits : 24 - 31 (8 bit)
DSI Wrapper PHY Configuration Register 5
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THSZERO : tCLK-POST
bits : 0 - 7 (8 bit)
DSI Wrapper Regulator and PLL Control Register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLEN : PLL Enable
bits : 0 - 0 (1 bit)
NDIV : PLL Loop Division Factor
bits : 2 - 8 (7 bit)
IDF : PLL Input Division Factor
bits : 11 - 14 (4 bit)
ODF : PLL Output Division Factor
bits : 16 - 17 (2 bit)
REGEN : Regulator Enable
bits : 24 - 24 (1 bit)
DSI Host Video Null Packet Configuration Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NPSIZE : Null Packet Size
bits : 0 - 12 (13 bit)
DSI Host Video HSA Configuration Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSA : Horizontal Synchronism Active duration
bits : 0 - 11 (12 bit)
DSI Host Video HBP Configuration Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HBP : Horizontal Back-Porch duration
bits : 0 - 11 (12 bit)
DSI Host Video Line Configuration Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HLINE : Horizontal Line duration
bits : 0 - 14 (15 bit)
DSI Host Video VSA Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VSA : Vertical Synchronism Active duration
bits : 0 - 9 (10 bit)
DSI Host Video VBP Configuration Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBP : Vertical Back-Porch duration
bits : 0 - 9 (10 bit)
DSI Host Video VFP Configuration Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VFP : Vertical Front-Porch duration
bits : 0 - 9 (10 bit)
DSI Host Video VA Configuration Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VA : Vertical Active duration
bits : 0 - 13 (14 bit)
DSI Host LTDC Command Configuration Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDSIZE : Command Size
bits : 0 - 15 (16 bit)
DSI Host Command mode Configuration Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEARE : Tearing Effect Acknowledge Request Enable
bits : 0 - 0 (1 bit)
ARE : Acknowledge Request Enable
bits : 1 - 1 (1 bit)
GSW0TX : Generic Short Write Zero parameters Transmission
bits : 8 - 8 (1 bit)
GSW1TX : Generic Short Write One parameters Transmission
bits : 9 - 9 (1 bit)
GSW2TX : Generic Short Write Two parameters Transmission
bits : 10 - 10 (1 bit)
GSR0TX : Generic Short Read Zero parameters Transmission
bits : 11 - 11 (1 bit)
GSR1TX : Generic Short Read One parameters Transmission
bits : 12 - 12 (1 bit)
GSR2TX : Generic Short Read Two parameters Transmission
bits : 13 - 13 (1 bit)
GLWTX : Generic Long Write Transmission
bits : 14 - 14 (1 bit)
DSW0TX : DCS Short Write Zero parameter Transmission
bits : 16 - 16 (1 bit)
DSW1TX : DCS Short Read One parameter Transmission
bits : 17 - 17 (1 bit)
DSR0TX : DCS Short Read Zero parameter Transmission
bits : 18 - 18 (1 bit)
DLWTX : DCS Long Write Transmission
bits : 19 - 19 (1 bit)
MRDPS : Maximum Read Packet Size
bits : 24 - 24 (1 bit)
DSI Host Generic Header Configuration Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DT : Type
bits : 0 - 5 (6 bit)
VCID : Channel
bits : 6 - 7 (2 bit)
WCLSB : WordCount LSB
bits : 8 - 15 (8 bit)
WCMSB : WordCount MSB
bits : 16 - 23 (8 bit)
DSI Host Generic Payload Data Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA1 : Payload Byte 1
bits : 0 - 7 (8 bit)
DATA2 : Payload Byte 2
bits : 8 - 15 (8 bit)
DATA3 : Payload Byte 3
bits : 16 - 23 (8 bit)
DATA4 : Payload Byte 4
bits : 24 - 31 (8 bit)
DSI Host Generic Packet Status Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMDFE : Command FIFO Empty
bits : 0 - 0 (1 bit)
CMDFF : Command FIFO Full
bits : 1 - 1 (1 bit)
PWRFE : Payload Write FIFO Empty
bits : 2 - 2 (1 bit)
PWRFF : Payload Write FIFO Full
bits : 3 - 3 (1 bit)
PRDFE : Payload Read FIFO Empty
bits : 4 - 4 (1 bit)
PRDFF : Payload Read FIFO Full
bits : 5 - 5 (1 bit)
RCB : Read Command Busy
bits : 6 - 6 (1 bit)
DSI Host Timeout Counter Configuration Register 0
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPRX_TOCNT : Low-power Reception Timeout Counter
bits : 0 - 15 (16 bit)
HSTX_TOCNT : High-Speed Transmission Timeout Counter
bits : 16 - 31 (16 bit)
DSI Host Timeout Counter Configuration Register 1
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSRD_TOCNT : High-Speed Read Timeout Counter
bits : 0 - 15 (16 bit)
DSI HOST Clock Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXECKDIV : TX Escape Clock Division
bits : 0 - 7 (8 bit)
TOCKDIV : Timeout Clock Division
bits : 8 - 15 (8 bit)
DSI Host Timeout Counter Configuration Register 2
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPRD_TOCNT : Low-Power Read Timeout Counter
bits : 0 - 15 (16 bit)
DSI Host Timeout Counter Configuration Register 3
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSWR_TOCNT : High-Speed Write Timeout Counter
bits : 0 - 15 (16 bit)
PM : Presp mode
bits : 24 - 24 (1 bit)
DSI Host Timeout Counter Configuration Register 4
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSWR_TOCNT : Low-Power Write Timeout Counter
bits : 0 - 15 (16 bit)
DSI Host Timeout Counter Configuration Register 5
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTA_TOCNT : Bus-Turn-Around Timeout Counter
bits : 0 - 15 (16 bit)
DSI Host Clock Lane Configuration Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPCC : D-PHY Clock Control
bits : 0 - 0 (1 bit)
ACR : Automatic Clock lane Control
bits : 1 - 1 (1 bit)
DSI Host Clock Lane Timer Configuration Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LP2HS_TIME : Low-Power to High-Speed Time
bits : 0 - 9 (10 bit)
HS2LP_TIME : High-Speed to Low-Power Time
bits : 16 - 25 (10 bit)
DSI Host Data Lane Timer Configuration Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MRD_TIME : Maximum Read Time
bits : 0 - 14 (15 bit)
LP2HS_TIME : Low-Power To High-Speed Time
bits : 16 - 23 (8 bit)
HS2LP_TIME : High-Speed To Low-Power Time
bits : 24 - 31 (8 bit)
DSI Host PHY Control Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEN : Digital Enable
bits : 1 - 1 (1 bit)
CKE : Clock Enable
bits : 2 - 2 (1 bit)
DSI Host PHY Configuration Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NL : Number of Lanes
bits : 0 - 1 (2 bit)
SW_TIME : Stop Wait Time
bits : 8 - 15 (8 bit)
DSI Host PHY ULPS Control Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
URCL : ULPS Request on Clock Lane
bits : 0 - 0 (1 bit)
UECL : ULPS Exit on Clock Lane
bits : 1 - 1 (1 bit)
URDL : ULPS Request on Data Lane
bits : 2 - 2 (1 bit)
UEDL : ULPS Exit on Data Lane
bits : 3 - 3 (1 bit)
DSI Host PHY TX Triggers Configuration Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_TRIG : Transmission Trigger
bits : 0 - 3 (4 bit)
DSI Host PHY Status Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PD : PHY Direction
bits : 1 - 1 (1 bit)
PSSC : PHY Stop State Clock lane
bits : 2 - 2 (1 bit)
UANC : ULPS Active Not Clock lane
bits : 3 - 3 (1 bit)
PSS0 : PHY Stop State lane 0
bits : 4 - 4 (1 bit)
UAN0 : ULPS Active Not lane 1
bits : 5 - 5 (1 bit)
RUE0 : RX ULPS Escape lane 0
bits : 6 - 6 (1 bit)
PSS1 : PHY Stop State lane 1
bits : 7 - 7 (1 bit)
UAN1 : ULPS Active Not lane 1
bits : 8 - 8 (1 bit)
DSI Host Interrupt and Status Register 0
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AE0 : Acknowledge Error 0
bits : 0 - 0 (1 bit)
AE1 : Acknowledge Error 1
bits : 1 - 1 (1 bit)
AE2 : Acknowledge Error 2
bits : 2 - 2 (1 bit)
AE3 : Acknowledge Error 3
bits : 3 - 3 (1 bit)
AE4 : Acknowledge Error 4
bits : 4 - 4 (1 bit)
AE5 : Acknowledge Error 5
bits : 5 - 5 (1 bit)
AE6 : Acknowledge Error 6
bits : 6 - 6 (1 bit)
AE7 : Acknowledge Error 7
bits : 7 - 7 (1 bit)
AE8 : Acknowledge Error 8
bits : 8 - 8 (1 bit)
AE9 : Acknowledge Error 9
bits : 9 - 9 (1 bit)
AE10 : Acknowledge Error 10
bits : 10 - 10 (1 bit)
AE11 : Acknowledge Error 11
bits : 11 - 11 (1 bit)
AE12 : Acknowledge Error 12
bits : 12 - 12 (1 bit)
AE13 : Acknowledge Error 13
bits : 13 - 13 (1 bit)
AE14 : Acknowledge Error 14
bits : 14 - 14 (1 bit)
AE15 : Acknowledge Error 15
bits : 15 - 15 (1 bit)
PE0 : PHY Error 0
bits : 16 - 16 (1 bit)
PE1 : PHY Error 1
bits : 17 - 17 (1 bit)
PE2 : PHY Error 2
bits : 18 - 18 (1 bit)
PE3 : PHY Error 3
bits : 19 - 19 (1 bit)
PE4 : PHY Error 4
bits : 20 - 20 (1 bit)
DSI Host LTDC VCID Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VCID : Virtual Channel ID
bits : 0 - 1 (2 bit)
DSI Host Interrupt and Status Register 1
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TOHSTX : Timeout High-Speed Transmission
bits : 0 - 0 (1 bit)
TOLPRX : Timeout Low-Power Reception
bits : 1 - 1 (1 bit)
ECCSE : ECC Single-bit Error
bits : 2 - 2 (1 bit)
ECCME : ECC Multi-bit Error
bits : 3 - 3 (1 bit)
CRCE : CRC Error
bits : 4 - 4 (1 bit)
PSE : Packet Size Error
bits : 5 - 5 (1 bit)
EOTPE : EoTp Error
bits : 6 - 6 (1 bit)
LPWRE : LTDC Payload Write Error
bits : 7 - 7 (1 bit)
GCWRE : Generic Command Write Error
bits : 8 - 8 (1 bit)
GPWRE : Generic Payload Write Error
bits : 9 - 9 (1 bit)
GPTXE : Generic Payload Transmit Error
bits : 10 - 10 (1 bit)
GPRDE : Generic Payload Read Error
bits : 11 - 11 (1 bit)
GPRXE : Generic Payload Receive Error
bits : 12 - 12 (1 bit)
DSI Host Interrupt Enable Register 0
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AE0IE : Acknowledge Error 0 Interrupt Enable
bits : 0 - 0 (1 bit)
AE1IE : Acknowledge Error 1 Interrupt Enable
bits : 1 - 1 (1 bit)
AE2IE : Acknowledge Error 2 Interrupt Enable
bits : 2 - 2 (1 bit)
AE3IE : Acknowledge Error 3 Interrupt Enable
bits : 3 - 3 (1 bit)
AE4IE : Acknowledge Error 4 Interrupt Enable
bits : 4 - 4 (1 bit)
AE5IE : Acknowledge Error 5 Interrupt Enable
bits : 5 - 5 (1 bit)
AE6IE : Acknowledge Error 6 Interrupt Enable
bits : 6 - 6 (1 bit)
AE7IE : Acknowledge Error 7 Interrupt Enable
bits : 7 - 7 (1 bit)
AE8IE : Acknowledge Error 8 Interrupt Enable
bits : 8 - 8 (1 bit)
AE9IE : Acknowledge Error 9 Interrupt Enable
bits : 9 - 9 (1 bit)
AE10IE : Acknowledge Error 10 Interrupt Enable
bits : 10 - 10 (1 bit)
AE11IE : Acknowledge Error 11 Interrupt Enable
bits : 11 - 11 (1 bit)
AE12IE : Acknowledge Error 12 Interrupt Enable
bits : 12 - 12 (1 bit)
AE13IE : Acknowledge Error 13 Interrupt Enable
bits : 13 - 13 (1 bit)
AE14IE : Acknowledge Error 14 Interrupt Enable
bits : 14 - 14 (1 bit)
AE15IE : Acknowledge Error 15 Interrupt Enable
bits : 15 - 15 (1 bit)
PE0IE : PHY Error 0 Interrupt Enable
bits : 16 - 16 (1 bit)
PE1IE : PHY Error 1 Interrupt Enable
bits : 17 - 17 (1 bit)
PE2IE : PHY Error 2 Interrupt Enable
bits : 18 - 18 (1 bit)
PE3IE : PHY Error 3 Interrupt Enable
bits : 19 - 19 (1 bit)
PE4IE : PHY Error 4 Interrupt Enable
bits : 20 - 20 (1 bit)
DSI Host Interrupt Enable Register 1
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOHSTXIE : Timeout High-Speed Transmission Interrupt Enable
bits : 0 - 0 (1 bit)
TOLPRXIE : Timeout Low-Power Reception Interrupt Enable
bits : 1 - 1 (1 bit)
ECCSEIE : ECC Single-bit Error Interrupt Enable
bits : 2 - 2 (1 bit)
ECCMEIE : ECC Multi-bit Error Interrupt Enable
bits : 3 - 3 (1 bit)
CRCEIE : CRC Error Interrupt Enable
bits : 4 - 4 (1 bit)
PSEIE : Packet Size Error Interrupt Enable
bits : 5 - 5 (1 bit)
EOTPEIE : EoTp Error Interrupt Enable
bits : 6 - 6 (1 bit)
LPWREIE : LTDC Payload Write Error Interrupt Enable
bits : 7 - 7 (1 bit)
GCWREIE : Generic Command Write Error Interrupt Enable
bits : 8 - 8 (1 bit)
GPWREIE : Generic Payload Write Error Interrupt Enable
bits : 9 - 9 (1 bit)
GPTXEIE : Generic Payload Transmit Error Interrupt Enable
bits : 10 - 10 (1 bit)
GPRDEIE : Generic Payload Read Error Interrupt Enable
bits : 11 - 11 (1 bit)
GPRXEIE : Generic Payload Receive Error Interrupt Enable
bits : 12 - 12 (1 bit)
DSI Host Force Interrupt Register 0
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FAE0 : Force Acknowledge Error 0
bits : 0 - 0 (1 bit)
FAE1 : Force Acknowledge Error 1
bits : 1 - 1 (1 bit)
FAE2 : Force Acknowledge Error 2
bits : 2 - 2 (1 bit)
FAE3 : Force Acknowledge Error 3
bits : 3 - 3 (1 bit)
FAE4 : Force Acknowledge Error 4
bits : 4 - 4 (1 bit)
FAE5 : Force Acknowledge Error 5
bits : 5 - 5 (1 bit)
FAE6 : Force Acknowledge Error 6
bits : 6 - 6 (1 bit)
FAE7 : Force Acknowledge Error 7
bits : 7 - 7 (1 bit)
FAE8 : Force Acknowledge Error 8
bits : 8 - 8 (1 bit)
FAE9 : Force Acknowledge Error 9
bits : 9 - 9 (1 bit)
FAE10 : Force Acknowledge Error 10
bits : 10 - 10 (1 bit)
FAE11 : Force Acknowledge Error 11
bits : 11 - 11 (1 bit)
FAE12 : Force Acknowledge Error 12
bits : 12 - 12 (1 bit)
FAE13 : Force Acknowledge Error 13
bits : 13 - 13 (1 bit)
FAE14 : Force Acknowledge Error 14
bits : 14 - 14 (1 bit)
FAE15 : Force Acknowledge Error 15
bits : 15 - 15 (1 bit)
FPE0 : Force PHY Error 0
bits : 16 - 16 (1 bit)
FPE1 : Force PHY Error 1
bits : 17 - 17 (1 bit)
FPE2 : Force PHY Error 2
bits : 18 - 18 (1 bit)
FPE3 : Force PHY Error 3
bits : 19 - 19 (1 bit)
FPE4 : Force PHY Error 4
bits : 20 - 20 (1 bit)
DSI Host Force Interrupt Register 1
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FTOHSTX : Force Timeout High-Speed Transmission
bits : 0 - 0 (1 bit)
FTOLPRX : Force Timeout Low-Power Reception
bits : 1 - 1 (1 bit)
FECCSE : Force ECC Single-bit Error
bits : 2 - 2 (1 bit)
FECCME : Force ECC Multi-bit Error
bits : 3 - 3 (1 bit)
FCRCE : Force CRC Error
bits : 4 - 4 (1 bit)
FPSE : Force Packet Size Error
bits : 5 - 5 (1 bit)
FEOTPE : Force EoTp Error
bits : 6 - 6 (1 bit)
FLPWRE : Force LTDC Payload Write Error
bits : 7 - 7 (1 bit)
FGCWRE : Force Generic Command Write Error
bits : 8 - 8 (1 bit)
FGPWRE : Force Generic Payload Write Error
bits : 9 - 9 (1 bit)
FGPTXE : Force Generic Payload Transmit Error
bits : 10 - 10 (1 bit)
FGPRDE : Force Generic Payload Read Error
bits : 11 - 11 (1 bit)
FGPRXE : Force Generic Payload Receive Error
bits : 12 - 12 (1 bit)
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