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address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
USBPHYC PLL1 control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL1EN : Enable the PLL1 inside PHY
bits : 0 - 0 (1 bit)
PLL1SEL : : Controls the PHY PLL1 input clock frequency selection
bits : 1 - 3 (3 bit)
USBPHYC LDO control and status register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDO_USED : Indicates the presence of the LDO in the chip
bits : 0 - 0 (1 bit)
access : read-only
LDO_STATUS : Monitors the status of the PHY's LDO
bits : 1 - 1 (1 bit)
access : read-only
LDO_DISABLE : Controls disable of the High Speed PHY's LDO
bits : 2 - 2 (1 bit)
access : read-write
USBPHYC tuning control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INCURREN : Controls the current boosting function
bits : 0 - 0 (1 bit)
INCURRINT : Controls PHY current boosting
bits : 1 - 1 (1 bit)
LFSCAPEN : : Enables the Low Full Speed feedback capacitor
bits : 2 - 2 (1 bit)
HSDRVSLEW : Controls the HS driver slew rate
bits : 3 - 3 (1 bit)
HSDRVDCCUR : Decreases the HS driver DC level
bits : 4 - 4 (1 bit)
HSDRVDCLEV : Increases the HS Driver DC level. Not applicable during the HS Test J and Test K data transfer
bits : 5 - 5 (1 bit)
HSDRVCURINCR : Enable the HS driver current increase feature
bits : 6 - 6 (1 bit)
FSDRVRFADJ : Tuning pin to adjust the full speed rise/fall time
bits : 7 - 7 (1 bit)
HSDRVRFRED : High Speed rise-fall reduction enable
bits : 8 - 8 (1 bit)
HSDRVCHKITRM : HS Driver current trimming pins for choke compensation
bits : 9 - 12 (4 bit)
HSDRVCHKZTRM : Controls the PHY bus HS driver impedance tuning for choke compensation
bits : 13 - 14 (2 bit)
SQLCHCTL : Adjust the squelch DC threshold value
bits : 15 - 16 (2 bit)
HDRXGNEQEN : Enables the HS Rx Gain Equalizer
bits : 17 - 17 (1 bit)
STAGSEL : HS Tx staggering enable
bits : 18 - 18 (1 bit)
HSFALLPREEM : HS Fall time control of single ended signals during pre-emphasis
bits : 19 - 19 (1 bit)
HSRXOFF : : HS Receiver Offset adjustment
bits : 20 - 21 (2 bit)
SHTCCTCTLPROT : Enables the short circuit protection circuitry in LS/FS driver
bits : 22 - 22 (1 bit)
SQLBYP : This pin is used to bypass the squelch inter-locking circuitry
bits : 23 - 23 (1 bit)
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