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address_offset : 0x0 Bytes (0x0)
size : 0x6 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection : not protected
AGT Counter Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGT : 16bit counter and reload registerNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, the 16-bit counter is forcibly stopped and set to FFFFH.
bits : 0 - 14 (15 bit)
access : read-write
AGT Compare Match A Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGTCMA : AGT Compare Match A data is stored.NOTE : When 1 is written to the TSTOP bit in the AGTCRn register, set to FFFFH
bits : 0 - 14 (15 bit)
access : read-write
AGT Compare Match B Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGTCMB : AGT Compare Match B data is stored.NOTE : When 1 is written to the TSTOP bit in the AGTCR register, set to FFFFH
bits : 0 - 14 (15 bit)
access : read-write
AGT Control Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSTART : AGT count start
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Count stops
#1 : 1
Count starts.
End of enumeration elements list.
TCSTF : AGT count status flag
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
Count stops
#1 : 1
Count in progress.
End of enumeration elements list.
TSTOP : AGT count forced stop
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : 0
Writing is invalid
#1 : 1
The count is forcibly stopped.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-write
TEDGF : Active edge judgment flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
No active edge received
#1 : 1
Active edge received.
End of enumeration elements list.
TUNDF : Underflow flag
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
No match
#1 : 1
Match.
End of enumeration elements list.
TCMAF : Compare match A flag
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
No match
#1 : 1
Match.
End of enumeration elements list.
TCMBF : Compare match B flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
No match
#1 : 1
Match.
End of enumeration elements list.
AGT Mode Register 1
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMOD : Operating mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
Timer mode
#001 : 001
Pulse output mode
#010 : 010
Event counter mode
#011 : 011
Pulse width measurement mode
#100 : 100
Pulse period measurement mode.
: others
settings are prohibited
End of enumeration elements list.
TEDGPL : Edge polarity
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Single-edge
#1 : 1
Both-edge.
End of enumeration elements list.
TCK : Count source
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : 000
PCLKB
#001 : 001
PCLKB/8
#011 : 011
PCLKB/2
#100 : 100
Divided clock AGTLCLK specified by CKS[2:0] bits in the AGTMR2 register
#101 : 101
Underflow event signal from AGT0*6
#110 : 110
Divided clock AGTSCLK specified by CKS[2:0] bits in the AGTMR2 register.
: others
settings are prohibited.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write
AGT Mode Register 2
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKS : AGTLCLK/AGTSCLK count source clock frequency division ratio
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
1/1
#001 : 001
1/2
#010 : 010
1/4
#011 : 011
1/8
#100 : 100
1/16
#101 : 101
1/32
#110 : 110
1/64
#111 : 111
1/128.
End of enumeration elements list.
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 3 - 5 (3 bit)
access : read-write
LPM : Low Power Mode
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal mode
#1 : 1
Low Power mode
End of enumeration elements list.
AGT I/O Control Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEDGSEL : I/O polarity switchFunction varies depending on the operating mode.
bits : 0 - -1 (0 bit)
access : read-write
TOE : AGTOn output enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
AGTOn output disabled
#1 : 1
AGTOn output enabled.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-write
TIPF : Input filter
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
No filter
#01 : 01
Filter sampled at PCLKB
#10 : 10
Filter sampled at PCLKB/8
#11 : 11
Filter sampled at PCLKB/32
End of enumeration elements list.
TIOGT : Count control
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
Event is always counted
#01 : 01
Event is counted during polarity period specified for AGTEEn.
: others
settings are prohibited.
End of enumeration elements list.
AGT Event Pin Select Register
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EEPS : AGTEE polarty selection
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
An event is counted during the low-level period
#1 : 1
An event is counted during the high-level period
End of enumeration elements list.
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 3 - 6 (4 bit)
access : read-write
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 3 - 6 (4 bit)
access : read-write
AGT Compare Match Function Select Register
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCMEA : Compare match A register enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable compare match A register
#1 : 1
Enable compare match A register
End of enumeration elements list.
TOEA : AGTOA output enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
AGTOA output disabled (port)
#1 : 1
AGTOA output enabled
End of enumeration elements list.
TOPOLA : AGTOA polarity select
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
AGTOA Output is started at low
#1 : 1
AGTOA Output is started at high
End of enumeration elements list.
TCMEB : Compare match B register enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable compare match B register
#1 : 1
Enable compare match B register
End of enumeration elements list.
TOEB : AGTOB output enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
AGTOB output disabled (port)
#1 : 1
AGTOB output enabled
End of enumeration elements list.
TOPOLB : AGTOB polarity select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
AGTOB Output is started at low
#1 : 1
AGTOB Output is started at high
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write
AGT Pin Select Register
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : AGTIO pin select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Select the AGTIOn except for below pins
#01 : 01
Setting prohibited
#10 : 10
Select the P402/AGTIOn. P402/AGTIOn is input only. It is not possible to output
#11 : 11
Select the P403/AGTIOn. P403/AGTIOn is input only. It is not possible to output
End of enumeration elements list.
TIES : AGTIO input enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
External event input is disabled during Software Standby mode
#1 : 1
External event input is enabled during Software Standby mode.
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 5 - 6 (2 bit)
access : read-write
Reserved : These bits are read as 000. The write value should be 000.
bits : 5 - 6 (2 bit)
access : read-write
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