\n
address_offset : 0x100 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x104 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x11C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
Flash Cache Enable Register
address_offset : 0x100 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCACHEEN : FCACHE Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
FCACHE is disabled
#1 : 1
FCACHE is enabled
End of enumeration elements list.
Reserved : These bits are read as 000000000000000. The write value should be 000000000000000.
bits : 1 - 14 (14 bit)
access : read-write
Flash Cache Invalidate Register
address_offset : 0x104 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCACHEIV : FCACHE Invalidation
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
(Read)not in progress / (Write) no effect.
#1 : 1
(Read)in progress /(Write) Starting Cache Invalidation
End of enumeration elements list.
Reserved : These bits are read as 000000000000000. The write value should be 000000000000000.
bits : 1 - 14 (14 bit)
access : read-write
Flash Wait Cycle Register
address_offset : 0x11C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLWT : These bits represent the ratio of the CPU clock period to the Flash memory access time.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
zero wait
: others
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 3 - 6 (4 bit)
access : read-write
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