Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x140 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x130 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1A0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x280 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x300 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x120 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
IRQ Control Register %s
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
NMI Pin Interrupt Control Register
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMIMD : NMI Detection Set
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Falling edge
#1 : 1
Rising edge
End of enumeration elements list.
NFCLKSEL : NMI Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
NFLTEN : NMI Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled.
#1 : 1
Digital filter is enabled.
End of enumeration elements list.
Non-Maskable Interrupt Enable Register
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IWDTEN : IWDT Underflow/Refresh Error Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
WDTEN : WDT Underflow/Refresh Error Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
LVD1EN : Voltage-Monitoring 1 Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
LVD2EN : Voltage-Monitoring 2 Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
VBATTEN : VBATT monitor Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
OSTEN : Oscillation Stop Detection Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
NMIEN : NMI Pin Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
RPEEN : RAM Parity Error Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
RECCEN : RAM ECC Error Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
BUSSEN : MPU Bus Slave Error Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
BUSMEN : MPU Bus Master Error Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
SPEEN : CPU Stack pointer monitor Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write
Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write
Non-Maskable Interrupt Status Clear Register
address_offset : 0x130 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IWDTCLR : IWDT Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.IWDTST flag.
End of enumeration elements list.
WDTCLR : WDT Clear
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.WDTST flag.
End of enumeration elements list.
LVD1CLR : LVD1 Clear
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.LVD1ST flag.
End of enumeration elements list.
LVD2CLR : LVD2 Clear
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.LVD2ST flag.
End of enumeration elements list.
VBATTCLR : VBATT Clear
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.VBATTST flag.
End of enumeration elements list.
OSTCLR : OST Clear
bits : 6 - 5 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.OSTST flag.
End of enumeration elements list.
NMICLR : NMI Clear
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.NMIST flag.
End of enumeration elements list.
RPECLR : SRAM Parity Error Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.RPEST flag.
End of enumeration elements list.
RECCCLR : SRAM ECC Error Clear
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.RECCST flag.
End of enumeration elements list.
BUSSCLR : Bus Slave Error Clear
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.BUSSST flag.
End of enumeration elements list.
BUSMCLR : Bus Master Error Clear
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.BUSMST flag.
End of enumeration elements list.
SPECLR : CPU Stack Pointer Monitor Interrupt Clear
bits : 12 - 11 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Clear the NMISR.SPEST flag.
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write
Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write
Non-Maskable Interrupt Status Register
address_offset : 0x140 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IWDTST : IWDT Underflow/Refresh Error Status Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
WDTST : WDT Underflow/Refresh Error Status Flag
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
LVD1ST : Voltage-Monitoring 1 Interrupt Status Flag
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
LVD2ST : Voltage-Monitoring 2 Interrupt Status Flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
VBATTST : VBATT monitor Interrupt Status Flag
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
OSTST : Oscillation Stop Detection Interrupt Status Flag
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested for main oscillation stop
#1 : 1
Interrupt requested for main oscillation stop.
End of enumeration elements list.
NMIST : NMI Status Flag
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
RPEST : RAM Parity Error Interrupt Status Flag
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
RECCST : RAM ECC Error Interrupt Status Flag
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
BUSSST : MPU Bus Slave Error Interrupt Status Flag
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
BUSMST : MPU Bus Master Error Interrupt Status Flag
bits : 11 - 10 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
SPEST : CPU Stack pointer monitor Interrupt Status Flag
bits : 12 - 11 (0 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not requested
#1 : 1
Interrupt requested.
End of enumeration elements list.
Reserved : These bits are read as 000.
bits : 13 - 14 (2 bit)
access : read-only
Reserved : These bits are read as 000.
bits : 13 - 14 (2 bit)
access : read-only
Wake Up Interrupt Enable Register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQWUPEN0 : IRQ0 interrupt S/W standby returns enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ0 interrupt is disabled
#1 : 1
S/W standby returns by IRQ0 interrupt is enabled
End of enumeration elements list.
IRQWUPEN1 : IRQ1 interrupt S/W standby returns enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ1 interrupt is disabled
#1 : 1
S/W standby returns by IRQ1 interrupt is enabled
End of enumeration elements list.
IRQWUPEN2 : IRQ2 interrupt S/W standby returns enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ2 interrupt is disabled
#1 : 1
S/W standby returns by IRQ2 interrupt is enabled
End of enumeration elements list.
IRQWUPEN3 : IRQ3 interrupt S/W standby returns enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ3 interrupt is disabled
#1 : 1
S/W standby returns by IRQ3 interrupt is enabled
End of enumeration elements list.
IRQWUPEN4 : IRQ4 interrupt S/W standby returns enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ4 interrupt is disabled
#1 : 1
S/W standby returns by IRQ4 interrupt is enabled
End of enumeration elements list.
IRQWUPEN5 : IRQ5 interrupt S/W standby returns enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ5 interrupt is disabled
#1 : 1
S/W standby returns by IRQ5 interrupt is enabled
End of enumeration elements list.
IRQWUPEN6 : IRQ6 interrupt S/W standby returns enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ6 interrupt is disabled
#1 : 1
S/W standby returns by IRQ6 interrupt is enabled
End of enumeration elements list.
IRQWUPEN7 : IRQ7 interrupt S/W standby returns enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ7 interrupt is disabled
#1 : 1
S/W standby returns by IRQ7 interrupt is enabled
End of enumeration elements list.
IRQWUPEN8 : IRQ8 interrupt S/W standby returns enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ8 interrupt is disabled
#1 : 1
S/W standby returns by IRQ8 interrupt is enabled
End of enumeration elements list.
IRQWUPEN9 : IRQ9 interrupt S/W standby returns enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ9 interrupt is disabled
#1 : 1
S/W standby returns by IRQ9 interrupt is enabled
End of enumeration elements list.
IRQWUPEN10 : IRQ10 interrupt S/W standby returns enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ10 interrupt is disabled
#1 : 1
S/W standby returns by IRQ10 interrupt is enabled
End of enumeration elements list.
IRQWUPEN11 : IRQ11 interrupt S/W standby returns enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ11 interrupt is disabled
#1 : 1
S/W standby returns by IRQ11 interrupt is enabled
End of enumeration elements list.
IRQWUPEN12 : IRQ12 interrupt S/W standby returns enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ12 interrupt is disabled
#1 : 1
S/W standby returns by IRQ12 interrupt is enabled
End of enumeration elements list.
IRQWUPEN13 : IRQ13 interrupt S/W standby returns enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ13 interrupt is disabled
#1 : 1
S/W standby returns by IRQ13 interrupt is enabled
End of enumeration elements list.
IRQWUPEN14 : IRQ14 interrupt S/W standby returns enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ14 interrupt is disabled
#1 : 1
S/W standby returns by IRQ14 interrupt is enabled
End of enumeration elements list.
IRQWUPEN15 : IRQ15 interrupt S/W standby returns enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IRQ15 interrupt is disabled
#1 : 1
S/W standby returns by IRQ15 interrupt is enabled
End of enumeration elements list.
IWDTWUPEN : IWDT interrupt S/W standby returns enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IWDT interrupt is disabled
#1 : 1
S/W standby returns by IWDT interrupt is enabled
End of enumeration elements list.
KEYWUPEN : Key interrupt S/W standby returns enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by KEY interrupt is disabled
#1 : 1
S/W standby returns by KEY interrupt is enabled
End of enumeration elements list.
LVD1WUPEN : LVD1 interrupt S/W standby returns enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by LVD1 interrupt is disabled
#1 : 1
S/W standby returns by LVD1 interrupt is enabled
End of enumeration elements list.
LVD2WUPEN : LVD2 interrupt S/W standby returns enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by LVD2 interrupt is disabled
#1 : 1
S/W standby returns by LVD2 interrupt is enabled
End of enumeration elements list.
VBATTWUPEN : VBATT monitor interrupt S/W standby returns enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by VBATT monitor interrupt is disabled
#1 : 1
S/W standby returns by VBATT monitor interrupt is enabled
End of enumeration elements list.
ACMPLP0WUPEN : ACMPLP0 interrupt S/W standby returns enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by ACMPLP0 interrupt is disabled
#1 : 1
S/W standby returns by ACMPLP0 interrupt is enabled
End of enumeration elements list.
RTCALMWUPEN : RTC alarm interrupt S/W standby returns enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by RTC alarm interrupt is disabled
#1 : 1
S/W standby returns by RTC alarm interrupt is enabled
End of enumeration elements list.
RTCPRDWUPEN : RCT period interrupt S/W standby returns enable
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by RTC period interrupt is disabled
#1 : 1
S/W standby returns by RTC period interrupt is enabled
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 26 - 25 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 26 - 25 (0 bit)
access : read-write
USBFSWUPEN : USBFS interrupt S/W standby returns enable
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by USBFS interrupt is disabled
#1 : 1
S/W standby returns by USBFS interrupt is enabled
End of enumeration elements list.
AGT1UDWUPEN : AGT1 underflow interrupt S/W standby returns enable
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by AGT1 underflow interrupt is disabled
#1 : 1
S/W standby returns by AGT1 underflow interrupt is enabled
End of enumeration elements list.
AGT1CAWUPEN : AGT1 compare match A interrupt S/W standby returns enable
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by AGT1 compare match A interrupt is disabled
#1 : 1
S/W standby returns by AGT1 compare match A interrupt is enabled
End of enumeration elements list.
AGT1CBWUPEN : AGT1 compare match B interrupt S/W standby returns enable
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by AGT1 compare match B interrupt is disabled
#1 : 1
S/W standby returns by AGT1 compare match B interrupt is enabled
End of enumeration elements list.
IIC0WUPEN : IIC0 address match interrupt S/W standby returns enable
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : 0
S/W standby returns by IIC0 address match interrupt is disabled
#1 : 1
S/W standby returns by IIC0 address match interrupt is enabled
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
Snooze Event Link Setting Register
address_offset : 0x200 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SELS : SYS Event Link Select
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
0x015 : 0x015
DTC_COMPLETE
0x02D : 0x02D
ADC140_WCMPM
0x02E : 0x02E
ADC140_WCMPUM
0x048 : 0x048
CTSU_CTSUFN
0x04A : 0x04A
DOC_DOPCI
0x0B0 : 0x0B0
SCI0_AM
0x0B1 : 0x0B1
SCI0_RXI_OR_ERI
: others
Settings prohibited.
End of enumeration elements list.
Reserved : These bits are read as 00000000. The write value should be 00000000.
bits : 8 - 14 (7 bit)
access : read-write
DMAC Event Link Setting Register %s
address_offset : 0x280 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : Event selection to DMAC Start request
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected.
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 00000000. The write value should be 00000000.
bits : 8 - 14 (7 bit)
access : read-write
DMAC Event Link Setting Register %s
address_offset : 0x284 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : Event selection to DMAC Start request
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected.
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 00000000. The write value should be 00000000.
bits : 8 - 14 (7 bit)
access : read-write
DMAC Event Link Setting Register %s
address_offset : 0x288 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : Event selection to DMAC Start request
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected.
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 00000000. The write value should be 00000000.
bits : 8 - 14 (7 bit)
access : read-write
DMAC Event Link Setting Register %s
address_offset : 0x28C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELS : Event selection to DMAC Start request
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected.
: others
See Event Table
End of enumeration elements list.
Reserved : These bits are read as 00000000. The write value should be 00000000.
bits : 8 - 14 (7 bit)
access : read-write
IRQ Control Register %s
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
ICU Event Link Setting Register %s
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IELS : ICU Event selection to NVICSet the number for the event signal to be linked .
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x000 : 0x000
Nothing is selected
: others
See Event Table
End of enumeration elements list.
IR : Interrupt Status Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated
#1 : 1
An interrupt request is generated ( 1 write to the IR bit is prohibited. )
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 17 - 22 (6 bit)
access : read-write
DTCE : DTC Activation Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTC activation is disabled
#1 : 1
DTC activation is enabled
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
IRQ Control Register %s
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQMD : IRQ Detection Sense Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Falling edge
#01 : 01
Rising edge
#10 : 10
Rising and falling edges
#11 : 11
Low level
End of enumeration elements list.
FCLKSEL : IRQ Digital Filter Sampling Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLKB
#01 : 01
PCLKB/8
#10 : 10
PCLKB/32
#11 : 11
PCLKB/64
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
FLTEN : IRQ Digital Filter Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter disabled.
#1 : 1
Digital filter enabled.
End of enumeration elements list.
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