Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x2 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x802 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80A Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x812 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x880 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1000 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1100 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1108 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1114 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1128 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1130 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1800 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1804 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected
Master Bus Control Register %s
address_offset : 0x1000 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reserved : These bits are read as 000000000000000. The write value should be 000000000000000.
bits : 0 - 13 (14 bit)
access : read-write
IERES : Ignore Error Responses
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
A bus error is reported
#1 : 1
A bus error is not reported.
End of enumeration elements list.
Master Bus Control Register %s
address_offset : 0x1004 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reserved : These bits are read as 000000000000000. The write value should be 000000000000000.
bits : 0 - 13 (14 bit)
access : read-write
IERES : Ignore Error Responses
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
A bus error is reported
#1 : 1
A bus error is not reported.
End of enumeration elements list.
Master Bus Control Register %s
address_offset : 0x1008 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reserved : These bits are read as 000000000000000. The write value should be 000000000000000.
bits : 0 - 13 (14 bit)
access : read-write
IERES : Ignore Error Responses
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
A bus error is reported
#1 : 1
A bus error is not reported.
End of enumeration elements list.
Master Bus Control Register %s
address_offset : 0x100C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reserved : These bits are read as 000000000000000. The write value should be 000000000000000.
bits : 0 - 13 (14 bit)
access : read-write
IERES : Ignore Error Responses
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
A bus error is reported
#1 : 1
A bus error is not reported.
End of enumeration elements list.
Slave Bus Control Register FLI
address_offset : 0x1100 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
fixed priority
#01 : 01
round-robin
: others
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Slave Bus Control Register %s
address_offset : 0x1108 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
fixed priority
#01 : 01
round-robin
: others
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Slave Bus Control Register %s
address_offset : 0x110C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
fixed priority
#01 : 01
round-robin
: others
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Slave Bus Control Register %s
address_offset : 0x1114 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
fixed priority
#01 : 01
round-robin
: others
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Slave Bus Control Register %s
address_offset : 0x1118 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
fixed priority
#01 : 01
round-robin
: others
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Slave Bus Control Register %s
address_offset : 0x111C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
fixed priority
#01 : 01
round-robin
: others
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Slave Bus Control Register %s
address_offset : 0x1120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
fixed priority
#01 : 01
round-robin
: others
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Slave Bus Control Register P6B
address_offset : 0x1128 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
fixed priority
#01 : 01
round-robin
: others
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Slave Bus Control Register %s
address_offset : 0x1130 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
fixed priority
#01 : 01
round-robin
: others
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Slave Bus Control Register %s
address_offset : 0x1134 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
fixed priority
#01 : 01
round-robin
: others
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Slave Bus Control Register %s
address_offset : 0x1138 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
fixed priority
#01 : 01
round-robin
: others
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
Reserved : These bits are read as 0000000000. The write value should be 0000000000.
bits : 6 - 14 (9 bit)
access : read-write
CS%s Mode Register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Byte strobe mode
#1 : 1
Single write strobe mode
End of enumeration elements list.
EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write
PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PRDMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal access compatible mode
#1 : 1
External data read continuous assertion mode
End of enumeration elements list.
CS%s Wait Control Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of CSPWWAIT clock cycle is inserted.
End of enumeration elements list.
CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of CSPRWAIT clock cycle is inserted.
End of enumeration elements list.
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write
CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x00 : 0x00
No wait is inserted.
: others
Wait with a length of CSWWAIT clock cycle is inserted.
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 21 - 22 (2 bit)
access : read-write
CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0x00 : 0x00
No wait is inserted.
: others
Wait with a length of CSRWAIT clock cycle is inserted.
End of enumeration elements list.
CS%s Wait Control Register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of CSROFF clock cycle is inserted.
End of enumeration elements list.
CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of CSWOFF clock cycle is inserted.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write
WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of WDOFF clock cycle is inserted.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 11 - 10 (0 bit)
access : read-write
AWAIT : Address Cycle Wait Select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of AWAIT clock cycle is inserted.
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 14 - 14 (1 bit)
access : read-write
RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of RDON clock cycle is inserted.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 19 - 18 (0 bit)
access : read-write
WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of WRON clock cycle is inserted.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 23 - 22 (0 bit)
access : read-write
WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of WDON clock cycle is inserted.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 27 - 26 (0 bit)
access : read-write
CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of CSON clock cycle is inserted.
End of enumeration elements list.
Bus Error Address Register %s
address_offset : 0x1800 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BERAD : Bus Error AddressWhen a bus error occurs, It stores an error address.
bits : 0 - 30 (31 bit)
access : read-only
Bus Error Status Register %s
address_offset : 0x1804 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACCSTST : Error Access StatusThe status at the time of the error
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Read access
#1 : 1
Write Access
End of enumeration elements list.
Reserved : These bits are read as 000000.
bits : 1 - 5 (5 bit)
access : read-only
ERRSTAT : Bus Error StatusWhen bus error assert, error flag occurs.
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
No bus error occurred
#1 : 1
Bus error occurred.
End of enumeration elements list.
Bus Error Address Register %s
address_offset : 0x1810 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BERAD : Bus Error AddressWhen a bus error occurs, It stores an error address.
bits : 0 - 30 (31 bit)
access : read-only
Bus Error Status Register %s
address_offset : 0x1814 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACCSTST : Error Access StatusThe status at the time of the error
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Read access
#1 : 1
Write Access
End of enumeration elements list.
Reserved : These bits are read as 000000.
bits : 1 - 5 (5 bit)
access : read-only
ERRSTAT : Bus Error StatusWhen bus error assert, error flag occurs.
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
No bus error occurred
#1 : 1
Bus error occurred.
End of enumeration elements list.
Bus Error Address Register %s
address_offset : 0x1820 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BERAD : Bus Error AddressWhen a bus error occurs, It stores an error address.
bits : 0 - 30 (31 bit)
access : read-only
Bus Error Status Register %s
address_offset : 0x1824 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACCSTST : Error Access StatusThe status at the time of the error
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Read access
#1 : 1
Write Access
End of enumeration elements list.
Reserved : These bits are read as 000000.
bits : 1 - 5 (5 bit)
access : read-only
ERRSTAT : Bus Error StatusWhen bus error assert, error flag occurs.
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
No bus error occurred
#1 : 1
Bus error occurred.
End of enumeration elements list.
Bus Error Address Register %s
address_offset : 0x1830 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BERAD : Bus Error AddressWhen a bus error occurs, It stores an error address.
bits : 0 - 30 (31 bit)
access : read-only
Bus Error Status Register %s
address_offset : 0x1834 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACCSTST : Error Access StatusThe status at the time of the error
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
Read access
#1 : 1
Write Access
End of enumeration elements list.
Reserved : These bits are read as 000000.
bits : 1 - 5 (5 bit)
access : read-only
ERRSTAT : Bus Error StatusWhen bus error assert, error flag occurs.
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
No bus error occurred
#1 : 1
Bus error occurred.
End of enumeration elements list.
CS%s Mode Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Byte strobe mode
#1 : 1
Single write strobe mode
End of enumeration elements list.
EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write
PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PRDMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal access compatible mode
#1 : 1
External data read continuous assertion mode
End of enumeration elements list.
CS%s Mode Register
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Byte strobe mode
#1 : 1
Single write strobe mode
End of enumeration elements list.
EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write
PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PRDMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal access compatible mode
#1 : 1
External data read continuous assertion mode
End of enumeration elements list.
CS%s Wait Control Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of CSPWWAIT clock cycle is inserted.
End of enumeration elements list.
CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of CSPRWAIT clock cycle is inserted.
End of enumeration elements list.
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write
CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x00 : 0x00
No wait is inserted.
: others
Wait with a length of CSWWAIT clock cycle is inserted.
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 21 - 22 (2 bit)
access : read-write
CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0x00 : 0x00
No wait is inserted.
: others
Wait with a length of CSRWAIT clock cycle is inserted.
End of enumeration elements list.
CS%s Wait Control Register 2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of CSROFF clock cycle is inserted.
End of enumeration elements list.
CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of CSWOFF clock cycle is inserted.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write
WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of WDOFF clock cycle is inserted.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 11 - 10 (0 bit)
access : read-write
AWAIT : Address Cycle Wait Select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of AWAIT clock cycle is inserted.
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 14 - 14 (1 bit)
access : read-write
RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of RDON clock cycle is inserted.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 19 - 18 (0 bit)
access : read-write
WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of WRON clock cycle is inserted.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 23 - 22 (0 bit)
access : read-write
WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of WDON clock cycle is inserted.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 27 - 26 (0 bit)
access : read-write
CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of CSON clock cycle is inserted.
End of enumeration elements list.
CS%s Mode Register
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Byte strobe mode
#1 : 1
Single write strobe mode
End of enumeration elements list.
EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write
PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PRDMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal access compatible mode
#1 : 1
External data read continuous assertion mode
End of enumeration elements list.
CS%s Wait Control Register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of CSPWWAIT clock cycle is inserted.
End of enumeration elements list.
CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of CSPRWAIT clock cycle is inserted.
End of enumeration elements list.
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write
CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x00 : 0x00
No wait is inserted.
: others
Wait with a length of CSWWAIT clock cycle is inserted.
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 21 - 22 (2 bit)
access : read-write
CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0x00 : 0x00
No wait is inserted.
: others
Wait with a length of CSRWAIT clock cycle is inserted.
End of enumeration elements list.
CS%s Wait Control Register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of CSROFF clock cycle is inserted.
End of enumeration elements list.
CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of CSWOFF clock cycle is inserted.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write
WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of WDOFF clock cycle is inserted.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 11 - 10 (0 bit)
access : read-write
AWAIT : Address Cycle Wait Select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of AWAIT clock cycle is inserted.
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 14 - 14 (1 bit)
access : read-write
RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of RDON clock cycle is inserted.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 19 - 18 (0 bit)
access : read-write
WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of WRON clock cycle is inserted.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 23 - 22 (0 bit)
access : read-write
WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of WDON clock cycle is inserted.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 27 - 26 (0 bit)
access : read-write
CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of CSON clock cycle is inserted.
End of enumeration elements list.
CS%s Wait Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of CSPWWAIT clock cycle is inserted.
End of enumeration elements list.
CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of CSPRWAIT clock cycle is inserted.
End of enumeration elements list.
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write
CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x00 : 0x00
No wait is inserted.
: others
Wait with a length of CSWWAIT clock cycle is inserted.
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 21 - 22 (2 bit)
access : read-write
CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0x00 : 0x00
No wait is inserted.
: others
Wait with a length of CSRWAIT clock cycle is inserted.
End of enumeration elements list.
CS%s Wait Control Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of CSROFF clock cycle is inserted.
End of enumeration elements list.
CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of CSWOFF clock cycle is inserted.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write
WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of WDOFF clock cycle is inserted.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 11 - 10 (0 bit)
access : read-write
AWAIT : Address Cycle Wait Select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of AWAIT clock cycle is inserted.
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 14 - 14 (1 bit)
access : read-write
RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of RDON clock cycle is inserted.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 19 - 18 (0 bit)
access : read-write
WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of WRON clock cycle is inserted.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 23 - 22 (0 bit)
access : read-write
WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of WDON clock cycle is inserted.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 27 - 26 (0 bit)
access : read-write
CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : 0x0
No wait is inserted.
: others
Wait with a length of CSON clock cycle is inserted.
End of enumeration elements list.
CS0 Control Register
address_offset : 0x802 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
16-bit bus space
#01 : 01
Setting prohibited
#10 : 10
8-bit bus space
#11 : 11
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Little Endian
#1 : 1
Big Endian
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 9 - 10 (2 bit)
access : read-write
MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Separate bus interface is selected for area 0.
#1 : 1
Address/data multiplexed I/O interface is selected for area 0.
End of enumeration elements list.
CS%s Recovery Cycle Register
address_offset : 0x80A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
No recovery cycle is inserted.
: others
RRCV recovery cycle is inserted.
End of enumeration elements list.
WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
No recovery cycle is inserted.
: others
WRCV recovery cycle is inserted.
End of enumeration elements list.
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write
CS%s Control Register
address_offset : 0x812 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
16-bit bus space
#01 : 01
Setting prohibited
#10 : 10
8-bit bus space
#11 : 11
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Little Endian
#1 : 1
Big Endian
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 9 - 10 (2 bit)
access : read-write
MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Separate bus interface is selected for area 0.
#1 : 1
Address/data multiplexed I/O interface is selected for area 0.
End of enumeration elements list.
CS%s Recovery Cycle Register
address_offset : 0x81A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
No recovery cycle is inserted.
: others
RRCV recovery cycle is inserted.
End of enumeration elements list.
WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
No recovery cycle is inserted.
: others
WRCV recovery cycle is inserted.
End of enumeration elements list.
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write
CS%s Control Register
address_offset : 0x822 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
16-bit bus space
#01 : 01
Setting prohibited
#10 : 10
8-bit bus space
#11 : 11
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Little Endian
#1 : 1
Big Endian
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 9 - 10 (2 bit)
access : read-write
MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Separate bus interface is selected for area 0.
#1 : 1
Address/data multiplexed I/O interface is selected for area 0.
End of enumeration elements list.
CS%s Recovery Cycle Register
address_offset : 0x82A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
No recovery cycle is inserted.
: others
RRCV recovery cycle is inserted.
End of enumeration elements list.
WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
No recovery cycle is inserted.
: others
WRCV recovery cycle is inserted.
End of enumeration elements list.
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write
CS%s Control Register
address_offset : 0x832 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
16-bit bus space
#01 : 01
Setting prohibited
#10 : 10
8-bit bus space
#11 : 11
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Little Endian
#1 : 1
Big Endian
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 9 - 10 (2 bit)
access : read-write
MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Separate bus interface is selected for area 0.
#1 : 1
Address/data multiplexed I/O interface is selected for area 0.
End of enumeration elements list.
CS%s Recovery Cycle Register
address_offset : 0x83A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
No recovery cycle is inserted.
: others
RRCV recovery cycle is inserted.
End of enumeration elements list.
WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : 0x0
No recovery cycle is inserted.
: others
WRCV recovery cycle is inserted.
End of enumeration elements list.
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write
CS Recovery Cycle Insertion Enable Register
address_offset : 0x880 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECVEN0 : Separate Bus Recovery Cycle Insertion Enable 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled.
#1 : 1
Enabled.
End of enumeration elements list.
RECVEN1 : Separate Bus Recovery Cycle Insertion Enable 1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled.
#1 : 1
Enabled.
End of enumeration elements list.
RECVEN2 : Separate Bus Recovery Cycle Insertion Enable 2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled.
#1 : 1
Enabled.
End of enumeration elements list.
RECVEN3 : Separate Bus Recovery Cycle Insertion Enable 3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled.
#1 : 1
Enabled.
End of enumeration elements list.
RECVEN4 : Separate Bus Recovery Cycle Insertion Enable 4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled.
#1 : 1
Enabled.
End of enumeration elements list.
RECVEN5 : Separate Bus Recovery Cycle Insertion Enable 5
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled.
#1 : 1
Enabled.
End of enumeration elements list.
RECVEN6 : Separate Bus Recovery Cycle Insertion Enable 6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled.
#1 : 1
Enabled.
End of enumeration elements list.
RECVEN7 : Separate Bus Recovery Cycle Insertion Enable 7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled.
#1 : 1
Enabled.
End of enumeration elements list.
RECVENM0 : Multiplexed Bus Recovery Cycle Insertion Enable 0
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Recovery cycle insertion is disabled.
#1 : 1
Recovery cycle insertion is enabled.
End of enumeration elements list.
RECVENM1 : Multiplexed Bus Recovery Cycle Insertion Enable 1
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Recovery cycle insertion is disabled.
#1 : 1
Recovery cycle insertion is enabled.
End of enumeration elements list.
RECVENM2 : Multiplexed Bus Recovery Cycle Insertion Enable 2
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Recovery cycle insertion is disabled.
#1 : 1
Recovery cycle insertion is enabled.
End of enumeration elements list.
RECVENM3 : Multiplexed Bus Recovery Cycle Insertion Enable 3
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Recovery cycle insertion is disabled.
#1 : 1
Recovery cycle insertion is enabled.
End of enumeration elements list.
RECVENM4 : Multiplexed Bus Recovery Cycle Insertion Enable 4
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Recovery cycle insertion is disabled.
#1 : 1
Recovery cycle insertion is enabled.
End of enumeration elements list.
RECVENM5 : Multiplexed Bus Recovery Cycle Insertion Enable 5
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Recovery cycle insertion is disabled.
#1 : 1
Recovery cycle insertion is enabled.
End of enumeration elements list.
RECVENM6 : Multiplexed Bus Recovery Cycle Insertion Enable 6
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Recovery cycle insertion is disabled.
#1 : 1
Recovery cycle insertion is enabled.
End of enumeration elements list.
RECVENM7 : Multiplexed Bus Recovery Cycle Insertion Enable 7
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Recovery cycle insertion is disabled.
#1 : 1
Recovery cycle insertion is enabled.
End of enumeration elements list.
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