\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0xA byte (0x0)
mem_usage : registers
protection : not protected
SPI Control Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPMS : SPI Mode Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
SPI operation (4-wire method)
#1 : 1
Clock synchronous operation (3-wire method)
End of enumeration elements list.
TXMD : Communications Operating Mode Select
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Full-duplex synchronous serial communications
#1 : 1
Serial communications consisting of only transmit operations
End of enumeration elements list.
MODFEN : Mode Fault Error Detection Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables the detection of mode fault error
#1 : 1
Enables the detection of mode fault error
End of enumeration elements list.
MSTR : SPI Master/Slave Mode Select
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Slave mode
#1 : 1
Master mode
End of enumeration elements list.
SPEIE : SPI Error Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables the generation of SPI error interrupt requests
#1 : 1
Enables the generation of SPI error interrupt requests
End of enumeration elements list.
SPTIE : Transmit Buffer Empty Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables the generation of transmit buffer empty interrupt requests
#1 : 1
Enables the generation of transmit buffer empty interrupt requests
End of enumeration elements list.
SPE : SPI Function Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables the SPI function
#1 : 1
Enables the SPI function
End of enumeration elements list.
SPRIE : SPI Receive Buffer Full Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables the generation of SPI receive buffer full interrupt requests
#1 : 1
Enables the generation of SPI receive buffer full interrupt requests
End of enumeration elements list.
SPI Slave Select Polarity Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSL0P : SSL0 Signal Polarity Setting
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
SSL0 signal is active low
#1 : 1
SSL0 signal is active high
End of enumeration elements list.
SSL1P : SSL1 Signal Polarity Setting
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
SSL1 signal is active low
#1 : 1
SSL1 signal is active high
End of enumeration elements list.
SSL2P : SSL2 Signal Polarity Setting
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
SSL2 signal is active low
#1 : 1
SSL2 signal is active high
End of enumeration elements list.
SSL3P : SSL3 Signal Polarity Setting
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
SSL3 signal is active low
#1 : 1
SSL3 signal is active high
End of enumeration elements list.
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 4 - 6 (3 bit)
access : read-write
SPI Command Register 0
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPHA : RSPCK Phase Setting
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data sampling on odd edge, data variation on even edge
#1 : 1
Data variation on odd edge, data sampling on even edge
End of enumeration elements list.
CPOL : RSPCK Polarity Setting
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
RSPCK is low when idle
#1 : 1
RSPCK is high when idle
End of enumeration elements list.
BRDV : Bit Rate Division Setting
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#00 : 00
These bits select the base bit rate
#01 : 01
These bits select the base bit rate divided by 2
#10 : 10
These bits select the base bit rate divided by 4
#11 : 11
These bits select the base bit rate divided by 8
End of enumeration elements list.
SSLA : SSL Signal Assertion Setting
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : 000
SSL0
#001 : 001
SSL1
#010 : 010
SSL2
#011 : 011
SSL3
: others
Setting prohibited
End of enumeration elements list.
SSLKP : SSL Signal Level Keeping
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Negates all SSL signals upon completion of transfer
#1 : 1
Keeps the SSL signal level from the end of transfer until the beginning of the next access
End of enumeration elements list.
SPB : RSPI Data Length Setting
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
20 bits
#0001 : 0001
24 bits
#0010 : 0010
32 bits
#0011 : 0011
32 bits
#1000 : 1000
9 bits
#1001 : 1001
10 bits
#1010 : 1010
11 bits
#1011 : 1011
12 bits
#1100 : 1100
13 bits
#1101 : 1101
14 bits
#1110 : 1110
15 bits
#1111 : 1111
16 bits
: others
8bits
End of enumeration elements list.
LSBF : RSPI LSB First
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
MSB first
#1 : 1
LSB first
End of enumeration elements list.
SPNDEN : RSPI Next-Access Delay Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
A next-access delay of 1 RSPCK + 2 PCLK
#1 : 1
A next-access delay is equal to the setting of the RSPI next-access delay register (SPND)
End of enumeration elements list.
SLNDEN : SSL Negation Delay Setting Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
An SSL negation delay of 1 RSPCK
#1 : 1
An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND)
End of enumeration elements list.
SCKDEN : RSPCK Delay Setting Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
An RSPCK delay of 1 RSPCK
#1 : 1
An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD)
End of enumeration elements list.
SPI Pin Control Register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPLP : RSPI Loopback
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal mode
#1 : 1
Loopback mode (data is inverted for transmission)
End of enumeration elements list.
SPLP2 : RSPI Loopback 2
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal mode
#1 : 1
Loopback mode (data is not inverted for transmission)
End of enumeration elements list.
MOIFV : MOSI Idle Fixed Value
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
The level output on the MOSIn pin during MOSI idling corresponds to low.
#1 : 1
The level output on the MOSIn pin during MOSI idling corresponds to high.
End of enumeration elements list.
MOIFE : MOSI Idle Value Fixing Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
MOSI output value equals final data from previous transfer
#1 : 1
MOSI output value equals the value set in the MOIFV bit
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
SPI Status Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVRF : Overrun Error Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No overrun error occurs
#1 : 1
An overrun error occurs
End of enumeration elements list.
IDLNF : SPI Idle Flag
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
SPI is in the idle state
#1 : 1
SPI is in the transfer state
End of enumeration elements list.
MODF : Mode Fault Error Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Neither mode fault error nor underrun error occurs
#1 : 1
A mode fault error or an underrun error occurs.
End of enumeration elements list.
PERF : Parity Error Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
No parity error occurs
#1 : 1
A parity error occurs
End of enumeration elements list.
UDRF : Underrun Error Flag(When MODF is 0, This bit is invalid.)
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
A mode fault error occurs (MODF=1)
#1 : 1
An underrun error occurs (MODF=1)
End of enumeration elements list.
SPTEF : SPI Transmit Buffer Empty Flag
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data found in the transmit buffer
#1 : 1
No data in the transmit buffer
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
SPRF : SPI Receive Buffer Full Flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
No valid data in SPDR
#1 : 1
Valid data found in SPDR
End of enumeration elements list.
SPI Data Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPDR : SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in word (SPDCR.SPLW=1), access SPDR.
bits : 0 - 30 (31 bit)
access : read-write
SPI Data Register ( halfword access )
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : SPDR
reset_Mask : 0x0
SPDR_HA : SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in halfword (SPDCR.SPLW=0), access SPDR_HA.
bits : 0 - 14 (15 bit)
access : read-write
SPI Bit Rate Register
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPR : SPBR sets the bit rate in master mode.
bits : 0 - 6 (7 bit)
access : read-write
SPI Data Control Register
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPRDTD : RSPI Receive/Transmit Data Selection
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
SPDR values are read from the receive buffer
#1 : 1
SPDR values are read from the transmit buffer (but only if the transmit buffer is empty)
End of enumeration elements list.
SPLW : SPI Word Access/Halfword Access Specification
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
SPDR_HA is valid to access in halfwords
#1 : 1
SPDR is valid (to access in words).
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
SPI Clock Delay Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCKDL : RSPCK Delay Setting
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
1 RSPCK
#001 : 001
2 RSPCK
#010 : 010
3 RSPCK
#011 : 011
4 RSPCK
#100 : 100
5 RSPCK
#101 : 101
6 RSPCK
#110 : 110
7 RSPCK
#111 : 111
8 RSPCK
End of enumeration elements list.
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 3 - 6 (4 bit)
access : read-write
SPI Slave Select Negation Delay Register
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLNDL : SSL Negation Delay Setting
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
1 RSPCK
#001 : 001
2 RSPCK
#010 : 010
3 RSPCK
#011 : 011
4 RSPCK
#100 : 100
5 RSPCK
#101 : 101
6 RSPCK
#110 : 110
7 RSPCK
#111 : 111
8 RSPCK
End of enumeration elements list.
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 3 - 6 (4 bit)
access : read-write
SPI Next-Access Delay Register
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPNDL : SPI Next-Access Delay Setting
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
1 RSPCK + 2 PCLK
#001 : 001
2 RSPCK + 2 PCLK
#010 : 010
3 RSPCK + 2 PCLK
#011 : 011
4 RSPCK + 2 PCLK
#100 : 100
5 RSPCK + 2 PCLK
#101 : 101
6 RSPCK + 2 PCLK
#110 : 110
7 RSPCK + 2 PCLK
#111 : 111
8 RSPCK + 2 PCLK
End of enumeration elements list.
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 3 - 6 (4 bit)
access : read-write
SPI Control Register 2
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPPE : Parity Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Does not add the parity bit to transmit data and does not check the parity bit of receive data
#1 : 1
Adds the parity bit to transmit data and checks the parity bit of receive data (when SPCR.TXMD = 0) / Adds the parity bit to transmit data but does not check the parity bit of receive data (when SPCR.TXMD = 1)
End of enumeration elements list.
SPOE : Parity Mode
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Selects even parity for use in transmission and reception
#1 : 1
Selects odd parity for use in transmission and reception
End of enumeration elements list.
SPIIE : SPI Idle Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables the generation of idle interrupt requests
#1 : 1
Enables the generation of idle interrupt requests
End of enumeration elements list.
PTE : Parity Self-Testing
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables the self-diagnosis function of the parity circuit
#1 : 1
Enables the self-diagnosis function of the parity circuit
End of enumeration elements list.
SCKASE : RSPCK Auto-Stop Function Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables the RSPCK auto-stop function
#1 : 1
Enables the RSPCK auto-stop function
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 5 - 6 (2 bit)
access : read-write
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