Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
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size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x68 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xB0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x36 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x46 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x54 Bytes (0x0)
size : 0xE byte (0x0)
mem_usage : registers
protection : not protected
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size : 0x16 byte (0x0)
mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
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size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xCC Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :
System Configuration Control Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBE : USB Operation Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled.
End of enumeration elements list.
DMRPU : D- Line Resistor Control
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Line pull-up disabled
#1 : 1
Line pull-up enabled.
End of enumeration elements list.
DPRPU : D+ Line Resistor Control
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Line pull-down disabled
#1 : 1
Line pull-down enabled.
End of enumeration elements list.
DRPD : D+/D- Line Resistor Control
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Line pull-down disabled
#1 : 1
Line pull-down enabled.
End of enumeration elements list.
DCFM : Controller Function Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Device controller selected
#1 : 1
Host controller selected.
End of enumeration elements list.
CNEN : CNEN Single End Receiver Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Single end receiver disabled
#1 : 1
Single end receiver enabled
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 9 - 8 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 9 - 8 (0 bit)
access : read-write
SCKE : USB Clock Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Clock supply to the USBFS stopped
#1 : 1
Clock supply to the USBFS enabled.
End of enumeration elements list.
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 11 - 14 (4 bit)
access : read-write
Pipe %s Transaction Counter Enable Register
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
The current counter value is cleared.
End of enumeration elements list.
TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transaction counter is disabled.
#1 : 1
Transaction counter is enabled.
End of enumeration elements list.
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 10 - 14 (5 bit)
access : read-write
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 10 - 14 (5 bit)
access : read-write
Pipe %s Transaction Counter Register
address_offset : 0x124 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write
CFIFO Port Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOPORT : FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.
bits : 0 - 14 (15 bit)
access : read-write
CFIFO Port Register L
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CFIFO
reset_Mask : 0x0
Pipe %s Control Register
address_offset : 0x152 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depending on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Pipe n not in use for the transaction
#1 : 1
Pipe n in use for the transaction.
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write disabled
#1 : 1
Specifies DATA1.
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write disabled
#1 : 1
Specifies DATA0.
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled (all buffers are initialized)
End of enumeration elements list.
ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto response disabled.
#1 : 1
Auto response enabled.
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 11 - 12 (2 bit)
access : read-write
Reserved : These bits are read as 000. The write value should be 000.
bits : 11 - 12 (2 bit)
access : read-write
INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
No data to be transmitted is in the FIFO buffer
#1 : 1
Data to be transmitted is in the FIFO buffer
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access by the CPU is disabled.
#1 : 1
Buffer access by the CPU is enabled.
End of enumeration elements list.
Pipe %s Control Register
address_offset : 0x170 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depending on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Pipe n not in use for the transaction
#1 : 1
Pipe n in use for the transaction.
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid
#1 : 1
Specifies DATA1.
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid
#1 : 1
Specifies DATA0.
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto buffer clear mode is disabled.
#1 : 1
Auto buffer clear mode is enabled (all buffers are initialized)
End of enumeration elements list.
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access is disabled.
#1 : 1
Buffer access is enabled.
End of enumeration elements list.
D0FIFO Port Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOPORT : FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.
bits : 0 - 14 (15 bit)
access : read-write
D0FIFO Port Register L
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : D0FIFO
reset_Mask : 0x0
Device Address %s Configuration Register
address_offset : 0x1A0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
DEVADDn is not used
#01 : 01
Low speed
#10 : 10
Full speed
#11 : 11
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 00000000. The write value should be 00000000.
bits : 8 - 14 (7 bit)
access : read-write
Reserved : These bits are read as 00000000. The write value should be 00000000.
bits : 8 - 14 (7 bit)
access : read-write
Pipe %s Transaction Counter Enable Register
address_offset : 0x1B4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
The current counter value is cleared.
End of enumeration elements list.
TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transaction counter is disabled.
#1 : 1
Transaction counter is enabled.
End of enumeration elements list.
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 10 - 14 (5 bit)
access : read-write
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 10 - 14 (5 bit)
access : read-write
Pipe %s Transaction Counter Register
address_offset : 0x1BA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write
D1FIFO Port Register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOPORT : FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits.
bits : 0 - 14 (15 bit)
access : read-write
D1FIFO Port Register L
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : D1FIFO
reset_Mask : 0x0
Pipe %s Control Register
address_offset : 0x1C6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depending on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Pipe n not in use for the transaction
#1 : 1
Pipe n in use for the transaction.
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write disabled
#1 : 1
Specifies DATA1.
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write disabled
#1 : 1
Specifies DATA0.
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled (all buffers are initialized)
End of enumeration elements list.
ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto response disabled.
#1 : 1
Auto response enabled.
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 11 - 12 (2 bit)
access : read-write
Reserved : These bits are read as 000. The write value should be 000.
bits : 11 - 12 (2 bit)
access : read-write
INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
No data to be transmitted is in the FIFO buffer
#1 : 1
Data to be transmitted is in the FIFO buffer
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access by the CPU is disabled.
#1 : 1
Buffer access by the CPU is enabled.
End of enumeration elements list.
Pipe %s Control Register
address_offset : 0x1EE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depending on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Pipe n not in use for the transaction
#1 : 1
Pipe n in use for the transaction.
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid
#1 : 1
Specifies DATA1.
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid
#1 : 1
Specifies DATA0.
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto buffer clear mode is disabled.
#1 : 1
Auto buffer clear mode is enabled (all buffers are initialized)
End of enumeration elements list.
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access is disabled.
#1 : 1
Buffer access is enabled.
End of enumeration elements list.
CFIFO Port Select Register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURPIPE : CFIFO Port Access Pipe Specification
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
DCP (Default control pipe)
#0001 : 0001
Pipe 1
#0010 : 0010
Pipe 2
#0011 : 0011
Pipe 3
#0100 : 0100
Pipe 4
#0101 : 0101
Pipe 5
#0110 : 0110
Pipe 6
#0111 : 0111
Pipe 7
#1000 : 1000
Pipe 8
#1001 : 1001
Pipe 9
End of enumeration elements list.
ISEL : CFIFO Port Access Direction When DCP is Selected
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Reading from the buffer memory is selected
#1 : 1
Writing to the buffer memory is selected
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 6 - 6 (1 bit)
access : read-write
BIGEND : CFIFO Port Endian Control
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Little endian
#1 : 1
Big endian
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 9 - 8 (0 bit)
access : read-write
MBW : CFIFO Port Access Bit Width
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
8-bit width
#1 : 1
16-bit width
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 11 - 12 (2 bit)
access : read-write
REW : Buffer Pointer Rewind
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
The buffer pointer is not rewound.
#1 : 1
The buffer pointer is rewound.
End of enumeration elements list.
RCNT : Read Count Mode
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the CFIFO.(In double buffer mode, the DTLN[8:0] bit value is cleared when all the data has been read from only a single plane.)
#1 : 1
The DTLN[8:0] bits are decremented each time the receive data is read from the CFIFO.
End of enumeration elements list.
CFIFO Port Control Register
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTLN : Receive Data LengthIndicates the length of the receive data.
bits : 0 - 7 (8 bit)
access : read-only
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 9 - 11 (3 bit)
access : read-write
FRDY : FIFO Port Ready
bits : 13 - 12 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO port access is disabled.
#1 : 1
FIFO port access is enabled.
End of enumeration elements list.
BCLR : CPU Buffer ClearNote: Only 0 can be read.
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Does not operate
#1 : 1
FIFO buffer cleared on the CPU side.
End of enumeration elements list.
BVAL : Buffer Memory Valid Flag
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
Writing ended
End of enumeration elements list.
Pipe %s Control Register
address_offset : 0x23C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depending on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Pipe n not in use for the transaction
#1 : 1
Pipe n in use for the transaction.
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write disabled
#1 : 1
Specifies DATA1.
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write disabled
#1 : 1
Specifies DATA0.
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled (all buffers are initialized)
End of enumeration elements list.
ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto response disabled.
#1 : 1
Auto response enabled.
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 11 - 12 (2 bit)
access : read-write
Reserved : These bits are read as 000. The write value should be 000.
bits : 11 - 12 (2 bit)
access : read-write
INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
No data to be transmitted is in the FIFO buffer
#1 : 1
Data to be transmitted is in the FIFO buffer
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access by the CPU is disabled.
#1 : 1
Buffer access by the CPU is enabled.
End of enumeration elements list.
Pipe %s Transaction Counter Enable Register
address_offset : 0x24C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
The current counter value is cleared.
End of enumeration elements list.
TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transaction counter is disabled.
#1 : 1
Transaction counter is enabled.
End of enumeration elements list.
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 10 - 14 (5 bit)
access : read-write
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 10 - 14 (5 bit)
access : read-write
Pipe %s Transaction Counter Register
address_offset : 0x254 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write
Pipe %s Control Register
address_offset : 0x26E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depending on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Pipe n not in use for the transaction
#1 : 1
Pipe n in use for the transaction.
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid
#1 : 1
Specifies DATA1.
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid
#1 : 1
Specifies DATA0.
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto buffer clear mode is disabled.
#1 : 1
Auto buffer clear mode is enabled (all buffers are initialized)
End of enumeration elements list.
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access is disabled.
#1 : 1
Buffer access is enabled.
End of enumeration elements list.
Device Address %s Configuration Register
address_offset : 0x272 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
DEVADDn is not used
#01 : 01
Low speed
#10 : 10
Full speed
#11 : 11
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 00000000. The write value should be 00000000.
bits : 8 - 14 (7 bit)
access : read-write
Reserved : These bits are read as 00000000. The write value should be 00000000.
bits : 8 - 14 (7 bit)
access : read-write
D0FIFO Port Select Register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURPIPE : FIFO Port Access Pipe Specification
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
DCP (Default control pipe)
#0001 : 0001
Pipe 1
#0010 : 0010
Pipe 2
#0011 : 0011
Pipe 3
#0100 : 0100
Pipe 4
#0101 : 0101
Pipe 5
#0110 : 0110
Pipe 6
#0111 : 0111
Pipe 7
#1000 : 1000
Pipe 8
#1001 : 1001
Pipe 9
End of enumeration elements list.
BIGEND : FIFO Port Endian Control
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Little endian
#1 : 1
Big endian
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 9 - 8 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 9 - 8 (0 bit)
access : read-write
MBW : FIFO Port Access Bit Width
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
8-bit width
#1 : 1
16-bit width
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 11 - 10 (0 bit)
access : read-write
DREQE : DMA/DTC Transfer Request Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA/DTC transfer request is disabled.
#1 : 1
DMA/DTC transfer request is enabled.
End of enumeration elements list.
DCLRM : Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto buffer clear mode is disabled.
#1 : 1
Auto buffer clear mode is enabled.
End of enumeration elements list.
REW : Buffer Pointer RewindNote: Only 0 can be read.
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
The buffer pointer is not rewound.
#1 : 1
The buffer pointer is rewound.
End of enumeration elements list.
RCNT : Read Count Mode
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.)
#1 : 1
The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1)
End of enumeration elements list.
D0FIFO Port Control Register
address_offset : 0x2A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTLN : Receive Data LengthIndicates the length of the receive data.
bits : 0 - 7 (8 bit)
access : read-only
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 9 - 11 (3 bit)
access : read-write
FRDY : FIFO Port Ready
bits : 13 - 12 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO port access is disabled.
#1 : 1
FIFO port access is enabled.
End of enumeration elements list.
BCLR : CPU Buffer ClearNote: Only 0 can be read.
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Does not operate
#1 : 1
FIFO buffer cleared on the CPU side.
End of enumeration elements list.
BVAL : Buffer Memory Valid Flag
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
Writing ended
End of enumeration elements list.
Pipe %s Control Register
address_offset : 0x2B4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depending on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Pipe n not in use for the transaction
#1 : 1
Pipe n in use for the transaction.
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write disabled
#1 : 1
Specifies DATA1.
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write disabled
#1 : 1
Specifies DATA0.
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled (all buffers are initialized)
End of enumeration elements list.
ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto response disabled.
#1 : 1
Auto response enabled.
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 11 - 12 (2 bit)
access : read-write
Reserved : These bits are read as 000. The write value should be 000.
bits : 11 - 12 (2 bit)
access : read-write
INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
No data to be transmitted is in the FIFO buffer
#1 : 1
Data to be transmitted is in the FIFO buffer
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access by the CPU is disabled.
#1 : 1
Buffer access by the CPU is enabled.
End of enumeration elements list.
D1FIFO Port Select Register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURPIPE : FIFO Port Access Pipe Specification
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
DCP (Default control pipe)
#0001 : 0001
Pipe 1
#0010 : 0010
Pipe 2
#0011 : 0011
Pipe 3
#0100 : 0100
Pipe 4
#0101 : 0101
Pipe 5
#0110 : 0110
Pipe 6
#0111 : 0111
Pipe 7
#1000 : 1000
Pipe 8
#1001 : 1001
Pipe 9
End of enumeration elements list.
BIGEND : FIFO Port Endian Control
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Little endian
#1 : 1
Big endian
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 9 - 8 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 9 - 8 (0 bit)
access : read-write
MBW : FIFO Port Access Bit Width
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
8-bit width
#1 : 1
16-bit width
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 11 - 10 (0 bit)
access : read-write
DREQE : DMA/DTC Transfer Request Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
DMA/DTC transfer request is disabled.
#1 : 1
DMA/DTC transfer request is enabled.
End of enumeration elements list.
DCLRM : Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto buffer clear mode is disabled.
#1 : 1
Auto buffer clear mode is enabled.
End of enumeration elements list.
REW : Buffer Pointer Rewind
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
The buffer pointer is not rewound.
#1 : 1
The buffer pointer is rewound.
End of enumeration elements list.
RCNT : Read Count Mode
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.)
#1 : 1
The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1)
End of enumeration elements list.
D1FIFO Port Control Register
address_offset : 0x2E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTLN : Receive Data LengthIndicates the length of the receive data.
bits : 0 - 7 (8 bit)
access : read-only
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 9 - 11 (3 bit)
access : read-write
FRDY : FIFO Port Ready
bits : 13 - 12 (0 bit)
access : read-only
Enumeration:
#0 : 0
FIFO port access is disabled.
#1 : 1
FIFO port access is enabled.
End of enumeration elements list.
BCLR : CPU Buffer ClearNote: Only 0 can be read.
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Does not operate
#1 : 1
FIFO buffer cleared on the CPU side.
End of enumeration elements list.
BVAL : Buffer Memory Valid Flag
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
Writing ended
End of enumeration elements list.
Pipe %s Transaction Counter Enable Register
address_offset : 0x2E8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
The current counter value is cleared.
End of enumeration elements list.
TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transaction counter is disabled.
#1 : 1
Transaction counter is enabled.
End of enumeration elements list.
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 10 - 14 (5 bit)
access : read-write
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 10 - 14 (5 bit)
access : read-write
Pipe %s Transaction Counter Register
address_offset : 0x2F2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write
Interrupt Enable Register 0
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reserved : These bits are read as 00000000. The write value should be 00000000.
bits : 0 - 6 (7 bit)
access : read-write
BRDYE : Buffer Ready Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
NRDYE : Buffer Not Ready Response Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
BEMPE : Buffer Empty Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
CTRE : Control Transfer Stage Transition Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
DVSE : Device State Transition Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
SOFE : Frame Number Update Interrupt Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
RSME : Resume Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
VBSE : VBUS Interrupt Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
Interrupt Enable Register 1
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDDETINTE0 : PDDETINT0 Detection Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
SACKE : Setup Transaction Normal Response Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
SIGNE : Setup Transaction Error Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
EOFERRE : EOF Error Detection Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 7 - 9 (3 bit)
access : read-write
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 7 - 9 (3 bit)
access : read-write
ATTCHE : Connection Detection Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
DTCHE : Disconnection Detection Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 13 - 12 (0 bit)
access : read-write
BCHGE : USB Bus Change Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
OVRCRE : Overcurrent Input Change Interrupt Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
Device Address %s Configuration Register
address_offset : 0x346 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
DEVADDn is not used
#01 : 01
Low speed
#10 : 10
Full speed
#11 : 11
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 00000000. The write value should be 00000000.
bits : 8 - 14 (7 bit)
access : read-write
Reserved : These bits are read as 00000000. The write value should be 00000000.
bits : 8 - 14 (7 bit)
access : read-write
BRDY Interrupt Enable Register
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPE0BRDYE : BRDY Interrupt Enable for PIPE0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE1BRDYE : BRDY Interrupt Enable for PIPE1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE2BRDYE : BRDY Interrupt Enable for PIPE2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE3BRDYE : BRDY Interrupt Enable for PIPE3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE4BRDYE : BRDY Interrupt Enable for PIPE4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE5BRDYE : BRDY Interrupt Enable for PIPE5
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE6BRDYE : BRDY Interrupt Enable for PIPE6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE7BRDYE : BRDY Interrupt Enable for PIPE7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE8BRDYE : BRDY Interrupt Enable for PIPE8
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE9BRDYE : BRDY Interrupt Enable for PIPE9
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 10 - 14 (5 bit)
access : read-write
NRDY Interrupt Enable Register
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPE0NRDYE : NRDY Interrupt Enable for PIPE0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE1NRDYE : NRDY Interrupt Enable for PIPE1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE2NRDYE : NRDY Interrupt Enable for PIPE2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE3NRDYE : NRDY Interrupt Enable for PIPE3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE4NRDYE : NRDY Interrupt Enable for PIPE4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE5NRDYE : NRDY Interrupt Enable for PIPE5
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE6NRDYE : NRDY Interrupt Enable for PIPE6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE7NRDYE : NRDY Interrupt Enable for PIPE7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE8NRDYE : NRDY Interrupt Enable for PIPE8
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE9NRDYE : NRDY Interrupt Enable for PIPE9
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 10 - 14 (5 bit)
access : read-write
Pipe %s Transaction Counter Enable Register
address_offset : 0x388 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCLR : Transaction Counter Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
The current counter value is cleared.
End of enumeration elements list.
TRENB : Transaction Counter Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transaction counter is disabled.
#1 : 1
Transaction counter is enabled.
End of enumeration elements list.
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 10 - 14 (5 bit)
access : read-write
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 10 - 14 (5 bit)
access : read-write
Pipe %s Transaction Counter Register
address_offset : 0x394 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNCNT : Transaction Counter
bits : 0 - 14 (15 bit)
access : read-write
BEMP Interrupt Enable Register
address_offset : 0x3A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPE0BEMPE : BEMP Interrupt Enable for PIPE0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE1BEMPE : BEMP Interrupt Enable for PIPE1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE2BEMPE : BEMP Interrupt Enable for PIPE2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE3BEMPE : BEMP Interrupt Enable for PIPE3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE4BEMPE : BEMP Interrupt Enable for PIPE4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE5BEMPE : BEMP Interrupt Enable for PIPE5
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE6BEMPE : BEMP Interrupt Enable for PIPE6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE7BEMPE : BEMP Interrupt Enable for PIPE7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE8BEMPE : BEMP Interrupt Enable for PIPE8
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
PIPE9BEMPE : BEMP Interrupt Enable for PIPE9
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt output disabled
#1 : 1
Interrupt output enabled
End of enumeration elements list.
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 10 - 14 (5 bit)
access : read-write
SOF Output Configuration Register
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGESTS : Edge Interrupt Output Status Monitor
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
before stopping the clock supply to the USB module
#1 : 1
the edge interrupt output signal is in the middle of the edge processing
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 5 - 4 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 5 - 4 (0 bit)
access : read-write
BRDYM : BRDY Interrupt Status Clear Timing
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
BRDY flag cleared by software
#1 : 1
BRDY flag cleared by the USBFS through a data read from the FIFO buffer or data write to the FIFO buffer.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write
TRNENSEL : Transaction-Enabled Time Select
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not low-speed communication
#1 : 1
Low-speed communication.
End of enumeration elements list.
Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 9 - 14 (6 bit)
access : read-write
System Configuration Status Register 0
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LNST : USB Data Line Status Monitor
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#00 : 00
SE0
#01 : 01
K-State (FS) / J-State(LS)
#10 : 10
J-State(FS) / K-State(LS)
#11 : 11
SE1
End of enumeration elements list.
IDMON : External ID0 Input Pin Monitor
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
USB0_ID pin is low
#1 : 1
USB0_ID pin is high
End of enumeration elements list.
HTACT : USB Host Sequencer Status Monitor
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
Host sequencer completely stopped
#1 : 1
Host sequencer not completely stopped.
End of enumeration elements list.
Reserved : These bits are read as 0000000.
bits : 7 - 12 (6 bit)
access : read-only
Reserved : These bits are read as 0000000.
bits : 7 - 12 (6 bit)
access : read-only
OVCMON : External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe OCVMON[1] bit indicates the status of the USBHS_OVRCURA pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB pin.
bits : 14 - 14 (1 bit)
access : read-only
Interrupt Status Register 0
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTSQ : Control Transfer Stage
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
#000 : 000
Idle or setup stage
#001 : 001
Control read data stage
#010 : 010
Control read status stage
#011 : 011
Control write data stage
#100 : 100
Control write status stage
#101 : 101
Control write (no data) status stage
#110 : 110
Control transfer sequence error
End of enumeration elements list.
VALID : USB Request Reception
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Setup packet is not received
#1 : 1
Setup packet is received
End of enumeration elements list.
DVSQ : Device State
bits : 4 - 5 (2 bit)
access : read-only
Enumeration:
#000 : 000
Powered state
#001 : 001
Default state
#010 : 010
Address state
#011 : 011
Configured state
End of enumeration elements list.
VBSTS : VBUS Input Status
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
USB_VBUS pin is low.
#1 : 1
USB_VBUS pin is high.
End of enumeration elements list.
BRDY : Buffer Ready Interrupt Status
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : 0
BRDY interrupts are not generated.
#1 : 1
BRDY interrupts are generated.
End of enumeration elements list.
NRDY : Buffer Not Ready Interrupt Status
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : 0
NRDY interrupts are not generated.
#1 : 1
NRDY interrupts are generated.
End of enumeration elements list.
BEMP : Buffer Empty Interrupt Status
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
#0 : 0
BEMP interrupts are not generated.
#1 : 1
BEMP interrupts are generated.
End of enumeration elements list.
CTRT : Control Transfer Stage Transition Interrupt Status
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Control transfer stage transition interrupts are not generated.
#1 : 1
Control transfer stage transition interrupts are generated.
End of enumeration elements list.
DVST : Device State Transition Interrupt Status
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
Device state transition interrupts are not generated.
#1 : 1
Device state transition interrupts are generated.
End of enumeration elements list.
SOFR : Frame Number Refresh Interrupt Status
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : 0
SOF interrupts are not generated.
#1 : 1
SOF interrupts are generated.
End of enumeration elements list.
RESM : Resume Interrupt Status
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Resume interrupts are not generated.
#1 : 1
Resume interrupts are generated.
End of enumeration elements list.
VBINT : VBUS Interrupt Status
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
VBUS interrupts are not generated.
#1 : 1
VBUS interrupts are generated.
End of enumeration elements list.
Device Address %s Configuration Register
address_offset : 0x41C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
DEVADDn is not used
#01 : 01
Low speed
#10 : 10
Full speed
#11 : 11
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 00000000. The write value should be 00000000.
bits : 8 - 14 (7 bit)
access : read-write
Reserved : These bits are read as 00000000. The write value should be 00000000.
bits : 8 - 14 (7 bit)
access : read-write
Interrupt Status Register 1
address_offset : 0x42 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDDETINT0 : PDDET0 Detection Interrupt Status
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
PDDET0 detection interrupts are not generated.
#1 : 1
PDDET0 detection interrupts are generated.
End of enumeration elements list.
SACK : Setup Transaction Normal Response Interrupt Status
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
SACK interrupts are not generated.
#1 : 1
SACK interrupts are generated.
End of enumeration elements list.
SIGN : Setup Transaction Error Interrupt Status
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
SIGN interrupts are not generated.
#1 : 1
SIGN interrupts are generated.
End of enumeration elements list.
EOFERR : EOF Error Detection Interrupt Status
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
EOFERR interrupts are not generated.
#1 : 1
EOFERR interrupts are generated.
End of enumeration elements list.
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 7 - 9 (3 bit)
access : read-write
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 7 - 9 (3 bit)
access : read-write
ATTCH : ATTCH Interrupt Status
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
ATTCH interrupts are not generated.
#1 : 1
ATTCH interrupts are generated.
End of enumeration elements list.
DTCH : USB Disconnection Detection Interrupt Status
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
DTCH interrupts are not generated.
#1 : 1
DTCH interrupts are generated.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 13 - 12 (0 bit)
access : read-write
BCHG : USB Bus Change Interrupt Status
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
BCHG interrupts are not generated.
#1 : 1
BCHG interrupts are generated.
End of enumeration elements list.
OVRCR : Overcurrent Input Change Interrupt Status
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
OVRCR interrupts are not generated.
#1 : 1
OVRCR interrupts are generated.
End of enumeration elements list.
BRDY Interrupt Status Register
address_offset : 0x46 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPE0BRDY : BRDY Interrupt Status for PIPE0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE1BRDY : BRDY Interrupt Status for PIPE1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE2BRDY : BRDY Interrupt Status for PIPE2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE3BRDY : BRDY Interrupt Status for PIPE3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE4BRDY : BRDY Interrupt Status for PIPE4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE5BRDY : BRDY Interrupt Status for PIPE5
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE6BRDY : BRDY Interrupt Status for PIPE6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE7BRDY : BRDY Interrupt Status for PIPE7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE8BRDY : BRDY Interrupt Status for PIPE8
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE9BRDY : BRDY Interrupt Status for PIPE9
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 10 - 14 (5 bit)
access : read-write
NRDY Interrupt Status Register
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPE0NRDY : NRDY Interrupt Status for PIPE0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE1NRDY : NRDY Interrupt Status for PIPE1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE2NRDY : NRDY Interrupt Status for PIPE2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE3NRDY : NRDY Interrupt Status for PIPE3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE4NRDY : NRDY Interrupt Status for PIPE4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE5NRDY : NRDY Interrupt Status for PIPE5
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE6NRDY : NRDY Interrupt Status for PIPE6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE7NRDY : NRDY Interrupt Status for PIPE7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE8NRDY : NRDY Interrupt Status for PIPE8
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE9NRDY : NRDY Interrupt Status for PIPE9
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 10 - 14 (5 bit)
access : read-write
BEMP Interrupt Status Register
address_offset : 0x4A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPE0BEMP : BEMP Interrupt Status for PIPE0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE1BEMP : BEMP Interrupt Status for PIPE1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE2BEMP : BEMP Interrupt Status for PIPE2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE3BEMP : BEMP Interrupt Status for PIPE3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE4BEMP : BEMP Interrupt Status for PIPE4
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE5BEMP : BEMP Interrupt Status for PIPE5
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE6BEMP : BEMP Interrupt Status for PIPE6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE7BEMP : BEMP Interrupt Status for PIPE7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE8BEMP : BEMP Interrupt Status for PIPE8
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
PIPE9BEMP : BEMP Interrupt Status for PIPE9
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts are not generated.
#1 : 1
Interrupts are generated.
End of enumeration elements list.
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 10 - 14 (5 bit)
access : read-write
Frame Number Register
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRNM : Frame NumberLatest frame number
bits : 0 - 9 (10 bit)
access : read-only
Reserved : These bits are read as 000. The write value should be 000.
bits : 11 - 12 (2 bit)
access : read-write
CRCE : Receive Data Error
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
No error
#1 : 1
An error occurred
End of enumeration elements list.
OVRN : Overrun/Underrun Detection Status
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : 0
No error
#1 : 1
An error occurred
End of enumeration elements list.
Device Address %s Configuration Register
address_offset : 0x4F4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
DEVADDn is not used
#01 : 01
Low speed
#10 : 10
Full speed
#11 : 11
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 00000000. The write value should be 00000000.
bits : 8 - 14 (7 bit)
access : read-write
Reserved : These bits are read as 00000000. The write value should be 00000000.
bits : 8 - 14 (7 bit)
access : read-write
USB Request Type Register
address_offset : 0x54 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BMREQUESTTYPE : Request TypeThese bits store the USB request bmRequestType value.
bits : 0 - 6 (7 bit)
access : read-write
BREQUEST : RequestThese bits store the USB request bRequest value.
bits : 8 - 14 (7 bit)
access : read-write
USB Request Value Register
address_offset : 0x56 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WVALUE : ValueThese bits store the USB request Value value.
bits : 0 - 14 (15 bit)
access : read-write
USB Request Index Register
address_offset : 0x58 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WINDEX : IndexThese bits store the USB request wIndex value.
bits : 0 - 14 (15 bit)
access : read-write
USB Request Length Register
address_offset : 0x5A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WLENGTH : LengthThese bits store the USB request wLength value.
bits : 0 - 14 (15 bit)
access : read-write
DCP Configuration Register
address_offset : 0x5C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Transfer Direction
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Data receiving direction
#1 : 1
Data transmitting direction
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 5 - 5 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 5 - 5 (1 bit)
access : read-write
SHTNAK : Pipe Disabled at End of Transfer
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Pipe continued at the end of transfer
#1 : 1
Pipe disabled at the end of transfer
End of enumeration elements list.
Reserved : These bits are read as 00000000. The write value should be 00000000.
bits : 8 - 14 (7 bit)
access : read-write
Device Address %s Configuration Register
address_offset : 0x5CE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : 00
DEVADDn is not used
#01 : 01
Low speed
#10 : 10
Full speed
#11 : 11
Setting prohibited
End of enumeration elements list.
Reserved : These bits are read as 00000000. The write value should be 00000000.
bits : 8 - 14 (7 bit)
access : read-write
Reserved : These bits are read as 00000000. The write value should be 00000000.
bits : 8 - 14 (7 bit)
access : read-write
DCP Maximum Packet Size Register
address_offset : 0x5E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MXPS : Maximum Packet SizeThese bits set the maximum amount of data (maximum packet size) in payloads for the DCP.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x08 : 0x08
8 bytes
0x10 : 0x10
16 bytes
0x18 : 0x18
24 bytes
0x20 : 0x20
32 bytes
0x28 : 0x28
40 bytes
0x30 : 0x30
48 bytes
0x38 : 0x38
56 bytes
0x40 : 0x40
64 bytes
0x48 : 0x48
72 bytes
0x50 : 0x50
80 bytes
0x58 : 0x58
88 bytes
0x60 : 0x60
96 bytes
0x68 : 0x68
104 bytes
0x70 : 0x70
112 bytes
0x78 : 0x78
120 bytes
End of enumeration elements list.
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 7 - 10 (4 bit)
access : read-write
DEVSEL : Device Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
Address 0000
#0001 : 0001
Address 0001
#0010 : 0010
Address 0010
#0011 : 0011
Address 0011
#0100 : 0100
Address 0100
#0101 : 0101
Address 0101
End of enumeration elements list.
DCP Control Register
address_offset : 0x60 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depending on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
CCPL : Control Transfer End Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
Completion of control transfer is enabled.
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
DCP is not used for the transaction.
#1 : 1
DCP is used for the transaction.
End of enumeration elements list.
SQMON : Sequence Toggle Bit Monitor
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
Specifies DATA1.
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
Specifies DATA0.
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 9 - 9 (1 bit)
access : read-write
Reserved : These bits are read as 00. The write value should be 00.
bits : 9 - 9 (1 bit)
access : read-write
SUREQCLR : SUREQ Bit Clear
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
Clears the SUREQ bit to 0.
End of enumeration elements list.
Reserved : These bits are read as 00. The write value should be 00.
bits : 12 - 12 (1 bit)
access : read-write
SUREQ : Setup Token Transmission
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid
#1 : 1
Transmits the setup packet.
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access is disabled.
#1 : 1
Buffer access is enabled.
End of enumeration elements list.
Pipe Window Select Register
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIPESEL : Pipe Window Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
No pipe selected
#0001 : 0001
PIPE1
#0010 : 0010
PIPE2
#0011 : 0011
PIPE3
#0100 : 0100
PIPE4
#0101 : 0101
PIPE5
#0110 : 0110
PIPE6
#0111 : 0111
PIPE7
#1000 : 1000
PIPE8
#1001 : 1001
PIPE9
End of enumeration elements list.
Reserved : These bits are read as 000000000000. The write value should be 000000000000.
bits : 4 - 14 (11 bit)
access : read-write
Pipe Configuration Register
address_offset : 0x68 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPNUM : Endpoint NumberThese bits specify the endpoint number for the selected pipe.Setting 0000b means unused pipe.
bits : 0 - 2 (3 bit)
access : read-write
DIR : Transfer Direction
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Receiving direction
#1 : 1
Transmitting direction
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
Reserved : This bit is read as 0. The write value should be 0.
bits : 6 - 5 (0 bit)
access : read-write
SHTNAK : Pipe Disabled at End of Transfer
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Continue pipe operation after transfer ends
#1 : 1
Disable pipe operation after transfer ends.
End of enumeration elements list.
Reserved : This bit is read as 0. The write value should be 0.
bits : 8 - 7 (0 bit)
access : read-write
DBLB : Double Buffer Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Single buffer
#1 : 1
Double buffer
End of enumeration elements list.
BFRE : BRDY Interrupt Operation Specification
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
BRDY interrupt upon transmitting or receiving data
#1 : 1
BRDY interrupt upon completion of reading data
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 11 - 12 (2 bit)
access : read-write
TYPE : Transfer Type
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#00 : 00
Pipe not used
#01 : 01
Bulk transfer(PIPE1 and PIPE5) /Setting prohibited(PIPE6 to PIPE9)
#10 : 10
Setting prohibited(PIPE1 and PIPE5) /Interrupt transfer(PIPE6 to PIPE9)
#11 : 11
Isochronous transfer(PIPE1 and PIPE2) /Setting prohibited(PIPE3 to PIPE9)
End of enumeration elements list.
Pipe Maximum Packet Size Register
address_offset : 0x6C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MXPS : Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to 64 bytes (040h) (Bits [8:7] are not provided.)
bits : 0 - 7 (8 bit)
access : read-write
Reserved : These bits are read as 000. The write value should be 000.
bits : 9 - 10 (2 bit)
access : read-write
DEVSEL : Device Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
Address 0000
#0001 : 0001
Address 0001
#0010 : 0010
Address 0010
#0011 : 0011
Address 0011
#0100 : 0100
Address 0100
#0101 : 0101
Address 0101
End of enumeration elements list.
Pipe Cycle Control Register
address_offset : 0x6E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IITV : Interval Error Detection IntervalSpecifies the interval error detection timing for the selected pipe in terms of frames, which is expressed as nth power of 2.
bits : 0 - 1 (2 bit)
access : read-write
IFIS : Isochronous IN Buffer Flush
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
The buffer is not flushed.
#1 : 1
The buffer is flushed.
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write
Reserved : These bits are read as 000. The write value should be 000.
bits : 13 - 14 (2 bit)
access : read-write
Device State Control Register 0
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RHST : USB Bus Reset Status
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
#000 : 000
Communication speed not determined
#001 : 001
Low-speed connection(When the host controller is selected) /USB bus reset in progress( When the function controller is selected)
#010 : 010
Full-speed connection(When the host controller is selected) /USB bus reset in progress or full-speed connection(When the function controller is selected)
#011 : 011
Setting prohibited
End of enumeration elements list.
UACT : USB Bus Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Downstream port is disabled (SOF transmission is disabled).
#1 : 1
Downstream port is enabled (SOF transmission is enabled).
End of enumeration elements list.
RESUME : Resume Output
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Resume signal is not output.
#1 : 1
Resume signal is output.
End of enumeration elements list.
USBRST : USB Bus Reset Output
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
USB bus reset signal is not output.
#1 : 1
USB bus reset signal is output.
End of enumeration elements list.
RWUPE : Wakeup Detection Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Downstream port wakeup is disabled.
#1 : 1
Downstream port wakeup is enabled.
End of enumeration elements list.
WKUP : Wakeup Output
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Remote wakeup signal is not output.
#1 : 1
Remote wakeup signal is output.
End of enumeration elements list.
VBUSEN : USB_VBUSEN Output Pin Control
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
External USB_VBUSEN pin outputs low
#1 : 1
External USB_VBUSEN pin outputs high
End of enumeration elements list.
EXICEN : USB_EXICEN Output Pin Control
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
External USB_EXICEN pin outputs low
#1 : 1
External USB_EXICEN pin outputs high
End of enumeration elements list.
HNPBTOA : Host Negotiation Protocol (HNP) Control This bit is used when switching from device B to device A while in OTG mode. If the HNPBTOA bit is 1, the internal function control keeps the suspended state until the HNP processing ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set.
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Switching from device B to device A is enabled
End of enumeration elements list.
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write
Reserved : These bits are read as 0000. The write value should be 0000.
bits : 12 - 14 (3 bit)
access : read-write
BC Control Register 0
address_offset : 0xB0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RPDME0 : D- Pin Pull-Down Control
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Pull-down off
#1 : 1
Pull-down on
End of enumeration elements list.
IDPSRCE0 : D+ Pin IDPSRC Output Control
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Stop
#1 : 1
10uA output
End of enumeration elements list.
IDMSINKE0 : D- Pin 0.6 V Input Detection (Comparator and Sink) Control
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Detection off
#1 : 1
Detection on ( Comparator and sink current on )
End of enumeration elements list.
VDPSRCE0 : D+ Pin VDPSRC (0.6 V) Output Control
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Stop
#1 : 1
0.6V output
End of enumeration elements list.
IDPSINKE0 : D+ Pin 0.6 V Input Detection (Comparator and Sink) Control
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Detection off
#1 : 1
Detection on ( Comparator and sink current on )
End of enumeration elements list.
VDMSRCE0 : D- Pin VDMSRC (0.6 V) Output Control
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Stop
#1 : 1
0.6V output
End of enumeration elements list.
BATCHGE0 : BC (Battery Charger) Function Ch0 General Enable Control
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHGDETSTS0 : D- Pin 0.6 V Input Detection Status
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : 0
Not detected
#1 : 1
Detected
End of enumeration elements list.
PDDETSTS0 : D+ Pin 0.6 V Input Detection Status
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : 0
Not detected
#1 : 1
Detected
End of enumeration elements list.
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 10 - 14 (5 bit)
access : read-write
Reserved : These bits are read as 000000. The write value should be 000000.
bits : 10 - 14 (5 bit)
access : read-write
USB Module Control Register
address_offset : 0xCC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VDDUSBE : USB Reference Power Supply Circuit On/Off Control
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
USB reference power supply circuit off
#1 : 1
USB reference power supply circuit on
End of enumeration elements list.
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 2 - 5 (4 bit)
access : read-write
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 2 - 5 (4 bit)
access : read-write
VDCEN : USB Regulator On/Off Control
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
USB regulator off
#1 : 1
USB regulator on
End of enumeration elements list.
Reserved : These bits are read as 00000000. The write value should be 00000000.
bits : 8 - 14 (7 bit)
access : read-write
Pipe %s Control Register
address_offset : 0xE0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depending on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Pipe n not in use for the transaction
#1 : 1
Pipe n in use for the transaction.
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write disabled
#1 : 1
Specifies DATA1.
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write disabled
#1 : 1
Specifies DATA0.
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled (all buffers are initialized)
End of enumeration elements list.
ATREPM : Auto Response Mode
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto response disabled.
#1 : 1
Auto response enabled.
End of enumeration elements list.
Reserved : These bits are read as 000. The write value should be 000.
bits : 11 - 12 (2 bit)
access : read-write
Reserved : These bits are read as 000. The write value should be 000.
bits : 11 - 12 (2 bit)
access : read-write
INBUFM : Transmit Buffer Monitor
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : 0
No data to be transmitted is in the FIFO buffer
#1 : 1
Data to be transmitted is in the FIFO buffer
End of enumeration elements list.
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access by the CPU is disabled.
#1 : 1
Buffer access by the CPU is enabled.
End of enumeration elements list.
Pipe %s Control Register
address_offset : 0xF4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Response PID
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
NAK response
#01 : 01
BUF response (depending on the buffer state)
#10 : 10
STALL response
#11 : 11
STALL response
End of enumeration elements list.
PBUSY : Pipe Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
Pipe n not in use for the transaction
#1 : 1
Pipe n in use for the transaction.
End of enumeration elements list.
SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
DATA0
#1 : 1
DATA1
End of enumeration elements list.
SQSET : Sequence Toggle Bit Set
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid
#1 : 1
Specifies DATA1.
End of enumeration elements list.
SQCLR : Sequence Toggle Bit Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
Invalid
#1 : 1
Specifies DATA0.
End of enumeration elements list.
ACLRM : Auto Buffer Clear Mode
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Auto buffer clear mode is disabled.
#1 : 1
Auto buffer clear mode is enabled (all buffers are initialized)
End of enumeration elements list.
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write
Reserved : These bits are read as 00000. The write value should be 00000.
bits : 10 - 13 (4 bit)
access : read-write
BSTS : Buffer Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : 0
Buffer access is disabled.
#1 : 1
Buffer access is enabled.
End of enumeration elements list.
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