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DAC12

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DADR0

DACR

DADPR

DAADSCR

DAVREFCR


DADR0

D/A Data Register 0
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DADR0 DADR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DADR

DADR : D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order 4 bits are fixed to 0: right justified format. When DADPR.DPSEL = 1, the low-order 4 bits are fixed to 0: left justified format.
bits : 0 - 14 (15 bit)
access : read-write


DACR

D/A Control Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DACR DACR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 Reserved Reserved DAOE0 Reserved

Reserved : This bit is read as 0. The write value should be 0.
bits : 5 - 4 (0 bit)
access : read-write

Reserved : This bit is read as 0. The write value should be 0.
bits : 5 - 4 (0 bit)
access : read-write

DAOE0 : D/A Output Enable 0
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Analog output of channel 0 (DA0) is disabled.

#1 : 1

D/A conversion of channel 0 is enabled. Analog output of channel 0 (DA0) is enabled.

End of enumeration elements list.

Reserved : This bit is read as 0. The write value should be 0.
bits : 7 - 6 (0 bit)
access : read-write


DADPR

DADR0 Format Select Register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DADPR DADPR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 Reserved DPSEL

Reserved : These bits are read as 0000000. The write value should be 0000000.
bits : 0 - 5 (6 bit)
access : read-write

DPSEL : DADRm Format Select
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Right justified format.

#1 : 1

Left justified format.

End of enumeration elements list.


DAADSCR

D/A-A/D Synchronous Start Control Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAADSCR DAADSCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DAADST

DAADST : D/A-A/D Synchronous Conversion
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

D/A converter operation does not synchronize with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is disabled).

#1 : 1

D/A converter operation synchronizes with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is enabled).

End of enumeration elements list.


DAVREFCR

D/A VREF Control Register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAVREFCR DAVREFCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 REF Reserved

REF : D/A Reference Voltage Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

Not selected

#001 : 001

AVCC0/AVSS0

#011 : 011

Internal reference voltage/AVSS0

#110 : 110

VREFH/VREFL

End of enumeration elements list.

Reserved : These bits are read as 00000. The write value should be 00000.
bits : 3 - 6 (4 bit)
access : read-write



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