\n

SLCDC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100 Bytes (0x0)
size : 0x36 byte (0x0)
mem_usage : registers
protection : not protected

Registers

LCDM0

LCDM1

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

LCDC0

SEG0

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

VLCD

SEG1

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13


LCDM0

LCD Mode Register 0
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCDM0 LCDM0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LBAS LDTY LWAVE MDSET

LBAS : LCD Display Bias Method Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

1/2 bias method

#01 : 01

1/3 bias method

#10 : 10

1/4 bias method

#11 : 11

Setting prohibited

End of enumeration elements list.

LDTY : Time Slice of LCD Display Select
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#000 : 000

Static

#001 : 001

2-time slice

#010 : 010

3-time slice

#011 : 011

4-time slice

#101 : 101

8-time slice

End of enumeration elements list.

LWAVE : LCD display waveform selection
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Waveform A

#1 : 1

Waveform B

End of enumeration elements list.

MDSET : LCD drive voltage generator selection
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

External resistance division method

#01 : 01

Internal voltage boosting method

#10 : 10

Capacitor split method

#11 : 11

Setting prohibited

End of enumeration elements list.


LCDM1

LCD Mode Register 1
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCDM1 LCDM1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LCDVLM Reserved LCDSEL BLON VLCON SCOC LCDON

LCDVLM : Voltage Boosting Pin Initial Value Switching Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Set when VDD >= 2.7 V

#1 : 1

Set when VDD <= 4.2 V

End of enumeration elements list.

Reserved : These bits are read as 00. The write value should be 00.
bits : 1 - 1 (1 bit)
access : read-write

LCDSEL : Display data area control
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Displaying an A-pattern area data (lower four bits of LCD display data register)(BLON=0)/Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC))(BLON=1)

#1 : 1

Displaying a B-pattern area data (higher four bits of LCD display data register)(BLON=0)/Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC))(BLON=1)

End of enumeration elements list.

BLON : Display data area control
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Displaying an A-pattern area data (lower four bits of LCD display data register)(LCDSEL=0)/Displaying a B-pattern area data (higher four bits of LCD display data register)(LCDSEL=1)

#1 : 1

Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC))

End of enumeration elements list.

VLCON : Voltage boost circuit or capacitor split circuit operation enable/disable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Stops voltage boost circuit or capacitor split circuit operation

#1 : 1

Enables voltage boost circuit or capacitor split circuit operation

End of enumeration elements list.

SCOC : LCD Display Enable/Disable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Output ground level to segment/common pin(LCDON=0)/Output ground level to segment/common pin(LCDON=1)

#1 : 1

Display off (all segment outputs are deselected)(LCDON=0)/Display on(LCDON=1)

End of enumeration elements list.

LCDON : LCD Display Enable/Disable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Output ground level to segment/common pin(SCOC=0)/Display off (all segment outputs are deselected)(SCOC=1)

#1 : 1

Output ground level to segment/common pin(SCOC=0)/Display on(SCOC=1)

End of enumeration elements list.


SEG14

LCD Display Data Register %s
address_offset : 0x1069 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG14 SEG14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG15

LCD Display Data Register %s
address_offset : 0x1178 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG15 SEG15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG16

LCD Display Data Register %s
address_offset : 0x1288 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG16 SEG16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG17

LCD Display Data Register %s
address_offset : 0x1399 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG17 SEG17 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG18

LCD Display Data Register %s
address_offset : 0x14AB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG18 SEG18 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG19

LCD Display Data Register %s
address_offset : 0x15BE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG19 SEG19 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG20

LCD Display Data Register %s
address_offset : 0x16D2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG20 SEG20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG21

LCD Display Data Register %s
address_offset : 0x17E7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG21 SEG21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG22

LCD Display Data Register %s
address_offset : 0x18FD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG22 SEG22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG23

LCD Display Data Register %s
address_offset : 0x1A14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG23 SEG23 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG24

LCD Display Data Register %s
address_offset : 0x1B2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG24 SEG24 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG25

LCD Display Data Register %s
address_offset : 0x1C45 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG25 SEG25 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG26

LCD Display Data Register %s
address_offset : 0x1D5F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG26 SEG26 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG27

LCD Display Data Register %s
address_offset : 0x1E7A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG27 SEG27 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG28

LCD Display Data Register %s
address_offset : 0x1F96 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG28 SEG28 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


LCDC0

LCD Clock Control Register 0
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCDC0 LCDC0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LCDC

LCDC : LCD clock (LCDCL)
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

#000001 : 000001

(Sub clock)/22 or (LOCO clock)/22

#000010 : 000010

(Sub clock)/23 or (LOCO clock)/23

#000011 : 000011

(Sub clock)/24 or (LOCO clock)/24

#000100 : 000100

(Sub clock)/25 or (LOCO clock)/25

#000101 : 000101

(Sub clock)/26 or (LOCO clock)/26

#000110 : 000110

(Sub clock)/27 or (LOCO clock)/27

#000111 : 000111

(Sub clock)/28 or (LOCO clock)/28

#001000 : 001000

(Sub clock)/29 or (LOCO clock)/29

#001001 : 001001

(Sub clock)/210 or (LOCO clock)/210

#010001 : 010001

(Main clock)/28 or (HOCO clock)/28

#010010 : 010010

(Main clock)/29 or (HOCO clock)/29

#010011 : 010011

(Main clock)/210 or (HOCO clock)/210

#010100 : 010100

(Main clock)/211 or (HOCO clock)/211

#010101 : 010101

(Main clock)/212 or (HOCO clock)/212

#010110 : 010110

(Main clock)/213 or (HOCO clock)/213

#010111 : 010111

(Main clock)/214 or (HOCO clock)/214

#011000 : 011000

(Main clock)/215 or (HOCO clock)/215

#011001 : 011001

(Main clock)/216 or (HOCO clock)/216

#011010 : 011010

(Main clock)/217 or (HOCO clock)/217

#011011 : 011011

(Main clock)/218 or (HOCO clock)/218

#101011 : 101011

(Main clock)/219 or (HOCO clock)/219

End of enumeration elements list.


SEG0

LCD Display Data Register %s
address_offset : 0x200 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG0 SEG0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG29

LCD Display Data Register %s
address_offset : 0x20B3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG29 SEG29 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG30

LCD Display Data Register %s
address_offset : 0x21D1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG30 SEG30 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG31

LCD Display Data Register %s
address_offset : 0x22F0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG31 SEG31 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG32

LCD Display Data Register %s
address_offset : 0x2410 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG32 SEG32 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG33

LCD Display Data Register %s
address_offset : 0x2531 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG33 SEG33 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG34

LCD Display Data Register %s
address_offset : 0x2653 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG34 SEG34 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG35

LCD Display Data Register %s
address_offset : 0x2776 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG35 SEG35 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG36

LCD Display Data Register %s
address_offset : 0x289A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG36 SEG36 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG37

LCD Display Data Register %s
address_offset : 0x29BF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG37 SEG37 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG38

LCD Display Data Register %s
address_offset : 0x2AE5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG38 SEG38 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG39

LCD Display Data Register %s
address_offset : 0x2C0C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG39 SEG39 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG40

LCD Display Data Register %s
address_offset : 0x2D34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG40 SEG40 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG41

LCD Display Data Register %s
address_offset : 0x2E5D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG41 SEG41 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG42

LCD Display Data Register %s
address_offset : 0x2F87 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG42 SEG42 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


VLCD

LCD Boost Level Control Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VLCD VLCD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VLCD

VLCD : Reference Voltage(Contrast Adjustment) Select
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#00100 : 00100

Reference voltageselection(contrast adjustment): 1.00 V (default) VL4 voltage: 3.00 V(1/3 bias method)/4.00 V(1/4 bias method)

#00101 : 00101

Reference voltageselection(contrast adjustment): 1.05 V VL4 voltage: 3.15 V(1/3 bias method)/4.20 V(1/4 bias method)

#00110 : 00110

Reference voltageselection(contrast adjustment): 1.10 V VL4 voltage: 3.30 V(1/3 bias method)/4.40 V(1/4 bias method)

#00111 : 00111

Reference voltageselection(contrast adjustment): 1.15 V VL4 voltage: 3.45 V(1/3 bias method)/4.60 V(1/4 bias method)

#01000 : 01000

Reference voltageselection(contrast adjustment): 1.20 V VL4 voltage: 3.60 V(1/3 bias method)/4.80 V(1/4 bias method)

#01001 : 01001

Reference voltageselection(contrast adjustment): 1.25 V VL4 voltage: 3.75 V(1/3 bias method)/5.00 V(1/4 bias method)

#01010 : 01010

Reference voltageselection(contrast adjustment): 1.30 V VL4 voltage: 3.90 V(1/3 bias method)/5.20 V(1/4 bias method)

#01011 : 01011

Reference voltageselection(contrast adjustment): 1.35 V VL4 voltage: 4.05 V(1/3 bias method)/Setting prohibited(1/4 bias method)

#01100 : 01100

Reference voltageselection(contrast adjustment): 1.40 V VL4 voltage: 4.20 V(1/3 bias method)/Setting prohibited(1/4 bias method)

#01101 : 01101

Reference voltageselection(contrast adjustment): 1.45 V VL4 voltage: 4.35 V(1/3 bias method)/Setting prohibited(1/4 bias method)

#01110 : 01110

Reference voltageselection(contrast adjustment): 1.50 V VL4 voltage: 4.50 V(1/3 bias method)/Setting prohibited(1/4 bias method)

#01111 : 01111

Reference voltageselection(contrast adjustment): 1.55 V VL4 voltage: 4.65 V(1/3 bias method)/Setting prohibited(1/4 bias method)

#10000 : 10000

Reference voltageselection(contrast adjustment): 1.60 V VL4 voltage: 4.80 V(1/3 bias method)/Setting prohibited(1/4 bias method)

#10001 : 10001

Reference voltageselection(contrast adjustment): 1.65 V VL4 voltage: 4.95 V(1/3 bias method)/Setting prohibited(1/4 bias method)

#10010 : 10010

Reference voltageselection(contrast adjustment): 1.70 V VL4 voltage: 5.10 V(1/3 bias method)/Setting prohibited(1/4 bias method)

#10011 : 10011

Reference voltageselection(contrast adjustment): 1.75 V VL4 voltage: 5.25 V(1/3 bias method)/Setting prohibited(1/4 bias method)

End of enumeration elements list.


SEG1

LCD Display Data Register %s
address_offset : 0x301 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG1 SEG1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG43

LCD Display Data Register %s
address_offset : 0x30B2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG43 SEG43 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG44

LCD Display Data Register %s
address_offset : 0x31DE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG44 SEG44 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG45

LCD Display Data Register %s
address_offset : 0x330B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG45 SEG45 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG46

LCD Display Data Register %s
address_offset : 0x3439 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG46 SEG46 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG47

LCD Display Data Register %s
address_offset : 0x3568 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG47 SEG47 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG48

LCD Display Data Register %s
address_offset : 0x3698 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG48 SEG48 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG49

LCD Display Data Register %s
address_offset : 0x37C9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG49 SEG49 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG50

LCD Display Data Register %s
address_offset : 0x38FB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG50 SEG50 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG51

LCD Display Data Register %s
address_offset : 0x3A2E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG51 SEG51 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG52

LCD Display Data Register %s
address_offset : 0x3B62 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG52 SEG52 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG53

LCD Display Data Register %s
address_offset : 0x3C97 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG53 SEG53 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG2

LCD Display Data Register %s
address_offset : 0x403 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG2 SEG2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG3

LCD Display Data Register %s
address_offset : 0x506 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG3 SEG3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG4

LCD Display Data Register %s
address_offset : 0x60A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG4 SEG4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG5

LCD Display Data Register %s
address_offset : 0x70F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG5 SEG5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG6

LCD Display Data Register %s
address_offset : 0x815 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG6 SEG6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG7

LCD Display Data Register %s
address_offset : 0x91C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG7 SEG7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG8

LCD Display Data Register %s
address_offset : 0xA24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG8 SEG8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG9

LCD Display Data Register %s
address_offset : 0xB2D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG9 SEG9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG10

LCD Display Data Register %s
address_offset : 0xC37 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG10 SEG10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG11

LCD Display Data Register %s
address_offset : 0xD42 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG11 SEG11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG12

LCD Display Data Register %s
address_offset : 0xE4E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG12 SEG12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write


SEG13

LCD Display Data Register %s
address_offset : 0xF5B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEG13 SEG13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEG

SEG : LCD Display Data
bits : 0 - 6 (7 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.