\n

R_BUS

Peripheral Memory Blocks

address_offset : 0x802 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x880 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1100 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1128 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2 Bytes (0x0)
size : 0xA byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x12 Bytes (0x0)
size : 0xA byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x22 Bytes (0x0)
size : 0xA byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x32 Bytes (0x0)
size : 0xA byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x42 Bytes (0x0)
size : 0xA byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x52 Bytes (0x0)
size : 0xA byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x62 Bytes (0x0)
size : 0xA byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x72 Bytes (0x0)
size : 0xA byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x80A Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x812 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x81A Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x822 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x82A Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x832 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x83A Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x842 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x84A Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x852 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x85A Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x862 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x86A Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x872 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x87A Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC00 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC10 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC14 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC20 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC24 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC40 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC44 Bytes (0x0)
size : 0x6 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC50 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1000 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1004 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1008 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1010 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1014 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1104 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1108 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x110C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1110 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1114 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1118 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x111C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1120 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1124 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x112C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1130 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1134 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1138 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x113C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1800 Bytes (0x0)
size : 0x5 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1810 Bytes (0x0)
size : 0x5 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1820 Bytes (0x0)
size : 0x5 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1830 Bytes (0x0)
size : 0x5 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1840 Bytes (0x0)
size : 0x5 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1850 Bytes (0x0)
size : 0x5 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1860 Bytes (0x0)
size : 0x5 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1870 Bytes (0x0)
size : 0x5 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1880 Bytes (0x0)
size : 0x5 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1890 Bytes (0x0)
size : 0x5 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x18A0 Bytes (0x0)
size : 0x5 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SDRAM - SDCCR

SDCCR

ADD

CNT

SDRAM - SDCMOD

SDCMOD

SDRAM - SDSELF

SDSELF

BUSM[M4I]-CNT

BUSS[EXT2]-BUSS[EXT]-BUSS[FBU]-BUSS[P7B]-BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

CSb[1]-CSb[0]-CR

CSb[1]-CSb[0]-REC

BUSERR[BUS11]-BUSERR[BUS10]-BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD

BUSERR[BUS11]-BUSERR[BUS10]-BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT

BUSS[FLI]-CNT

BUSS[GPX]-BUSS[EXT2]-BUSS[EXT]-BUSS[FBU]-BUSS[P7B]-BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

CSa[1]-CSa[0]-MOD

CSa[1]-CSa[0]-WCR1

SDRAM - SDRFCR

SDRFCR

CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-MOD

CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR1

CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR2

SDRAM - SDRFEN

SDRFEN

CSa[1]-CSa[0]-WCR2

BUSERR[BUS1]-ADD

BUSERR[BUS1]-STAT

CSb[2]-CSb[1]-CSb[0]-CR

CSb[2]-CSb[1]-CSb[0]-REC

CSa[7]-CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-MOD

CSa[7]-CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR1

CSa[7]-CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR2

CSa[0]-MOD

SDRAM - SDAMOD

MOD

CR

SDAMOD

SDRAM - SDICR

SDICR

BUSM[M4D]-BUSM[M4I]-CNT

CSb[3]-CSb[2]-CSb[1]-CSb[0]-CR

CSb[3]-CSb[2]-CSb[1]-CSb[0]-REC

BUSS[RAMH]-BUSS[FLI]-CNT

SDRAM - SDIR

SDIR

CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-CR

CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-REC

BUSM[SYS]-BUSM[M4D]-BUSM[M4I]-CNT

BUSERR[BUS2]-BUSERR[BUS1]-ADD

BUSERR[BUS2]-BUSERR[BUS1]-STAT

CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-CR

CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-REC

CSa[2]-CSa[1]-CSa[0]-MOD

BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

CSa[2]-CSa[1]-CSa[0]-WCR1

CSa[2]-CSa[1]-CSa[0]-WCR2

CSb[6]-CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-CR

CSb[6]-CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-REC

CSa[0]-WCR1

WCR1

STAT

SDRAM - SDADR

SDADR

BUSM[DMA]-BUSM[SYS]-BUSM[M4D]-BUSM[M4I]-CNT

CSb[7]-CSb[6]-CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-CR

CSb[7]-CSb[6]-CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-REC

SDRAM - SDTR

SDTR

BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

SDRAM - SDMOD

SDMOD

BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD

BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT

SDRAM - SDSR

SDSR

BUSM[EDM]-BUSM[DMA]-BUSM[SYS]-BUSM[M4D]-BUSM[M4I]-CNT

BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

BUSM[GPX]-BUSM[EDM]-BUSM[DMA]-BUSM[SYS]-BUSM[M4D]-BUSM[M4I]-CNT

BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD

BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT

CSa[3]-CSa[2]-CSa[1]-CSa[0]-MOD

CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR1

BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR2

BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD

BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT

CSa[0]-WCR2

WCR2

CSb[0]-CR

CSb[0]-REC

CSRECEN

BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD

BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT

BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

REC

CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-MOD

CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR1

CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR2

BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD

BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT

BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD

BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT

BUSS[P7B]-BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD

BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT

BUSS[FBU]-BUSS[P7B]-BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

BUSS[EXT]-BUSS[FBU]-BUSS[P7B]-BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-MOD

BUSERR[BUS10]-BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD

BUSERR[BUS10]-BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT

CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR1

CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR2


SDRAM - SDCCR

SDRAM Registers - - SDC Control Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDRAM - SDCCR SDRAM - SDCCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EXENB BSIZE

EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

BSIZE : SDRAM Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

A 16-bit bus space

#01 : 01

Setting prohibited

#10 : 10

An 8-bit bus space

#11 : 11

Setting prohibited

End of enumeration elements list.


SDCCR

SDC Control Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDCCR SDCCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EXENB BSIZE

EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

BSIZE : SDRAM Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

A 16-bit bus space

#01 : 01

Setting prohibited

#10 : 10

An 8-bit bus space

#11 : 11

Setting prohibited

End of enumeration elements list.


ADD

Bus Error Address Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADD ADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error AddressWhen a bus error occurs, It stores an error address.
bits : 0 - 30 (31 bit)
access : read-only


CNT

Master Bus Control Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IERES

IERES : Ignore Error Responses
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus error will be reported.

#1 : 1

Bus error will not be reported.

End of enumeration elements list.


SDRAM - SDCMOD

SDRAM Registers - - SDC Mode Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDRAM - SDCMOD SDRAM - SDCMOD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EMODE

EMODE : Endian Mode
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Endian order of SDRAM address space is the same as the endian order of the operating mode

#1 : 1

Endian order of SDRAM address space is not the endian order of the operating mode.

End of enumeration elements list.


SDCMOD

SDC Mode Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDCMOD SDCMOD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EMODE

EMODE : Endian Mode
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Endian order of SDRAM address space is the same as the endian order of the operating mode

#1 : 1

Endian order of SDRAM address space is not the endian order of the operating mode.

End of enumeration elements list.


SDRAM - SDSELF

SDRAM Registers - - SDRAM Self-Refresh Control Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDRAM - SDSELF SDRAM - SDSELF read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SFEN

SFEN : SDRAM Self-Refresh Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.


SDSELF

SDRAM Self-Refresh Control Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDSELF SDSELF read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SFEN

SFEN : SDRAM Self-Refresh Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.


BUSM[M4I]-CNT

Master Bus Control Register
address_offset : 0x1000 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSM[M4I]-CNT BUSM[M4I]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IERES

IERES : Ignore Error Responses
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus error will be reported.

#1 : 1

Bus error will not be reported.

End of enumeration elements list.


BUSS[EXT2]-BUSS[EXT]-BUSS[FBU]-BUSS[P7B]-BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

Slave Bus Control Register
address_offset : 0x100A4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSS[EXT2]-BUSS[EXT]-BUSS[FBU]-BUSS[P7B]-BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT BUSS[EXT2]-BUSS[EXT]-BUSS[FBU]-BUSS[P7B]-BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBMET

ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

fixed priority

#01 : 01

round-robin

End of enumeration elements list.


CSb[1]-CSb[0]-CR

Control Register
address_offset : 0x1012 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSb[1]-CSb[0]-CR CSb[1]-CSb[0]-CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXENB BSIZE EMODE MPXEN

EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable operation

#1 : 1

Enable operation

End of enumeration elements list.

BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

A 16-bit bus space

#01 : 01

Setting prohibited

#10 : 10

An 8-bit bus space

#11 : 11

Setting prohibited

End of enumeration elements list.

EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little Endian

#1 : 1

Big Endian

End of enumeration elements list.

MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Separate bus interface is selected for area n

#1 : 1

Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)

End of enumeration elements list.


CSb[1]-CSb[0]-REC

Recovery Cycle Register
address_offset : 0x101A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSb[1]-CSb[0]-REC CSb[1]-CSb[0]-REC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRCV WRCV

RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

End of enumeration elements list.

WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

End of enumeration elements list.


BUSERR[BUS11]-BUSERR[BUS10]-BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD

Bus Error Address Register
address_offset : 0x10B70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS11]-BUSERR[BUS10]-BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD BUSERR[BUS11]-BUSERR[BUS10]-BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error AddressWhen a bus error occurs, It stores an error address.
bits : 0 - 30 (31 bit)
access : read-only


BUSERR[BUS11]-BUSERR[BUS10]-BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT

Bus Error Status Register
address_offset : 0x10B74 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS11]-BUSERR[BUS10]-BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT BUSERR[BUS11]-BUSERR[BUS10]-BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACCSTAT ERRSTAT

ACCSTAT : Error access statusThe status at the time of the error
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Read access

#1 : 1

Write Access

End of enumeration elements list.

ERRSTAT : Bus Error StatusWhen bus error assert, error flag occurs.
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

No bus error occurred

#1 : 1

Bus error occurred

End of enumeration elements list.


BUSS[FLI]-CNT

Slave Bus Control Register
address_offset : 0x1100 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSS[FLI]-CNT BUSS[FLI]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBMET

ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

fixed priority

#01 : 01

round-robin

End of enumeration elements list.


BUSS[GPX]-BUSS[EXT2]-BUSS[EXT]-BUSS[FBU]-BUSS[P7B]-BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

Slave Bus Control Register
address_offset : 0x111E0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSS[GPX]-BUSS[EXT2]-BUSS[EXT]-BUSS[FBU]-BUSS[P7B]-BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT BUSS[GPX]-BUSS[EXT2]-BUSS[EXT]-BUSS[FBU]-BUSS[P7B]-BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBMET

ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

fixed priority

#01 : 01

round-robin

End of enumeration elements list.


CSa[1]-CSa[0]-MOD

Mode Register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[1]-CSa[0]-MOD CSa[1]-CSa[0]-MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRMOD EWENB PRENB PWENB PRMOD

WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Byte strobe mode

#1 : 1

Single write strobe mode

End of enumeration elements list.

EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PRMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal access compatible mode

#1 : 1

External data read continuous assertion mode

End of enumeration elements list.


CSa[1]-CSa[0]-WCR1

Wait Control Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[1]-CSa[0]-WCR1 CSa[1]-CSa[0]-WCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPWWAIT CSPRWAIT CSWWAIT CSRWAIT

CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

End of enumeration elements list.

CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

End of enumeration elements list.


SDRAM - SDRFCR

SDRAM Registers - - SDRAM Refresh Control Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDRAM - SDRFCR SDRAM - SDRFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFC REFW

RFC : Auto-Refresh Request Interval Setting
bits : 0 - 10 (11 bit)
access : read-write

Enumeration:

0x0 : 0x0

Setting prohibited

End of enumeration elements list.

REFW : Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count Setting. ( REFW+1 Cycles )
bits : 12 - 14 (3 bit)
access : read-write


SDRFCR

SDRAM Refresh Control Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDRFCR SDRFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFC REFW

RFC : Auto-Refresh Request Interval Setting
bits : 0 - 10 (11 bit)
access : read-write

Enumeration:

0x0 : 0x0

Setting prohibited

: others

RFC+1 cycles inserted

End of enumeration elements list.

REFW : Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count Setting. ( REFW+1 Cycles )
bits : 12 - 14 (3 bit)
access : read-write


CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-MOD

Mode Register
address_offset : 0x152 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-MOD CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRMOD EWENB PRENB PWENB PRMOD

WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Byte strobe mode

#1 : 1

Single write strobe mode

End of enumeration elements list.

EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PRMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal access compatible mode

#1 : 1

External data read continuous assertion mode

End of enumeration elements list.


CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR1

Wait Control Register 1
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR1 CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPWWAIT CSPRWAIT CSWWAIT CSRWAIT

CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

End of enumeration elements list.

CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

End of enumeration elements list.


CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR2

Wait Control Register 2
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR2 CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSROFF CSWOFF WDOFF AWAIT RDON WRON WDON CSON

CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

AWAIT : CS Assert Wait Select
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.


SDRAM - SDRFEN

SDRAM Registers - - SDRAM Auto-Refresh Control Register
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDRAM - SDRFEN SDRAM - SDRFEN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RFEN

RFEN : Auto-Refresh Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.


SDRFEN

SDRAM Auto-Refresh Control Register
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDRFEN SDRFEN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RFEN

RFEN : Auto-Refresh Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.


CSa[1]-CSa[0]-WCR2

Wait Control Register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[1]-CSa[0]-WCR2 CSa[1]-CSa[0]-WCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSROFF CSWOFF WDOFF AWAIT RDON WRON WDON CSON

CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

AWAIT : CS Assert Wait Select
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.


BUSERR[BUS1]-ADD

Bus Error Address Register
address_offset : 0x1800 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS1]-ADD BUSERR[BUS1]-ADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error AddressWhen a bus error occurs, It stores an error address.
bits : 0 - 30 (31 bit)
access : read-only


BUSERR[BUS1]-STAT

Bus Error Status Register
address_offset : 0x1804 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS1]-STAT BUSERR[BUS1]-STAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACCSTAT ERRSTAT

ACCSTAT : Error access statusThe status at the time of the error
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Read access

#1 : 1

Write Access

End of enumeration elements list.

ERRSTAT : Bus Error StatusWhen bus error assert, error flag occurs.
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

No bus error occurred

#1 : 1

Bus error occurred

End of enumeration elements list.


CSb[2]-CSb[1]-CSb[0]-CR

Control Register
address_offset : 0x1832 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSb[2]-CSb[1]-CSb[0]-CR CSb[2]-CSb[1]-CSb[0]-CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXENB BSIZE EMODE MPXEN

EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable operation

#1 : 1

Enable operation

End of enumeration elements list.

BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

A 16-bit bus space

#01 : 01

Setting prohibited

#10 : 10

An 8-bit bus space

#11 : 11

Setting prohibited

End of enumeration elements list.

EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little Endian

#1 : 1

Big Endian

End of enumeration elements list.

MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Separate bus interface is selected for area n

#1 : 1

Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)

End of enumeration elements list.


CSb[2]-CSb[1]-CSb[0]-REC

Recovery Cycle Register
address_offset : 0x183A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSb[2]-CSb[1]-CSb[0]-REC CSb[2]-CSb[1]-CSb[0]-REC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRCV WRCV

RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

End of enumeration elements list.

WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

End of enumeration elements list.


CSa[7]-CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-MOD

Mode Register
address_offset : 0x1C2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[7]-CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-MOD CSa[7]-CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRMOD EWENB PRENB PWENB PRMOD

WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Byte strobe mode

#1 : 1

Single write strobe mode

End of enumeration elements list.

EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PRMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal access compatible mode

#1 : 1

External data read continuous assertion mode

End of enumeration elements list.


CSa[7]-CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR1

Wait Control Register 1
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[7]-CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR1 CSa[7]-CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPWWAIT CSPRWAIT CSWWAIT CSRWAIT

CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

End of enumeration elements list.

CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

End of enumeration elements list.


CSa[7]-CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR2

Wait Control Register 2
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[7]-CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR2 CSa[7]-CSa[6]-CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSROFF CSWOFF WDOFF AWAIT RDON WRON WDON CSON

CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

AWAIT : CS Assert Wait Select
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.


CSa[0]-MOD

Mode Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[0]-MOD CSa[0]-MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRMOD EWENB PRENB PWENB PRMOD

WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Byte strobe mode

#1 : 1

Single write strobe mode

End of enumeration elements list.

EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PRMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal access compatible mode

#1 : 1

External data read continuous assertion mode

End of enumeration elements list.


SDRAM - SDAMOD

SDRAM Registers - - SDRAM Access Mode Register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDRAM - SDAMOD SDRAM - SDAMOD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BE

BE : Continuous Access Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable.

End of enumeration elements list.


MOD

Mode Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRMOD EWENB PRENB PWENB PRMOD

WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Byte strobe mode

#1 : 1

Single write strobe mode

End of enumeration elements list.

EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PRMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal access compatible mode

#1 : 1

External data read continuous assertion mode

End of enumeration elements list.


CR

Control Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXENB BSIZE EMODE MPXEN

EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable operation

#1 : 1

Enable operation

End of enumeration elements list.

BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

A 16-bit bus space

#01 : 01

Setting prohibited

#10 : 10

An 8-bit bus space

#11 : 11

Setting prohibited

End of enumeration elements list.

EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little Endian

#1 : 1

Big Endian

End of enumeration elements list.

MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Separate bus interface is selected for area n

#1 : 1

Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)

End of enumeration elements list.


SDAMOD

SDRAM Access Mode Register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDAMOD SDAMOD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BE

BE : Continuous Access Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable.

End of enumeration elements list.


SDRAM - SDICR

SDRAM Registers - - SDRAM Initialization Sequence Control Register
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDRAM - SDICR SDRAM - SDICR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INIRQ

INIRQ : Initialization Sequence Start
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid

#1 : 1

Initialization sequence starts

End of enumeration elements list.


SDICR

SDRAM Initialization Sequence Control Register
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDICR SDICR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INIRQ

INIRQ : Initialization Sequence Start
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Invalid

#1 : 1

Initialization sequence starts

End of enumeration elements list.


BUSM[M4D]-BUSM[M4I]-CNT

Master Bus Control Register
address_offset : 0x2004 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSM[M4D]-BUSM[M4I]-CNT BUSM[M4D]-BUSM[M4I]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IERES

IERES : Ignore Error Responses
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus error will be reported.

#1 : 1

Bus error will not be reported.

End of enumeration elements list.


CSb[3]-CSb[2]-CSb[1]-CSb[0]-CR

Control Register
address_offset : 0x2062 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSb[3]-CSb[2]-CSb[1]-CSb[0]-CR CSb[3]-CSb[2]-CSb[1]-CSb[0]-CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXENB BSIZE EMODE MPXEN

EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable operation

#1 : 1

Enable operation

End of enumeration elements list.

BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

A 16-bit bus space

#01 : 01

Setting prohibited

#10 : 10

An 8-bit bus space

#11 : 11

Setting prohibited

End of enumeration elements list.

EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little Endian

#1 : 1

Big Endian

End of enumeration elements list.

MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Separate bus interface is selected for area n

#1 : 1

Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)

End of enumeration elements list.


CSb[3]-CSb[2]-CSb[1]-CSb[0]-REC

Recovery Cycle Register
address_offset : 0x206A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSb[3]-CSb[2]-CSb[1]-CSb[0]-REC CSb[3]-CSb[2]-CSb[1]-CSb[0]-REC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRCV WRCV

RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

End of enumeration elements list.

WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

End of enumeration elements list.


BUSS[RAMH]-BUSS[FLI]-CNT

Slave Bus Control Register
address_offset : 0x2204 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSS[RAMH]-BUSS[FLI]-CNT BUSS[RAMH]-BUSS[FLI]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBMET

ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

fixed priority

#01 : 01

round-robin

End of enumeration elements list.


SDRAM - SDIR

SDRAM Registers - - SDRAM Initialization Register
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDRAM - SDIR SDRAM - SDIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARFI ARFC PRC

ARFI : Initialization Auto-Refresh Interval ( PRF+3 cycles )
bits : 0 - 2 (3 bit)
access : read-write

ARFC : Initialization Auto-Refresh Count
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

Setting prohibited

End of enumeration elements list.

PRC : Initialization Precharge Cycle Count ( PRF+3 cycles )
bits : 8 - 9 (2 bit)
access : read-write


SDIR

SDRAM Initialization Register
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDIR SDIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARFI ARFC PRC

ARFI : Initialization Auto-Refresh Interval ( PRF+3 cycles )
bits : 0 - 2 (3 bit)
access : read-write

ARFC : Initialization Auto-Refresh Count
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

Setting prohibited

: others

ARFC+1 times

End of enumeration elements list.

PRC : Initialization Precharge Cycle Count ( PRF+3 cycles )
bits : 8 - 9 (2 bit)
access : read-write


CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-CR

Control Register
address_offset : 0x28A2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-CR CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXENB BSIZE EMODE MPXEN

EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable operation

#1 : 1

Enable operation

End of enumeration elements list.

BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

A 16-bit bus space

#01 : 01

Setting prohibited

#10 : 10

An 8-bit bus space

#11 : 11

Setting prohibited

End of enumeration elements list.

EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little Endian

#1 : 1

Big Endian

End of enumeration elements list.

MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Separate bus interface is selected for area n

#1 : 1

Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)

End of enumeration elements list.


CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-REC

Recovery Cycle Register
address_offset : 0x28AA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-REC CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-REC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRCV WRCV

RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

End of enumeration elements list.

WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

End of enumeration elements list.


BUSM[SYS]-BUSM[M4D]-BUSM[M4I]-CNT

Master Bus Control Register
address_offset : 0x300C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSM[SYS]-BUSM[M4D]-BUSM[M4I]-CNT BUSM[SYS]-BUSM[M4D]-BUSM[M4I]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IERES

IERES : Ignore Error Responses
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus error will be reported.

#1 : 1

Bus error will not be reported.

End of enumeration elements list.


BUSERR[BUS2]-BUSERR[BUS1]-ADD

Bus Error Address Register
address_offset : 0x3010 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS2]-BUSERR[BUS1]-ADD BUSERR[BUS2]-BUSERR[BUS1]-ADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error AddressWhen a bus error occurs, It stores an error address.
bits : 0 - 30 (31 bit)
access : read-only


BUSERR[BUS2]-BUSERR[BUS1]-STAT

Bus Error Status Register
address_offset : 0x3014 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS2]-BUSERR[BUS1]-STAT BUSERR[BUS2]-BUSERR[BUS1]-STAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACCSTAT ERRSTAT

ACCSTAT : Error access statusThe status at the time of the error
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Read access

#1 : 1

Write Access

End of enumeration elements list.

ERRSTAT : Bus Error StatusWhen bus error assert, error flag occurs.
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

No bus error occurred

#1 : 1

Bus error occurred

End of enumeration elements list.


CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-CR

Control Register
address_offset : 0x30F2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-CR CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXENB BSIZE EMODE MPXEN

EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable operation

#1 : 1

Enable operation

End of enumeration elements list.

BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

A 16-bit bus space

#01 : 01

Setting prohibited

#10 : 10

An 8-bit bus space

#11 : 11

Setting prohibited

End of enumeration elements list.

EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little Endian

#1 : 1

Big Endian

End of enumeration elements list.

MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Separate bus interface is selected for area n

#1 : 1

Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)

End of enumeration elements list.


CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-REC

Recovery Cycle Register
address_offset : 0x30FA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-REC CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-REC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRCV WRCV

RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

End of enumeration elements list.

WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

End of enumeration elements list.


CSa[2]-CSa[1]-CSa[0]-MOD

Mode Register
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[2]-CSa[1]-CSa[0]-MOD CSa[2]-CSa[1]-CSa[0]-MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRMOD EWENB PRENB PWENB PRMOD

WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Byte strobe mode

#1 : 1

Single write strobe mode

End of enumeration elements list.

EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PRMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal access compatible mode

#1 : 1

External data read continuous assertion mode

End of enumeration elements list.


BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

Slave Bus Control Register
address_offset : 0x330C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBMET

ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

fixed priority

#01 : 01

round-robin

End of enumeration elements list.


CSa[2]-CSa[1]-CSa[0]-WCR1

Wait Control Register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[2]-CSa[1]-CSa[0]-WCR1 CSa[2]-CSa[1]-CSa[0]-WCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPWWAIT CSPRWAIT CSWWAIT CSRWAIT

CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

End of enumeration elements list.

CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

End of enumeration elements list.


CSa[2]-CSa[1]-CSa[0]-WCR2

Wait Control Register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[2]-CSa[1]-CSa[0]-WCR2 CSa[2]-CSa[1]-CSa[0]-WCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSROFF CSWOFF WDOFF AWAIT RDON WRON WDON CSON

CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

AWAIT : CS Assert Wait Select
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.


CSb[6]-CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-CR

Control Register
address_offset : 0x3952 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSb[6]-CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-CR CSb[6]-CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXENB BSIZE EMODE MPXEN

EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable operation

#1 : 1

Enable operation

End of enumeration elements list.

BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

A 16-bit bus space

#01 : 01

Setting prohibited

#10 : 10

An 8-bit bus space

#11 : 11

Setting prohibited

End of enumeration elements list.

EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little Endian

#1 : 1

Big Endian

End of enumeration elements list.

MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Separate bus interface is selected for area n

#1 : 1

Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)

End of enumeration elements list.


CSb[6]-CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-REC

Recovery Cycle Register
address_offset : 0x395A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSb[6]-CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-REC CSb[6]-CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-REC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRCV WRCV

RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

End of enumeration elements list.

WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

End of enumeration elements list.


CSa[0]-WCR1

Wait Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[0]-WCR1 CSa[0]-WCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPWWAIT CSPRWAIT CSWWAIT CSRWAIT

CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

End of enumeration elements list.

CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

End of enumeration elements list.


WCR1

Wait Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WCR1 WCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPWWAIT CSPRWAIT CSWWAIT CSRWAIT

CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSPWWAIT clock cycle is inserted.

End of enumeration elements list.

CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSPRWAIT clock cycle is inserted.

End of enumeration elements list.

CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

: others

Wait with a length of CSWWAIT clock cycle is inserted.

End of enumeration elements list.

CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

: others

Wait with a length of CSRWAIT clock cycle is inserted.

End of enumeration elements list.


STAT

Bus Error Status Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACCSTAT ERRSTAT

ACCSTAT : Error access statusThe status at the time of the error
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Read access

#1 : 1

Write Access

End of enumeration elements list.

ERRSTAT : Bus Error StatusWhen bus error assert, error flag occurs.
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

No bus error occurred

#1 : 1

Bus error occurred

End of enumeration elements list.


SDRAM - SDADR

SDRAM Registers - - SDRAM Address Register
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDRAM - SDADR SDRAM - SDADR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MXC

MXC : Address Multiplex Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

8-bit shift

#01 : 01

9-bit shift

#10 : 10

10-bit shift

#11 : 11

11-bit shift

End of enumeration elements list.


SDADR

SDRAM Address Register
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDADR SDADR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MXC

MXC : Address Multiplex Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : 00

8-bit shift

#01 : 01

9-bit shift

#10 : 10

10-bit shift

#11 : 11

11-bit shift

End of enumeration elements list.


BUSM[DMA]-BUSM[SYS]-BUSM[M4D]-BUSM[M4I]-CNT

Master Bus Control Register
address_offset : 0x4018 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSM[DMA]-BUSM[SYS]-BUSM[M4D]-BUSM[M4I]-CNT BUSM[DMA]-BUSM[SYS]-BUSM[M4D]-BUSM[M4I]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IERES

IERES : Ignore Error Responses
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus error will be reported.

#1 : 1

Bus error will not be reported.

End of enumeration elements list.


CSb[7]-CSb[6]-CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-CR

Control Register
address_offset : 0x41C2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSb[7]-CSb[6]-CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-CR CSb[7]-CSb[6]-CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXENB BSIZE EMODE MPXEN

EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable operation

#1 : 1

Enable operation

End of enumeration elements list.

BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

A 16-bit bus space

#01 : 01

Setting prohibited

#10 : 10

An 8-bit bus space

#11 : 11

Setting prohibited

End of enumeration elements list.

EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little Endian

#1 : 1

Big Endian

End of enumeration elements list.

MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Separate bus interface is selected for area n

#1 : 1

Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)

End of enumeration elements list.


CSb[7]-CSb[6]-CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-REC

Recovery Cycle Register
address_offset : 0x41CA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSb[7]-CSb[6]-CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-REC CSb[7]-CSb[6]-CSb[5]-CSb[4]-CSb[3]-CSb[2]-CSb[1]-CSb[0]-REC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRCV WRCV

RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

End of enumeration elements list.

WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

End of enumeration elements list.


SDRAM - SDTR

SDRAM Registers - - SDRAM Timing Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDRAM - SDTR SDRAM - SDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CL WR RP RCD RAS

CL : SDRAMC Column Latency
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#001 : 001

1 cycle

#010 : 010

2 cycles

#011 : 011

3 cycles

End of enumeration elements list.

WR : Write Recovery Interval
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

1 cycle

#1 : 1

2 cycles

End of enumeration elements list.

RP : Row Precharge Interval ( RP+1 cycles )
bits : 9 - 10 (2 bit)
access : read-write

RCD : Row Column Latency ( RCD+1 cycles )
bits : 12 - 12 (1 bit)
access : read-write

RAS : Row Active Interval
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#000 : 000

1 cycle

#001 : 001

2 cycles

#010 : 010

3 cycles

#011 : 011

4 cycles

#100 : 100

5 cycles

#101 : 101

6 cycles

#110 : 110

7 cycles

#111 : 111

Setting prohibited

End of enumeration elements list.


SDTR

SDRAM Timing Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDTR SDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CL WR RP RCD RAS

CL : SDRAMC Column Latency
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#001 : 001

1 cycle

#010 : 010

2 cycles

#011 : 011

3 cycles

: others

Setting prohibited

End of enumeration elements list.

WR : Write Recovery Interval
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

1 cycle

#1 : 1

2 cycles

End of enumeration elements list.

RP : Row Precharge Interval ( RP+1 cycles )
bits : 9 - 10 (2 bit)
access : read-write

RCD : Row Column Latency ( RCD+1 cycles )
bits : 12 - 12 (1 bit)
access : read-write

RAS : Row Active Interval
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#000 : 000

1 cycle

#001 : 001

2 cycles

#010 : 010

3 cycles

#011 : 011

4 cycles

#100 : 100

5 cycles

#101 : 101

6 cycles

#110 : 110

7 cycles

#111 : 111

Setting prohibited

End of enumeration elements list.


BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

Slave Bus Control Register
address_offset : 0x4418 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBMET

ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

fixed priority

#01 : 01

round-robin

End of enumeration elements list.


SDRAM - SDMOD

SDRAM Registers - - SDRAM Mode Register
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDRAM - SDMOD SDRAM - SDMOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR

MR : Mode Register SettingWriting to these bits: Mode register set command is issued.
bits : 0 - 13 (14 bit)
access : read-write


SDMOD

SDRAM Mode Register
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMOD SDMOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR

MR : Mode Register SettingWriting to these bits: Mode register set command is issued.
bits : 0 - 13 (14 bit)
access : read-write


BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD

Bus Error Address Register
address_offset : 0x4830 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error AddressWhen a bus error occurs, It stores an error address.
bits : 0 - 30 (31 bit)
access : read-only


BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT

Bus Error Status Register
address_offset : 0x4834 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACCSTAT ERRSTAT

ACCSTAT : Error access statusThe status at the time of the error
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Read access

#1 : 1

Write Access

End of enumeration elements list.

ERRSTAT : Bus Error StatusWhen bus error assert, error flag occurs.
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

No bus error occurred

#1 : 1

Bus error occurred

End of enumeration elements list.


SDRAM - SDSR

SDRAM Registers - - SDRAM Status Register
address_offset : 0x50 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SDRAM - SDSR SDRAM - SDSR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MRSST INIST SRFST

MRSST : Mode Register Setting Status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Mode register setting not in progress

#1 : 1

Mode register setting in progress

End of enumeration elements list.

INIST : Initialization Status
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : 0

Initialization sequence not in progress

#1 : 1

Initialization sequence in progress

End of enumeration elements list.

SRFST : Self-Refresh Transition/Recovery Status
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transition/recovery not in progress

#1 : 1

Transition/recovery in progress

End of enumeration elements list.


SDSR

SDRAM Status Register
address_offset : 0x50 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SDSR SDSR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MRSST INIST SRFST

MRSST : Mode Register Setting Status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Mode register setting not in progress

#1 : 1

Mode register setting in progress

End of enumeration elements list.

INIST : Initialization Status
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : 0

Initialization sequence not in progress

#1 : 1

Initialization sequence in progress

End of enumeration elements list.

SRFST : Self-Refresh Transition/Recovery Status
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

Transition/recovery not in progress

#1 : 1

Transition/recovery in progress

End of enumeration elements list.


BUSM[EDM]-BUSM[DMA]-BUSM[SYS]-BUSM[M4D]-BUSM[M4I]-CNT

Master Bus Control Register
address_offset : 0x5028 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSM[EDM]-BUSM[DMA]-BUSM[SYS]-BUSM[M4D]-BUSM[M4I]-CNT BUSM[EDM]-BUSM[DMA]-BUSM[SYS]-BUSM[M4D]-BUSM[M4I]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IERES

IERES : Ignore Error Responses
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus error will be reported.

#1 : 1

Bus error will not be reported.

End of enumeration elements list.


BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

Slave Bus Control Register
address_offset : 0x5528 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBMET

ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

fixed priority

#01 : 01

round-robin

End of enumeration elements list.


BUSM[GPX]-BUSM[EDM]-BUSM[DMA]-BUSM[SYS]-BUSM[M4D]-BUSM[M4I]-CNT

Master Bus Control Register
address_offset : 0x603C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSM[GPX]-BUSM[EDM]-BUSM[DMA]-BUSM[SYS]-BUSM[M4D]-BUSM[M4I]-CNT BUSM[GPX]-BUSM[EDM]-BUSM[DMA]-BUSM[SYS]-BUSM[M4D]-BUSM[M4I]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IERES

IERES : Ignore Error Responses
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Bus error will be reported.

#1 : 1

Bus error will not be reported.

End of enumeration elements list.


BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD

Bus Error Address Register
address_offset : 0x6060 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error AddressWhen a bus error occurs, It stores an error address.
bits : 0 - 30 (31 bit)
access : read-only


BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT

Bus Error Status Register
address_offset : 0x6064 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACCSTAT ERRSTAT

ACCSTAT : Error access statusThe status at the time of the error
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Read access

#1 : 1

Write Access

End of enumeration elements list.

ERRSTAT : Bus Error StatusWhen bus error assert, error flag occurs.
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

No bus error occurred

#1 : 1

Bus error occurred

End of enumeration elements list.


CSa[3]-CSa[2]-CSa[1]-CSa[0]-MOD

Mode Register
address_offset : 0x62 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[3]-CSa[2]-CSa[1]-CSa[0]-MOD CSa[3]-CSa[2]-CSa[1]-CSa[0]-MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRMOD EWENB PRENB PWENB PRMOD

WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Byte strobe mode

#1 : 1

Single write strobe mode

End of enumeration elements list.

EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PRMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal access compatible mode

#1 : 1

External data read continuous assertion mode

End of enumeration elements list.


CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR1

Wait Control Register 1
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR1 CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPWWAIT CSPRWAIT CSWWAIT CSRWAIT

CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

End of enumeration elements list.

CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

End of enumeration elements list.


BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

Slave Bus Control Register
address_offset : 0x663C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBMET

ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

fixed priority

#01 : 01

round-robin

End of enumeration elements list.


CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR2

Wait Control Register 2
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR2 CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSROFF CSWOFF WDOFF AWAIT RDON WRON WDON CSON

CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

AWAIT : CS Assert Wait Select
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.


BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

Slave Bus Control Register
address_offset : 0x7754 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBMET

ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

fixed priority

#01 : 01

round-robin

End of enumeration elements list.


BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD

Bus Error Address Register
address_offset : 0x78A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error AddressWhen a bus error occurs, It stores an error address.
bits : 0 - 30 (31 bit)
access : read-only


BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT

Bus Error Status Register
address_offset : 0x78A4 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACCSTAT ERRSTAT

ACCSTAT : Error access statusThe status at the time of the error
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Read access

#1 : 1

Write Access

End of enumeration elements list.

ERRSTAT : Bus Error StatusWhen bus error assert, error flag occurs.
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

No bus error occurred

#1 : 1

Bus error occurred

End of enumeration elements list.


CSa[0]-WCR2

Wait Control Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[0]-WCR2 CSa[0]-WCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSROFF CSWOFF WDOFF AWAIT RDON WRON WDON CSON

CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

AWAIT : CS Assert Wait Select
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.


WCR2

Wait Control Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WCR2 WCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSROFF CSWOFF WDOFF AWAIT RDON WRON WDON CSON

CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSROFF clock cycle is inserted.

End of enumeration elements list.

CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSWOFF clock cycle is inserted.

End of enumeration elements list.

WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WDOFF clock cycle is inserted.

End of enumeration elements list.

AWAIT : CS Assert Wait Select
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of AWAIT clock cycle is inserted.

End of enumeration elements list.

RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of RDON clock cycle is inserted.

End of enumeration elements list.

WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WRON clock cycle is inserted.

End of enumeration elements list.

WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of WDON clock cycle is inserted.

End of enumeration elements list.

CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

: others

Wait with a length of CSON clock cycle is inserted.

End of enumeration elements list.


CSb[0]-CR

Control Register
address_offset : 0x802 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSb[0]-CR CSb[0]-CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXENB BSIZE EMODE MPXEN

EXENB : Operation Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable operation

#1 : 1

Enable operation

End of enumeration elements list.

BSIZE : External Bus Width Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

A 16-bit bus space

#01 : 01

Setting prohibited

#10 : 10

An 8-bit bus space

#11 : 11

Setting prohibited

End of enumeration elements list.

EMODE : Endian Mode
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Little Endian

#1 : 1

Big Endian

End of enumeration elements list.

MPXEN : Address/Data Multiplexed I/O Interface Select
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Separate bus interface is selected for area n

#1 : 1

Address/data multiplexed I/O interface is selected for area n. (n = 0 to 7)

End of enumeration elements list.


CSb[0]-REC

Recovery Cycle Register
address_offset : 0x80A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSb[0]-REC CSb[0]-REC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRCV WRCV

RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

End of enumeration elements list.

WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

End of enumeration elements list.


CSRECEN

CS Recovery Cycle Insertion Enable Register
address_offset : 0x880 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSRECEN CSRECEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCVEN0 RCVEN1 RCVEN2 RCVEN3 RCVEN4 RCVEN5 RCVEN6 RCVEN7 RCVENM0 RCVENM1 RCVENM2 RCVENM3 RCVENM4 RCVENM5 RCVENM6 RCVENM7

RCVEN0 : Separate Bus Recovery Cycle Insertion Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVEN1 : Separate Bus Recovery Cycle Insertion Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVEN2 : Separate Bus Recovery Cycle Insertion Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVEN3 : Separate Bus Recovery Cycle Insertion Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVEN4 : Separate Bus Recovery Cycle Insertion Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVEN5 : Separate Bus Recovery Cycle Insertion Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVEN6 : Separate Bus Recovery Cycle Insertion Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVEN7 : Separate Bus Recovery Cycle Insertion Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVENM0 : Multiplexed Bus Recovery Cycle Insertion Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVENM1 : Multiplexed Bus Recovery Cycle Insertion Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVENM2 : Multiplexed Bus Recovery Cycle Insertion Enable
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVENM3 : Multiplexed Bus Recovery Cycle Insertion Enable
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVENM4 : Multiplexed Bus Recovery Cycle Insertion Enable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVENM5 : Multiplexed Bus Recovery Cycle Insertion Enable
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVENM6 : Multiplexed Bus Recovery Cycle Insertion Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.

RCVENM7 : Multiplexed Bus Recovery Cycle Insertion Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Recovery cycle insertion is disabled.

#1 : 1

Recovery cycle insertion is enabled.

End of enumeration elements list.


BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

Slave Bus Control Register
address_offset : 0x8870 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBMET

ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

fixed priority

#01 : 01

round-robin

End of enumeration elements list.


BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD

Bus Error Address Register
address_offset : 0x90F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error AddressWhen a bus error occurs, It stores an error address.
bits : 0 - 30 (31 bit)
access : read-only


BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT

Bus Error Status Register
address_offset : 0x90F4 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACCSTAT ERRSTAT

ACCSTAT : Error access statusThe status at the time of the error
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Read access

#1 : 1

Write Access

End of enumeration elements list.

ERRSTAT : Bus Error StatusWhen bus error assert, error flag occurs.
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

No bus error occurred

#1 : 1

Bus error occurred

End of enumeration elements list.


BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

Slave Bus Control Register
address_offset : 0x9990 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBMET

ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

fixed priority

#01 : 01

round-robin

End of enumeration elements list.


REC

Recovery Cycle Register
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REC REC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRCV WRCV

RRCV : Read Recovery
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

: others

RRCV recovery cycle is inserted.

End of enumeration elements list.

WRCV : Write Recovery
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : 0x0

No recovery cycle is inserted.

: others

WRCV recovery cycle is inserted.

End of enumeration elements list.


CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-MOD

Mode Register
address_offset : 0xA2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-MOD CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRMOD EWENB PRENB PWENB PRMOD

WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Byte strobe mode

#1 : 1

Single write strobe mode

End of enumeration elements list.

EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PRMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal access compatible mode

#1 : 1

External data read continuous assertion mode

End of enumeration elements list.


CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR1

Wait Control Register 1
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR1 CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPWWAIT CSPRWAIT CSWWAIT CSRWAIT

CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

End of enumeration elements list.

CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

End of enumeration elements list.


CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR2

Wait Control Register 2
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR2 CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSROFF CSWOFF WDOFF AWAIT RDON WRON WDON CSON

CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

AWAIT : CS Assert Wait Select
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.


BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD

Bus Error Address Register
address_offset : 0xA950 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error AddressWhen a bus error occurs, It stores an error address.
bits : 0 - 30 (31 bit)
access : read-only


BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT

Bus Error Status Register
address_offset : 0xA954 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACCSTAT ERRSTAT

ACCSTAT : Error access statusThe status at the time of the error
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Read access

#1 : 1

Write Access

End of enumeration elements list.

ERRSTAT : Bus Error StatusWhen bus error assert, error flag occurs.
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

No bus error occurred

#1 : 1

Bus error occurred

End of enumeration elements list.


BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

Slave Bus Control Register
address_offset : 0xAAB4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBMET

ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

fixed priority

#01 : 01

round-robin

End of enumeration elements list.


BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

Slave Bus Control Register
address_offset : 0xBBDC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBMET

ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

fixed priority

#01 : 01

round-robin

End of enumeration elements list.


BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD

Bus Error Address Register
address_offset : 0xC1C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error AddressWhen a bus error occurs, It stores an error address.
bits : 0 - 30 (31 bit)
access : read-only


BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT

Bus Error Status Register
address_offset : 0xC1C4 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACCSTAT ERRSTAT

ACCSTAT : Error access statusThe status at the time of the error
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Read access

#1 : 1

Write Access

End of enumeration elements list.

ERRSTAT : Bus Error StatusWhen bus error assert, error flag occurs.
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

No bus error occurred

#1 : 1

Bus error occurred

End of enumeration elements list.


BUSS[P7B]-BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

Slave Bus Control Register
address_offset : 0xCD08 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSS[P7B]-BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT BUSS[P7B]-BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBMET

ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

fixed priority

#01 : 01

round-robin

End of enumeration elements list.


BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD

Bus Error Address Register
address_offset : 0xDA40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error AddressWhen a bus error occurs, It stores an error address.
bits : 0 - 30 (31 bit)
access : read-only


BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT

Bus Error Status Register
address_offset : 0xDA44 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACCSTAT ERRSTAT

ACCSTAT : Error access statusThe status at the time of the error
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Read access

#1 : 1

Write Access

End of enumeration elements list.

ERRSTAT : Bus Error StatusWhen bus error assert, error flag occurs.
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

No bus error occurred

#1 : 1

Bus error occurred

End of enumeration elements list.


BUSS[FBU]-BUSS[P7B]-BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

Slave Bus Control Register
address_offset : 0xDE38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSS[FBU]-BUSS[P7B]-BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT BUSS[FBU]-BUSS[P7B]-BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBMET

ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

fixed priority

#01 : 01

round-robin

End of enumeration elements list.


BUSS[EXT]-BUSS[FBU]-BUSS[P7B]-BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT

Slave Bus Control Register
address_offset : 0xEF6C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSS[EXT]-BUSS[FBU]-BUSS[P7B]-BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT BUSS[EXT]-BUSS[FBU]-BUSS[P7B]-BUSS[P6B]-BUSS[PxB]-BUSS[P4B]-BUSS[P3B]-BUSS[P2B]-BUSS[P0B]-BUSS[RAM1]-BUSS[RAM0]-BUSS[MBIU]-BUSS[RAMH]-BUSS[FLI]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBMET

ARBMET : Arbitration MethodSpecify the priority between groups
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

fixed priority

#01 : 01

round-robin

End of enumeration elements list.


CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-MOD

Mode Register
address_offset : 0xF2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-MOD CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRMOD EWENB PRENB PWENB PRMOD

WRMOD : Write Access Mode Select
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Byte strobe mode

#1 : 1

Single write strobe mode

End of enumeration elements list.

EWENB : External Wait Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PRENB : Page Read Access Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PWENB : Page Write Access Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

PRMOD : Page Read Access Mode Select
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal access compatible mode

#1 : 1

External data read continuous assertion mode

End of enumeration elements list.


BUSERR[BUS10]-BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD

Bus Error Address Register
address_offset : 0xF2D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS10]-BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD BUSERR[BUS10]-BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-ADD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BERAD

BERAD : Bus Error AddressWhen a bus error occurs, It stores an error address.
bits : 0 - 30 (31 bit)
access : read-only


BUSERR[BUS10]-BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT

Bus Error Status Register
address_offset : 0xF2D4 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSERR[BUS10]-BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT BUSERR[BUS10]-BUSERR[BUS9]-BUSERR[BUS8]-BUSERR[BUS7]-BUSERR[BUS6]-BUSERR[BUS5]-BUSERR[BUS4]-BUSERR[BUS3]-BUSERR[BUS2]-BUSERR[BUS1]-STAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACCSTAT ERRSTAT

ACCSTAT : Error access statusThe status at the time of the error
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

Read access

#1 : 1

Write Access

End of enumeration elements list.

ERRSTAT : Bus Error StatusWhen bus error assert, error flag occurs.
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

No bus error occurred

#1 : 1

Bus error occurred

End of enumeration elements list.


CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR1

Wait Control Register 1
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR1 CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSPWWAIT CSPRWAIT CSWWAIT CSRWAIT

CSPWWAIT : Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSPRWAIT : Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSWWAIT : Normal Write Cycle Wait Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

End of enumeration elements list.

CSRWAIT : Normal Read Cycle Wait Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x00 : 0x00

No wait is inserted.

End of enumeration elements list.


CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR2

Wait Control Register 2
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR2 CSa[5]-CSa[4]-CSa[3]-CSa[2]-CSa[1]-CSa[0]-WCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSROFF CSWOFF WDOFF AWAIT RDON WRON WDON CSON

CSROFF : Read-Access CS Extension Cycle Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSWOFF : Write-Access CS Extension Cycle Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WDOFF : Write Data Output Extension Cycle Select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

AWAIT : CS Assert Wait Select
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

RDON : RD Assert Wait Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WRON : WR Assert Wait Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

WDON : Write Data Output Wait Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.

CSON : CS Assert Wait Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 0x0

No wait is inserted.

End of enumeration elements list.



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