\n

TAUD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TAUDCDR0

TAUDCDR4

TAUDCDR5

TAUDCSR0

TAUDCSR1

TAUDCSR2

TAUDCSR3

TAUDCSR4

TAUDCSR5

TAUDCSR6

TAUDCSR7

TAUDCSR8

TAUDCSR9

TAUDCSR10

TAUDCSR11

TAUDCSR12

TAUDCSR13

TAUDCSR14

TAUDCSR15

TAUDCDR6

TAUDCSC0

TAUDCSC1

TAUDCSC2

TAUDCSC3

TAUDCSC4

TAUDCSC5

TAUDCSC6

TAUDCSC7

TAUDCSC8

TAUDCSC9

TAUDCSC10

TAUDCSC11

TAUDCSC12

TAUDCSC13

TAUDCSC14

TAUDCSC15

TAUDCDR7

TAUDTE

TAUDTS

TAUDTT

TAUDCDR8

TAUDCMOR0

TAUDCMOR1

TAUDCMOR2

TAUDCMOR3

TAUDCMOR4

TAUDCMOR5

TAUDCMOR6

TAUDCMOR7

TAUDCMOR8

TAUDCMOR9

TAUDCMOR10

TAUDCMOR11

TAUDCMOR12

TAUDCMOR13

TAUDCMOR14

TAUDCMOR15

TAUDCDR9

TAUDTPS

TAUDBRS

TAUDTOM

TAUDTOC

TAUDTDE

TAUDTDM

TAUDTRE

TAUDTRC

TAUDRDE

TAUDRDM

TAUDRDS

TAUDRDC

TAUDCDR10

TAUDEMU

TAUDCDR11

TAUDCDR12

TAUDCDR13

TAUDCDR14

TAUDCDR15

TAUDCDR1

TAUDTOL

TAUDRDT

TAUDRSF

TAUDTRO

TAUDTME

TAUDTDL

TAUDTO

TAUDTOE

TAUDCDR2

TAUDCNT0

TAUDCNT1

TAUDCNT2

TAUDCNT3

TAUDCNT4

TAUDCNT5

TAUDCNT6

TAUDCNT7

TAUDCNT8

TAUDCNT9

TAUDCNT10

TAUDCNT11

TAUDCNT12

TAUDCNT13

TAUDCNT14

TAUDCNT15

TAUDCDR3

TAUDCMUR0

TAUDCMUR1

TAUDCMUR2

TAUDCMUR3

TAUDCMUR4

TAUDCMUR5

TAUDCMUR6

TAUDCMUR7

TAUDCMUR8

TAUDCMUR9

TAUDCMUR10

TAUDCMUR11

TAUDCMUR12

TAUDCMUR13

TAUDCMUR14

TAUDCMUR15


TAUDCDR0

Channel Data Register m
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCDR0 TAUDCDR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCDR4

Channel Data Register m
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCDR4 TAUDCDR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCDR5

Channel Data Register m
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCDR5 TAUDCDR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCSR0

Channel Status Register m
address_offset : 0x140 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSR0 TAUDCSR0 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSR1

Channel Status Register m
address_offset : 0x144 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSR1 TAUDCSR1 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSR2

Channel Status Register m
address_offset : 0x148 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSR2 TAUDCSR2 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSR3

Channel Status Register m
address_offset : 0x14C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSR3 TAUDCSR3 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSR4

Channel Status Register m
address_offset : 0x150 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSR4 TAUDCSR4 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSR5

Channel Status Register m
address_offset : 0x154 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSR5 TAUDCSR5 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSR6

Channel Status Register m
address_offset : 0x158 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSR6 TAUDCSR6 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSR7

Channel Status Register m
address_offset : 0x15C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSR7 TAUDCSR7 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSR8

Channel Status Register m
address_offset : 0x160 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSR8 TAUDCSR8 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSR9

Channel Status Register m
address_offset : 0x164 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSR9 TAUDCSR9 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSR10

Channel Status Register m
address_offset : 0x168 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSR10 TAUDCSR10 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSR11

Channel Status Register m
address_offset : 0x16C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSR11 TAUDCSR11 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSR12

Channel Status Register m
address_offset : 0x170 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSR12 TAUDCSR12 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSR13

Channel Status Register m
address_offset : 0x174 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSR13 TAUDCSR13 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSR14

Channel Status Register m
address_offset : 0x178 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSR14 TAUDCSR14 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSR15

Channel Status Register m
address_offset : 0x17C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSR15 TAUDCSR15 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCDR6

Channel Data Register m
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCDR6 TAUDCDR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCSC0

Channel Status Clear Trigger Register m
address_offset : 0x180 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSC0 TAUDCSC0 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSC1

Channel Status Clear Trigger Register m
address_offset : 0x184 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSC1 TAUDCSC1 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSC2

Channel Status Clear Trigger Register m
address_offset : 0x188 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSC2 TAUDCSC2 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSC3

Channel Status Clear Trigger Register m
address_offset : 0x18C Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSC3 TAUDCSC3 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSC4

Channel Status Clear Trigger Register m
address_offset : 0x190 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSC4 TAUDCSC4 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSC5

Channel Status Clear Trigger Register m
address_offset : 0x194 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSC5 TAUDCSC5 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSC6

Channel Status Clear Trigger Register m
address_offset : 0x198 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSC6 TAUDCSC6 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSC7

Channel Status Clear Trigger Register m
address_offset : 0x19C Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSC7 TAUDCSC7 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSC8

Channel Status Clear Trigger Register m
address_offset : 0x1A0 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSC8 TAUDCSC8 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSC9

Channel Status Clear Trigger Register m
address_offset : 0x1A4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSC9 TAUDCSC9 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSC10

Channel Status Clear Trigger Register m
address_offset : 0x1A8 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSC10 TAUDCSC10 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSC11

Channel Status Clear Trigger Register m
address_offset : 0x1AC Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSC11 TAUDCSC11 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSC12

Channel Status Clear Trigger Register m
address_offset : 0x1B0 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSC12 TAUDCSC12 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSC13

Channel Status Clear Trigger Register m
address_offset : 0x1B4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSC13 TAUDCSC13 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSC14

Channel Status Clear Trigger Register m
address_offset : 0x1B8 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSC14 TAUDCSC14 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCSC15

Channel Status Clear Trigger Register m
address_offset : 0x1BC Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCSC15 TAUDCSC15 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCDR7

Channel Data Register m
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCDR7 TAUDCDR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDTE

Channel Authorized Status Register
address_offset : 0x1C0 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDTE TAUDTE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDTS

Channel Start Trigger Register
address_offset : 0x1C4 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUDTS TAUDTS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDTT

Channel Stop Trigger Register
address_offset : 0x1C8 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUDTT TAUDTT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCDR8

Channel Data Register m
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCDR8 TAUDCDR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCMOR0

Channel Mode OS Register m
address_offset : 0x200 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMOR0 TAUDCMOR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCMOR1

Channel Mode OS Register m
address_offset : 0x204 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMOR1 TAUDCMOR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCMOR2

Channel Mode OS Register m
address_offset : 0x208 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMOR2 TAUDCMOR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCMOR3

Channel Mode OS Register m
address_offset : 0x20C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMOR3 TAUDCMOR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCMOR4

Channel Mode OS Register m
address_offset : 0x210 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMOR4 TAUDCMOR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCMOR5

Channel Mode OS Register m
address_offset : 0x214 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMOR5 TAUDCMOR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCMOR6

Channel Mode OS Register m
address_offset : 0x218 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMOR6 TAUDCMOR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCMOR7

Channel Mode OS Register m
address_offset : 0x21C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMOR7 TAUDCMOR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCMOR8

Channel Mode OS Register m
address_offset : 0x220 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMOR8 TAUDCMOR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCMOR9

Channel Mode OS Register m
address_offset : 0x224 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMOR9 TAUDCMOR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCMOR10

Channel Mode OS Register m
address_offset : 0x228 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMOR10 TAUDCMOR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCMOR11

Channel Mode OS Register m
address_offset : 0x22C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMOR11 TAUDCMOR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCMOR12

Channel Mode OS Register m
address_offset : 0x230 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMOR12 TAUDCMOR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCMOR13

Channel Mode OS Register m
address_offset : 0x234 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMOR13 TAUDCMOR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCMOR14

Channel Mode OS Register m
address_offset : 0x238 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMOR14 TAUDCMOR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCMOR15

Channel Mode OS Register m
address_offset : 0x23C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMOR15 TAUDCMOR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCDR9

Channel Data Register m
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCDR9 TAUDCDR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDTPS

Prescaler Clock Selected Register
address_offset : 0x240 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDTPS TAUDTPS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDBRS

Prescaler Baudrate setting Register
address_offset : 0x244 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDBRS TAUDBRS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDTOM

Channel Output Mode Register
address_offset : 0x248 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDTOM TAUDTOM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDTOC

Channel Output Configuration Register
address_offset : 0x24C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDTOC TAUDTOC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDTDE

Channel Dead Time Output Authorized Register
address_offset : 0x250 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDTDE TAUDTDE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDTDM

Channel Dead Time Output Mode Register
address_offset : 0x254 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDTDM TAUDTDM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDTRE

Channel Real Time Output Authorized Register
address_offset : 0x258 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDTRE TAUDTRE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDTRC

Channel Real Time Output Control Register
address_offset : 0x25C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDTRC TAUDTRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDRDE

Channel Reload data Authorized Register
address_offset : 0x260 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDRDE TAUDRDE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDRDM

Channel Reload data Mode Register
address_offset : 0x264 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDRDM TAUDRDM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDRDS

Channel Reload data Control CH Selected Register
address_offset : 0x268 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDRDS TAUDRDS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDRDC

Channel Reload data Control Register
address_offset : 0x26C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDRDC TAUDRDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCDR10

Channel Data Register m
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCDR10 TAUDCDR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDEMU

Emulation Register
address_offset : 0x290 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDEMU TAUDEMU read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCDR11

Channel Data Register m
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCDR11 TAUDCDR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCDR12

Channel Data Register m
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCDR12 TAUDCDR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCDR13

Channel Data Register m
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCDR13 TAUDCDR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCDR14

Channel Data Register m
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCDR14 TAUDCDR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCDR15

Channel Data Register m
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCDR15 TAUDCDR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCDR1

Channel Data Register m
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCDR1 TAUDCDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDTOL

Channel Output Active Level Register
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDTOL TAUDTOL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDRDT

Channel Reload data Trigger Register
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TAUDRDT TAUDRDT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDRSF

Channel Reload Status Register
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDRSF TAUDRSF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDTRO

Channel Real Time Output Register
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDTRO TAUDTRO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDTME

Channel Modulation Output Authorized Register
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDTME TAUDTME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDTDL

Channel Dead Time Output Level Register
address_offset : 0x54 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDTDL TAUDTDL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDTO

Channel Output Register
address_offset : 0x58 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDTO TAUDTO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDTOE

Channel Output Authorized Register
address_offset : 0x5C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDTOE TAUDTOE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCDR2

Channel Data Register m
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCDR2 TAUDCDR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCNT0

Channel Counter Register m
address_offset : 0x80 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCNT0 TAUDCNT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCNT1

Channel Counter Register m
address_offset : 0x84 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCNT1 TAUDCNT1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCNT2

Channel Counter Register m
address_offset : 0x88 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCNT2 TAUDCNT2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCNT3

Channel Counter Register m
address_offset : 0x8C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCNT3 TAUDCNT3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCNT4

Channel Counter Register m
address_offset : 0x90 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCNT4 TAUDCNT4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCNT5

Channel Counter Register m
address_offset : 0x94 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCNT5 TAUDCNT5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCNT6

Channel Counter Register m
address_offset : 0x98 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCNT6 TAUDCNT6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCNT7

Channel Counter Register m
address_offset : 0x9C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCNT7 TAUDCNT7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCNT8

Channel Counter Register m
address_offset : 0xA0 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCNT8 TAUDCNT8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCNT9

Channel Counter Register m
address_offset : 0xA4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCNT9 TAUDCNT9 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCNT10

Channel Counter Register m
address_offset : 0xA8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCNT10 TAUDCNT10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCNT11

Channel Counter Register m
address_offset : 0xAC Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCNT11 TAUDCNT11 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCNT12

Channel Counter Register m
address_offset : 0xB0 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCNT12 TAUDCNT12 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCNT13

Channel Counter Register m
address_offset : 0xB4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCNT13 TAUDCNT13 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCNT14

Channel Counter Register m
address_offset : 0xB8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCNT14 TAUDCNT14 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCNT15

Channel Counter Register m
address_offset : 0xBC Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAUDCNT15 TAUDCNT15 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCDR3

Channel Data Register m
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCDR3 TAUDCDR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TAUDCMUR0

Channel Mode User Register m
address_offset : 0xC0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMUR0 TAUDCMUR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCMUR1

Channel Mode User Register m
address_offset : 0xC4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMUR1 TAUDCMUR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCMUR2

Channel Mode User Register m
address_offset : 0xC8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMUR2 TAUDCMUR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCMUR3

Channel Mode User Register m
address_offset : 0xCC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMUR3 TAUDCMUR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCMUR4

Channel Mode User Register m
address_offset : 0xD0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMUR4 TAUDCMUR4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCMUR5

Channel Mode User Register m
address_offset : 0xD4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMUR5 TAUDCMUR5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCMUR6

Channel Mode User Register m
address_offset : 0xD8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMUR6 TAUDCMUR6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCMUR7

Channel Mode User Register m
address_offset : 0xDC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMUR7 TAUDCMUR7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCMUR8

Channel Mode User Register m
address_offset : 0xE0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMUR8 TAUDCMUR8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCMUR9

Channel Mode User Register m
address_offset : 0xE4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMUR9 TAUDCMUR9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCMUR10

Channel Mode User Register m
address_offset : 0xE8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMUR10 TAUDCMUR10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCMUR11

Channel Mode User Register m
address_offset : 0xEC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMUR11 TAUDCMUR11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCMUR12

Channel Mode User Register m
address_offset : 0xF0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMUR12 TAUDCMUR12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCMUR13

Channel Mode User Register m
address_offset : 0xF4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMUR13 TAUDCMUR13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCMUR14

Channel Mode User Register m
address_offset : 0xF8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMUR14 TAUDCMUR14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TAUDCMUR15

Channel Mode User Register m
address_offset : 0xFC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAUDCMUR15 TAUDCMUR15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0


Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.