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R_CTSU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1E byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTSUCR0

CTSUCR1

CTSUDCLKC

CTSUST

CTSUSSC

CTSUCHAC[1]

CTSUSO0

CTSUCHTRC[0]

CTSUSO1

CTSUSC

CTSURC

CTSUCHAC[2]

CTSUERRS

CTSUSDPRS

CTSUCHTRC[1]

CTSUCHAC[3]

CTSUCHAC[4]

CTSUCHTRC[2]

CTSUSST

CTSUCHTRC[3]

CTSUMCH0

CTSUCHTRC[4]

CTSUMCH1

CTSUCHAC0

CTSUCHAC1

CTSUCHAC2

CTSUCHAC3

CTSUCHAC4

CTSUCHTRC0

CTSUCHAC[0]

CTSUCHTRC1

CTSUCHTRC2

CTSUCHTRC3

CTSUCHTRC4


CTSUCR0

CTSU Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCR0 CTSUCR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CTSUSTRT CTSUCAP CTSUSNZ CTSUIOC CTSUINIT CTSUTXVSEL

CTSUSTRT : CTSU Measurement Operation Start
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Measurement operation stops.

#1 : 1

Measurement operation starts.

End of enumeration elements list.

CTSUCAP : CTSU Measurement Operation Start Trigger Select
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Software trigger.

#1 : 1

External trigger.

End of enumeration elements list.

CTSUSNZ : CTSU Wait State Power-Saving Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Power-saving function during wait state is disabled.

#1 : 1

Power-saving function during wait state is enabled.

End of enumeration elements list.

CTSUIOC : CTSU Transmit Pin Control
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Low-level output from transmit channel non-measurement pin.

#1 : 1

High-level output from transmit channel non-measurement pin.

End of enumeration elements list.

CTSUINIT : CTSU Control Block Initialization
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Writing a 0 has no effect, this bit is read as 0.

#1 : 1

initializes the CTSU control block and registers.

End of enumeration elements list.

CTSUTXVSEL : CTSU Transmission power supply selection
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Select Vcc

#1 : 1

Select internal logic power supply

End of enumeration elements list.


CTSUCR1

CTSU Control Register 1
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCR1 CTSUCR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CTSUPON CTSUCSW CTSUATUNE0 CTSUATUNE1 CTSUCLK CTSUMD

CTSUPON : CTSU Power Supply Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Powered off the CTSU

#1 : 1

Powered on the CTSU

End of enumeration elements list.

CTSUCSW : CTSU LPF Capacitance Charging Control
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Turned off capacitance switch

#1 : 1

Turned on capacitance switch

End of enumeration elements list.

CTSUATUNE0 : CTSU Power Supply Operating Mode Setting
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal operating mode

#1 : 1

Low-voltage operating mode

End of enumeration elements list.

CTSUATUNE1 : CTSU Power Supply Capacity Adjustment
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Normal output

#1 : 1

High-current output

End of enumeration elements list.

CTSUCLK : CTSU Operating Clock Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

PCLK

#01 : 01

PCLK/2 (PCLK divided by 2)

#10 : 10

PCLK/2 (PCLK divided by 4)

#11 : 11

Setting prohibited

End of enumeration elements list.

CTSUMD : CTSU Measurement Mode Select
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : 00

Self-capacitance single scan mode

#01 : 01

Self-capacitance multi-scan mode

#10 : 10

Mutual capacitance simple scan mode

#11 : 11

Mutual capacitance full scan mode

End of enumeration elements list.


CTSUDCLKC

CTSU High-Pass Noise Reduction Control Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUDCLKC CTSUDCLKC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CTSUSSMOD CTSUSSCNT

CTSUSSMOD : CTSU Diffusion Clock Mode SelectNOTE: This bit should be set to 00b.
bits : 0 - 0 (1 bit)
access : read-write

CTSUSSCNT : CTSU Diffusion Clock Mode ControlNOTE: This bit should be set to 11b.
bits : 4 - 4 (1 bit)
access : read-write


CTSUST

CTSU Status Register
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUST CTSUST read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CTSUSTC CTSUDTSR CTSUSOVF CTSUROVF CTSUPS

CTSUSTC : CTSU Measurement Status Counter
bits : 0 - 1 (2 bit)
access : read-only

Enumeration:

#000 : 000

Status 0

#001 : 001

Status 1

#010 : 010

Status 2

#011 : 011

Status 3

#100 : 100

Status 4

#101 : 101

Status 5

End of enumeration elements list.

CTSUDTSR : CTSU Data Transfer Status Flag
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

Measurement result has been read

#1 : 1

Measurement result has not been read

End of enumeration elements list.

CTSUSOVF : CTSU Sensor Counter Overflow Flag
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

No overflow

#1 : 1

An overflow

End of enumeration elements list.

CTSUROVF : CTSU Reference Counter Overflow Flag
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

No overflow

#1 : 1

An overflow

End of enumeration elements list.

CTSUPS : CTSU Mutual Capacitance Status Flag
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : 0

First measurement

#1 : 1

Second measurement

End of enumeration elements list.


CTSUSSC

CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUSSC CTSUSSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTSUSSDIV

CTSUSSDIV : CTSU Spectrum Diffusion Frequency Division Setting
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#0000 : 0000

4.00 <= fb

#0001 : 0001

2.00 <= fb < 4.00

#0010 : 0010

1.33 <= fb < 2.00

#0011 : 0011

1.00 <= fb < 1.33

#0100 : 0100

0.80 <= fb < 1.00

#0101 : 0101

0.67 <= fb < 0.80

#0110 : 0110

0.57 <= fb < 0.67

#0111 : 0111

0.50 <= fb < 0.57

#1000 : 1000

0.44 <= fb < 0.50

#1001 : 1001

0.40 <= fb < 0.44

#1010 : 1010

0.36 <= fb < 0.40

#1011 : 1011

0.33 <= fb < 0.36

#1100 : 1100

0.31 <= fb < 0.33

#1101 : 1101

0.29 <= fb < 0.31

#1110 : 1110

0.27 <= fb < 0.29

#1111 : 1111

fb < 0.27

End of enumeration elements list.


CTSUCHAC[1]

CTSU Channel Enable Control Register
address_offset : 0x13 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHAC[1] CTSUCHAC[1] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS7

TS7 : CTSU Channel Enable Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.


CTSUSO0

CTSU Sensor Offset Register 0
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUSO0 CTSUSO0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTSUSO CTSUSNUM

CTSUSO : CTSU Sensor Offset AdjustmentCurrent offset amount is CTSUSO ( 0 to 1023 )
bits : 0 - 8 (9 bit)
access : read-write

CTSUSNUM : CTSU Measurement Count Setting
bits : 10 - 14 (5 bit)
access : read-write


CTSUCHTRC[0]

CTSU Channel Transmit/Receive Control Register
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHTRC[0] CTSUCHTRC[0] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7

TS0 : CTSU Channel Transmit/Receive Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS1 : CTSU Channel Transmit/Receive Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS2 : CTSU Channel Transmit/Receive Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS3 : CTSU Channel Transmit/Receive Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS4 : CTSU Channel Transmit/Receive Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS5 : CTSU Channel Transmit/Receive Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS6 : CTSU Channel Transmit/Receive Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS7 : CTSU Channel Transmit/Receive Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.


CTSUSO1

CTSU Sensor Offset Register 1
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUSO1 CTSUSO1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTSURICOA CTSUSDPA CTSUICOG

CTSURICOA : CTSU Reference ICO Current AdjustmentCurrent offset amount is CTSUSO ( 0 to 255 )
bits : 0 - 6 (7 bit)
access : read-write

CTSUSDPA : CTSU Base Clock SettingOperating clock divided by ( CTSUSDPA + 1 ) x 2
bits : 8 - 11 (4 bit)
access : read-write

CTSUICOG : CTSU ICO Gain Adjustment
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#00 : 00

100 percent gain

#01 : 01

66 percent gain

#10 : 10

50 percent gain

#11 : 11

40 percent gain

End of enumeration elements list.


CTSUSC

CTSU Sensor Counter
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CTSUSC CTSUSC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTSUSC

CTSUSC : CTSU Sensor CounterThese bits indicate the measurement result of the CTSU. These bits indicate FFFFh when an overflow occurs.
bits : 0 - 14 (15 bit)
access : read-only


CTSURC

CTSU Reference Counter
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CTSURC CTSURC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTSURC

CTSURC : CTSU Reference CounterThese bits indicate the measurement result of the reference ICO.These bits indicate FFFFh when an overflow occurs.
bits : 0 - 14 (15 bit)
access : read-only


CTSUCHAC[2]

CTSU Channel Enable Control Register
address_offset : 0x1B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHAC[2] CTSUCHAC[2] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS7

TS7 : CTSU Channel Enable Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.


CTSUERRS

CTSU Error Status Register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CTSUERRS CTSUERRS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTSUICOMP

CTSUICOMP : TSCAP Voltage Error Monitor
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : 0

Normal TSCAP voltage

#1 : 1

Abnormal TSCAP voltage

End of enumeration elements list.


CTSUSDPRS

CTSU Synchronous Noise Reduction Setting Register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUSDPRS CTSUSDPRS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CTSUPRRATIO CTSUPRMODE CTSUSOFF

CTSUPRRATIO : CTSU Measurement Time and Pulse Count AdjustmentRecommended setting: 3 (0011b)
bits : 0 - 2 (3 bit)
access : read-write

CTSUPRMODE : CTSU Base Period and Pulse Count Setting
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : 00

510 pulses

#01 : 01

126 pulses

#10 : 10

62 pulses (recommended setting value)

#11 : 11

Setting prohibited

End of enumeration elements list.

CTSUSOFF : CTSU High-Pass Noise Reduction Function Off Setting
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

High-pass noise reduction function turned on

#1 : 1

High-pass noise reduction function turned off

End of enumeration elements list.


CTSUCHTRC[1]

CTSU Channel Transmit/Receive Control Register
address_offset : 0x22 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHTRC[1] CTSUCHTRC[1] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS7

TS7 : CTSU Channel Transmit/Receive Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.


CTSUCHAC[3]

CTSU Channel Enable Control Register
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHAC[3] CTSUCHAC[3] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS7

TS7 : CTSU Channel Enable Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.


CTSUCHAC[4]

CTSU Channel Enable Control Register
address_offset : 0x2E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHAC[4] CTSUCHAC[4] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS7

TS7 : CTSU Channel Enable Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.


CTSUCHTRC[2]

CTSU Channel Transmit/Receive Control Register
address_offset : 0x2F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHTRC[2] CTSUCHTRC[2] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS7

TS7 : CTSU Channel Transmit/Receive Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.


CTSUSST

CTSU Sensor Stabilization Wait Control Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUSST CTSUSST read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CTSUSST

CTSUSST : CTSU Sensor Stabilization Wait ControlNOTE: The value of these bits should be fixed to 00010000b.
bits : 0 - 6 (7 bit)
access : read-write


CTSUCHTRC[3]

CTSU Channel Transmit/Receive Control Register
address_offset : 0x3D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHTRC[3] CTSUCHTRC[3] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS7

TS7 : CTSU Channel Transmit/Receive Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.


CTSUMCH0

CTSU Measurement Channel Register 0
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUMCH0 CTSUMCH0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CTSUMCH0

CTSUMCH0 : CTSU Measurement Channel 0.Note1: Writing to these bits is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] bits = 00b).Note2: If the value of CTSUMCH0 was set to b'111111 in mode other than self-capacitor single scan mode, the measurement is stopped.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : TS0

measured TS0

1 : TS1

measured TS1

2 : TS2

measured TS2

3 : TS3

measured TS3

4 : TS4

measured TS4

5 : TS5

measured TS5

6 : TS6

measured TS6

7 : TS7

measured TS7

8 : TS8

measured TS8

9 : TS9

measured TS9

10 : TS10

measured TS10

11 : TS11

measured TS11

12 : TS12

measured TS12

13 : TS13

measured TS13

14 : TS14

measured TS14

15 : TS15

measured TS15

16 : TS16

measured TS16

17 : TS17

measured TS17

18 : TS18

measured TS18

19 : TS19

measured TS19

20 : TS20

measured TS20

21 : TS21

measured TS21

22 : TS22

measured TS22

23 : TS23

measured TS23

24 : TS24

measured TS24

25 : TS25

measured TS25

26 : TS26

measured TS26

27 : TS27

measured TS27

28 : TS28

measured TS28

29 : TS29

measured TS29

30 : TS30

measured TS30

31 : TS31

measured TS31

32 : TS32

measured TS32

33 : TS33

measured TS33

34 : TS34

measured TS34

35 : TS35

measured TS35

#111111 : STOP

Conversion Stopped

End of enumeration elements list.


CTSUCHTRC[4]

CTSU Channel Transmit/Receive Control Register
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHTRC[4] CTSUCHTRC[4] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS7

TS7 : CTSU Channel Transmit/Receive Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.


CTSUMCH1

CTSU Measurement Channel Register 1
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUMCH1 CTSUMCH1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CTSUMCH1

CTSUMCH1 : CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 was set to b'111111, the measurement is stopped.
bits : 0 - 4 (5 bit)
access : read-only

Enumeration:

0 : TS0

measured TS0

1 : TS1

measured TS1

2 : TS2

measured TS2

3 : TS3

measured TS3

4 : TS4

measured TS4

5 : TS5

measured TS5

6 : TS6

measured TS6

7 : TS7

measured TS7

8 : TS8

measured TS8

9 : TS9

measured TS9

10 : TS10

measured TS10

11 : TS11

measured TS11

12 : TS12

measured TS12

13 : TS13

measured TS13

14 : TS14

measured TS14

15 : TS15

measured TS15

16 : TS16

measured TS16

17 : TS17

measured TS17

18 : TS18

measured TS18

19 : TS19

measured TS19

20 : TS20

measured TS20

21 : TS21

measured TS21

22 : TS22

measured TS22

23 : TS23

measured TS23

24 : TS24

measured TS24

25 : TS25

measured TS25

26 : TS26

measured TS26

27 : TS27

measured TS27

28 : TS28

measured TS28

29 : TS29

measured TS29

30 : TS30

measured TS30

31 : TS31

measured TS31

32 : TS32

measured TS32

33 : TS33

measured TS33

34 : TS34

measured TS34

35 : TS35

measured TS35

#111111 : STOP

Conversion Stopped

End of enumeration elements list.


CTSUCHAC0

CTSU Channel Enable Control Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHAC0 CTSUCHAC0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7

TS0 : CTSU Channel Enable Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS1 : CTSU Channel Enable Control
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS2 : CTSU Channel Enable Control
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS3 : CTSU Channel Enable Control
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS4 : CTSU Channel Enable Control
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS5 : CTSU Channel Enable Control
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS6 : CTSU Channel Enable Control
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS7 : CTSU Channel Enable Control
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.


CTSUCHAC1

CTSU Channel Enable Control Register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHAC1 CTSUCHAC1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7

TS0 : CTSU Channel Enable Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS1 : CTSU Channel Enable Control
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS2 : CTSU Channel Enable Control
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS3 : CTSU Channel Enable Control
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS4 : CTSU Channel Enable Control
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS5 : CTSU Channel Enable Control
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS6 : CTSU Channel Enable Control
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS7 : CTSU Channel Enable Control
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.


CTSUCHAC2

CTSU Channel Enable Control Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHAC2 CTSUCHAC2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7

TS0 : CTSU Channel Enable Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS1 : CTSU Channel Enable Control
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS2 : CTSU Channel Enable Control
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS3 : CTSU Channel Enable Control
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS4 : CTSU Channel Enable Control
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS5 : CTSU Channel Enable Control
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS6 : CTSU Channel Enable Control
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS7 : CTSU Channel Enable Control
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.


CTSUCHAC3

CTSU Channel Enable Control Register
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHAC3 CTSUCHAC3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7

TS0 : CTSU Channel Enable Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS1 : CTSU Channel Enable Control
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS2 : CTSU Channel Enable Control
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS3 : CTSU Channel Enable Control
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS4 : CTSU Channel Enable Control
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS5 : CTSU Channel Enable Control
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS6 : CTSU Channel Enable Control
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS7 : CTSU Channel Enable Control
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.


CTSUCHAC4

CTSU Channel Enable Control Register
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHAC4 CTSUCHAC4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7

TS0 : CTSU Channel Enable Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS1 : CTSU Channel Enable Control
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS2 : CTSU Channel Enable Control
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS3 : CTSU Channel Enable Control
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS4 : CTSU Channel Enable Control
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS5 : CTSU Channel Enable Control
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS6 : CTSU Channel Enable Control
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS7 : CTSU Channel Enable Control
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.


CTSUCHTRC0

CTSU Channel Transmit/Receive Control Register
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHTRC0 CTSUCHTRC0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7

TS0 : CTSU Channel Transmit/Receive Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS1 : CTSU Channel Transmit/Receive Control
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS2 : CTSU Channel Transmit/Receive Control
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS3 : CTSU Channel Transmit/Receive Control
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS4 : CTSU Channel Transmit/Receive Control
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS5 : CTSU Channel Transmit/Receive Control
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS6 : CTSU Channel Transmit/Receive Control
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS7 : CTSU Channel Transmit/Receive Control
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.


CTSUCHAC[0]

CTSU Channel Enable Control Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHAC[0] CTSUCHAC[0] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7

TS0 : CTSU Channel Enable Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS1 : CTSU Channel Enable Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS2 : CTSU Channel Enable Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS3 : CTSU Channel Enable Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS4 : CTSU Channel Enable Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS5 : CTSU Channel Enable Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS6 : CTSU Channel Enable Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.

TS7 : CTSU Channel Enable Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0 : 0

Do not measure

1 : 1

Measure

End of enumeration elements list.


CTSUCHTRC1

CTSU Channel Transmit/Receive Control Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHTRC1 CTSUCHTRC1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7

TS0 : CTSU Channel Transmit/Receive Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS1 : CTSU Channel Transmit/Receive Control
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS2 : CTSU Channel Transmit/Receive Control
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS3 : CTSU Channel Transmit/Receive Control
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS4 : CTSU Channel Transmit/Receive Control
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS5 : CTSU Channel Transmit/Receive Control
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS6 : CTSU Channel Transmit/Receive Control
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS7 : CTSU Channel Transmit/Receive Control
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.


CTSUCHTRC2

CTSU Channel Transmit/Receive Control Register
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHTRC2 CTSUCHTRC2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7

TS0 : CTSU Channel Transmit/Receive Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS1 : CTSU Channel Transmit/Receive Control
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS2 : CTSU Channel Transmit/Receive Control
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS3 : CTSU Channel Transmit/Receive Control
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS4 : CTSU Channel Transmit/Receive Control
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS5 : CTSU Channel Transmit/Receive Control
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS6 : CTSU Channel Transmit/Receive Control
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS7 : CTSU Channel Transmit/Receive Control
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.


CTSUCHTRC3

CTSU Channel Transmit/Receive Control Register
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHTRC3 CTSUCHTRC3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7

TS0 : CTSU Channel Transmit/Receive Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS1 : CTSU Channel Transmit/Receive Control
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS2 : CTSU Channel Transmit/Receive Control
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS3 : CTSU Channel Transmit/Receive Control
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS4 : CTSU Channel Transmit/Receive Control
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS5 : CTSU Channel Transmit/Receive Control
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS6 : CTSU Channel Transmit/Receive Control
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS7 : CTSU Channel Transmit/Receive Control
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.


CTSUCHTRC4

CTSU Channel Transmit/Receive Control Register
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTSUCHTRC4 CTSUCHTRC4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7

TS0 : CTSU Channel Transmit/Receive Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS1 : CTSU Channel Transmit/Receive Control
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS2 : CTSU Channel Transmit/Receive Control
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS3 : CTSU Channel Transmit/Receive Control
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS4 : CTSU Channel Transmit/Receive Control
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS5 : CTSU Channel Transmit/Receive Control
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS6 : CTSU Channel Transmit/Receive Control
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.

TS7 : CTSU Channel Transmit/Receive Control
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Reception

#1 : 1

Transmission

End of enumeration elements list.



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