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R_DAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xA byte (0x0)
mem_usage : registers
protection : not protected

Registers

DADR[0]

DADR0

DAADUSR

DAASWCR

DADR[1]

DADR1

DACR

DADPR

DAADSCR

DAVREFCR

DAAMPCR

DAPC


DADR[0]

D/A Data Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DADR[0] DADR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DADR

DADR : D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order 4 bits are fixed to 0: right justified format. When DADPR.DPSEL = 1, the low-order 4 bits are fixed to 0: left justified format.
bits : 0 - 14 (15 bit)
access : read-write


DADR0

D/A Data Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DADR0 DADR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DADR

DADR : D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order 4 bits are fixed to 0: right justified format. When DADPR.DPSEL = 1, the low-order 4 bits are fixed to 0: left justified format.
bits : 0 - 14 (15 bit)
access : read-write


DAADUSR

D/A A/D Synchronous Unit Select Register
address_offset : 0x10C0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAADUSR DAADUSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AMADSEL1

AMADSEL1 : The DAADUSR register selects the target ADC12 unit for D/A and A/D synchronous conversions. Set bit [1] to 1 to select unit 1 as the target synchronous unit for the MCU. When setting the DAADSCR.DAADST bit to 1 for synchronous conversions, select the target unit in this register in advance. Only set the DAADUSR register while the ADCSR.ADST bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit is set to 0.
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not select unit 1

#1 : 1

Select unit 1

End of enumeration elements list.


DAASWCR

D/A Amplifier Stabilization Wait Control Register
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAASWCR DAASWCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DAASW0 DAASW1

DAASW0 : Set the DAASW0 bit to 1 in the initialization procedure to wait for stabilization of the output amplifier of D/A channel 0. When DAASW0 is set to 1, D/A conversion operates, but the conversion result D/A is not output from channel 0. When the DAASW0 bit is 0, the stabilization wait time stops, and the D/A conversion result of channel 0 is output through the output amplifier.
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Amplifier stabilization wait off (output) for channel 0

#1 : 1

Amplifier stabilization wait on (high-Z) for channel 0

End of enumeration elements list.

DAASW1 : Set the DAASW1 bit to 1 in the initialization procedure to wait for stabilization of the output amplifier of D/A channel 1. When DAASW1 is set to 1, D/A conversion operates, but the conversion result D/A is not output from channel 1. When the DAASW1 bit is 0, the stabilization wait time stops, and the D/A conversion result of channel 1 is output through the output amplifier.
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Amplifier stabilization wait off (output) for channel 1

#1 : 1

Amplifier stabilization wait on (high-Z) for channel 1

End of enumeration elements list.


DADR[1]

D/A Data Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DADR[1] DADR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DADR

DADR : D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order 4 bits are fixed to 0: right justified format. When DADPR.DPSEL = 1, the low-order 4 bits are fixed to 0: left justified format.
bits : 0 - 14 (15 bit)
access : read-write


DADR1

D/A Data Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DADR1 DADR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DADR

DADR : D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order 4 bits are fixed to 0: right justified format. When DADPR.DPSEL = 1, the low-order 4 bits are fixed to 0: left justified format.
bits : 0 - 14 (15 bit)
access : read-write


DACR

D/A Control Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DACR DACR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DAE DAOE0 DAOE1

DAE : D/A Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : 0

Control D/A conversion of channels 0 and 1 individually

End of enumeration elements list.

DAOE0 : D/A Output Enable 0
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Analog output of channel 0 (DA0) is disabled.

#1 : 1

D/A conversion of channel 0 is enabled. Analog output of channel 0 (DA0) is enabled.

End of enumeration elements list.

DAOE1 : D/A Output Enable 0
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Analog output of channel 0 (DA0) is disabled.

#1 : 1

D/A conversion of channel 0 is enabled. Analog output of channel 0 (DA0) is enabled.

End of enumeration elements list.


DADPR

DADR0 Format Select Register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DADPR DADPR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DPSEL

DPSEL : DADRm Format Select
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Right justified format.

#1 : 1

Left justified format.

End of enumeration elements list.


DAADSCR

D/A-A/D Synchronous Start Control Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAADSCR DAADSCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DAADST

DAADST : D/A-A/D Synchronous Conversion
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

D/A converter operation does not synchronize with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is disabled).

#1 : 1

D/A converter operation synchronizes with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is enabled).

End of enumeration elements list.


DAVREFCR

D/A VREF Control Register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAVREFCR DAVREFCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 REF

REF : D/A Reference Voltage Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : 000

Not selected

#001 : 001

AVCC0/AVSS0

#011 : 011

Internal reference voltage/AVSS0

#110 : 110

VREFH/VREFL

: others

Setting prohibited

End of enumeration elements list.


DAAMPCR

D/A Output Amplifier Control Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAAMPCR DAAMPCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DAAMP0 DAAMP1

DAAMP0 : Amplifier Control
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not use channel output amplifier

End of enumeration elements list.

DAAMP1 : Amplifier Control
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : 0

Do not use channel output amplifier

End of enumeration elements list.


DAPC

D/A Switch Charge Pump Control Register
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAPC DAPC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PUMPEN

PUMPEN : Charge Pump Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : 0

Charge pump disabled

#1 : 1

Charge pump enabled

End of enumeration elements list.



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