\n
address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x26 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1E Bytes (0x0)
size : 0x6 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x2E Bytes (0x0)
size : 0x6 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x36 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3A Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
DALI Bit Timing Violation Threshold Register 1
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTV1 : Bit Timing Violation Threshold 1Specifies the bit timing violation threshold value 1.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
bits : 0 - 5 (6 bit)
access : read-write
BTV2 : Bit Timing Violation Threshold 2Specifies the bit timing violation threshold value 2.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
bits : 8 - 14 (7 bit)
access : read-write
DALI Collision Threshold Register 5
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COL9 : Collision Threshold 9Specifies the collision threshold value 9.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
bits : 0 - 6 (7 bit)
access : read-write
DALI Configuration Register 1
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BR : Clock SelectBit rate setting example is shown in Table
bits : 0 - 6 (7 bit)
access : read-write
CKS : Clock Select
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : 00
PCLK clock (x = 0)
#01 : 01
PCLK/4 clock (x = 1)
#10 : 10
PCLK/16 clock (x = 2)
#11 : 11
PCLK/64 clock (x = 3)
End of enumeration elements list.
CHL : Character Length
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#000 : 000
8 bits
#001 : 001
16 bits
#010 : 010
24 bits
#011 : 011
32 bits
#100 : 100
20 bits
#101 : 101
17 bits
: others
Setting prohibited
End of enumeration elements list.
DALI Configuration Register 2
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTVE : Bit Timing Violation EnableNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0.
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Bit timing violation function is disabled.
#1 : 1
Bit timing violation function is enabled.
End of enumeration elements list.
BTVM : Bit Timing Violation ModeNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0.
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Edge in gray area between half bit and 2-half bit is not detected as bit timing violation.
#1 : 1
Edge in gray area between half bit and 2-half bit is detected as bit timing violation.
End of enumeration elements list.
SGA : Save an Edge of Gray Area ModeNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0.
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The edge allowable area of the DRX0 input signal is the default.
#1 : 1
The edge allowable area of the DRX0 input signal is extended.
End of enumeration elements list.
TXWE : DTX Width Modulation EnableNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0.
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
The width of DTX0 waveform is not modulated.
#1 : 1
The width of DTX0 waveform is modulated.
End of enumeration elements list.
CDE : Collision Detect EnableNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0.
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Collision detection is disabled.
#1 : 1
Collision detection is enabled.
End of enumeration elements list.
CDM0 : Collision Detect ModeNote: The bit must be modified only when the DALI0.STR1.BBF bit is 0.
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Destroy area
#1 : 1
Destroy area and avoidance area (edge)
End of enumeration elements list.
DALI DTX Width Register 1
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXLW : DTX Low WidthDTX0 pin low level width
bits : 0 - 5 (6 bit)
access : read-write
DALI Transmit Data Register 1H
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTDR : Upper 16-bit DALI transmit data
bits : 0 - 14 (15 bit)
access : read-write
DALI Bit Timing Violation Threshold Register 2
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTV3 : Bit Timing Violation Threshold 3Specifies the bit timing violation threshold value 3.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
bits : 0 - 6 (7 bit)
access : read-write
BTV4 : Bit Timing Violation Threshold 4Specifies the bit timing violation threshold value 4.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
bits : 8 - 14 (7 bit)
access : read-write
DALI Transmit Data Register 1L
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTDR : Lower 16-bit DALI transmit data
bits : 0 - 14 (15 bit)
access : read-write
DALI Transmit Control Register 1
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
alternate_register : SPDR
reset_Mask : 0x0
TRST : Transmission Start Trigger
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Transmission Start
End of enumeration elements list.
DALI Control Register 1
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TE : Transmit Enabling
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmit operation is disabled.
#1 : 1
Transmit operation is enabled.
End of enumeration elements list.
RE : Receive Enabling
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Storing received data is disabled.
#1 : 1
Storing received data is enabled.
End of enumeration elements list.
SDIE : DALI_SDI Output Enabling
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
DALI_SDI output is disabled.
#1 : 1
DALI_SDI output is enabled.
End of enumeration elements list.
DEIE : DALI_DEI Output Enabling
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
DALI_DEI output is disabled.
#1 : 1
DALI_DEI output is enabled.
End of enumeration elements list.
CLIE : DALI_CLI Output Enabling
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
DALI_CLI output is disabled.
#1 : 1
DALI_CLI output is enabled.
End of enumeration elements list.
BPIE : DALI_BPI Output Enabling
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
DALI_BPI output is disabled.
#1 : 1
DALI_BPI output is enabled.
End of enumeration elements list.
FEIE : DALI_FEI Output Enabling
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
DALI_FEI output is disabled.
#1 : 1
DALI_FEI output is enabled.
End of enumeration elements list.
DALI DTX Control Register 1
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXAS : DTX Assert LevelNote 1. The bit must be modified only when the DALI0.CTR1.TE bit is 0.
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The DTX0 pin is driven low.
#1 : 1
The DTX0 pin is driven high.
End of enumeration elements list.
TXASE : DTX Assert EnablingNote 1. The bit must be modified only when the DALI0.CTR1.TE bit is 0.
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
An internal transmit data is output to the DTX0 pin.
#1 : 1
The level specified by TXAS bit is output to the DTX0 pin.
End of enumeration elements list.
DALI Reception Data Register 1H
address_offset : 0x2E Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DRDR : Upper 16-bit of DALI receive data
bits : 0 - 14 (15 bit)
access : read-only
DALI Reception Data Register 1L
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DRDR : Lower 16-bit of DALI receive data
bits : 0 - 14 (15 bit)
access : read-only
DALI Status Register 1
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFEF : Manchester Flaming Error Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No MFE occurred or 1 was written to the DALI0.FECR1.MFEFC bit.
#1 : 1
An MFE occurred.
End of enumeration elements list.
OVF : Overrun Error Flag
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : 0
No overrun error occurred or 1 was written to the DALI0.FECR1.OVFC bit.
#1 : 1
An overrun error occurred.
End of enumeration elements list.
BTVF : Bit Timing Violation Flag
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : 0
No bit timing violation occurred or 1 was written to the DALI0.FECR1.BTVFC bit.
#1 : 1
Bit timing violation occurred
End of enumeration elements list.
RDRF : Receive Data Register Full Flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : 0
The DALI0.RDR1L register was read or 1 was written to the DALI0.FECR1.RDRFC.
#1 : 1
Receive data is stored in the DALI0.RDR1L or DALI0.RDR1H register.
End of enumeration elements list.
TENDF : Transmit End Flag
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
1 was written to the DALI0.FECR1.TENDFC bit.
#1 : 1
Frame transmission has been completed.
End of enumeration elements list.
BBF : Bus BUSY Flag
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : 0
DALI bus is IDLE
#1 : 1
DALI bus is BUSY
End of enumeration elements list.
BPDF : Bus Power Down Flag
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : 0
No effected
#1 : 1
Bus power down detected
End of enumeration elements list.
O32F : Over 32-Bit Data Reception Flag
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : 0
Receive data is 32 bits or less, or 1 was written to the DALI0.FECR1.O32FC bit.
#1 : 1
Receive data is 33 bits or more.
End of enumeration elements list.
CDF : Collision Detect Flag
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : 0
No collision occurred or 1 was written to the DALI0.FECR1.CDFC bit.
#1 : 1
A collision occurred.
End of enumeration elements list.
DAF : Destroy Area Flag
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : 0
The collision did not occur in the destroy area or 1 was written to the DALI0.FECR1.DAFC bit.
#1 : 1
The collision occurred in the destroy area.
End of enumeration elements list.
RDBL : Receive Data Bit LengthThese bits store the bit length for data received successfully
bits : 10 - 14 (5 bit)
access : read-only
DALI Collision Register 1
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CFTF2 : Collision Detect Timing Flag 2
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
#0000 : 0000
After reset is released
#0001 : 0001
Collision detection timing 1
#0010 : 0010
Collision detection timing 2
#0011 : 0011
Collision detection timing 3
#0100 : 0100
Collision detection timing 4
#0101 : 0101
Collision detection timing 5
#0110 : 0110
Collision detection timing 6
#0111 : 0111
Collision detection timing 7 *1
#1000 : 1000
Collision detection timing 8 *1
#1001 : 1001
Collision detection timing 9 *1
#1010 : 1010
Collision detection timing 10 *1
: others
Setting prohibited
End of enumeration elements list.
CDTF1 : Collision Detect Timing Flag 1
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : 0
Collision detection started at the edge on a bit period boundary.
#1 : 1
Collision detection started at the edge in the middle of a bit period.
End of enumeration elements list.
CLDAF : Collision Last Destroy Area Flag
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
#0 : 0
Collision detected is caused by a DRX0 edge occurrence.
#1 : 1
Collision detected is not caused by a DRX0 edge occurrence. (Last destroy area)
End of enumeration elements list.
RXDMON : DRX MonitorThis bit monitors the DRX0 pin value after the DRX0 pin is synchronized
bits : 11 - 10 (0 bit)
access : read-only
RXDCEG : DRX Collision Edge
bits : 12 - 11 (0 bit)
access : read-only
Enumeration:
#0 : 0
Falling edge
#1 : 1
Rising edge
End of enumeration elements list.
TXDCV : DTX Collision Value
bits : 13 - 12 (0 bit)
access : read-only
Enumeration:
#0 : 0
Low
#1 : 1
High
End of enumeration elements list.
DALI Flag Error Clear Register 1
address_offset : 0x3A Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MFEFC : Manchester Flaming Error Flag Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : 0
DALI0.STR1.MFEF bit is not cleared.
#1 : 1
DALI0.STR1.MFEF bit is cleared
End of enumeration elements list.
OVFC : Overrun Error Flag Clear
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : 0
DALI0.STR1.OVF bit is not cleared.
#1 : 1
DALI0.STR1.OVF bit is cleared
End of enumeration elements list.
BTVFC : Bit Timing Violation Flag Clear
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : 0
DALI0.STR1.BTVF bit is not cleared.
#1 : 1
DALI0.STR1.BTVF bit is cleared.
End of enumeration elements list.
RDRFC : Receive Data Register Full Flag Clear
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : 0
DALI0.STR1.RDRF bit is not cleared.
#1 : 1
DALI0.STR1.RDRF bit is cleared.
End of enumeration elements list.
TENDFC : Transmit End Flag Clear
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
#0 : 0
DALI0.STR1.TENDF bit is not cleared.
#1 : 1
DALI0.STR1.TENDF bit is cleared
End of enumeration elements list.
BBFC : Bus BUSY Flag ClearNote1: Do not clear DALI0.STR1.BBF bit when DALI0.CTR1.TE bit or DALI0.CTR1.RE bit is 1.
bits : 5 - 4 (0 bit)
access : write-only
Enumeration:
#0 : 0
DALI0.STR1.BBF bit is not cleared.
#1 : 1
DALI0.STR1.BBF bit is cleared
End of enumeration elements list.
BPDFC : Bus Power Down Flag Clear
bits : 6 - 5 (0 bit)
access : write-only
Enumeration:
#0 : 0
DALI0.STR1.BPDF bit is not cleared.
#1 : 1
DALI0.STR1.BPDF bit is cleared.
End of enumeration elements list.
O32FC : Over 32-Bit Data Reception Flag Clear
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : 0
DALI0.STR1.O32F bit is not cleared.
#1 : 1
DALI0.STR1.O32F bit is cleared
End of enumeration elements list.
CDFC : Collision Detect Flag Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : 0
DALI0.STR1.CDF bit is not cleared.
#1 : 1
DALI0.STR1.CDF bit is cleared.
End of enumeration elements list.
DAFC : Destroy Area Flag Clear
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : 0
DALI0.STR1.DAF bit is not cleared.
#1 : 1
DALI0.STR1.DAF bit is cleared.
End of enumeration elements list.
DALI Software Reset Register 1
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWR : Software ResetWriting 1 to this bit causes a software reset.
bits : 0 - -1 (0 bit)
access : write-only
DALI Bit Timing Violation Threshold Register 3
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTV5 : Bit Timing Violation Threshold 5Specifies the bit timing violation threshold value 5.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
bits : 0 - 6 (7 bit)
access : read-write
DALI Bit Timing Violation Threshold Register 4
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTV6 : Bit Timing Violation Threshold 6Specifies the bit timing violation threshold value 6.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
bits : 0 - 7 (8 bit)
access : read-write
DALI Collision Threshold Register 1
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COL1 : Collision Threshold 1Specifies the collision threshold value 1.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
bits : 0 - 4 (5 bit)
access : read-write
COL2 : Collision Threshold 2Specifies the collision threshold value 2.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
bits : 8 - 12 (5 bit)
access : read-write
DALI Collision Threshold Register 2
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COL3 : Collision Threshold 3Specifies the collision threshold value 3.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
bits : 0 - 5 (6 bit)
access : read-write
COL4 : Collision Threshold 4Specifies the collision threshold value 4.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
bits : 8 - 13 (6 bit)
access : read-write
DALI Collision Threshold Register 3
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COL5 : Collision Threshold 5Specifies the collision threshold value 5.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
bits : 0 - 5 (6 bit)
access : read-write
COL6 : Collision Threshold 6Specifies the collision threshold value 6.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
bits : 8 - 13 (6 bit)
access : read-write
DALI Collision Threshold Register 4
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COL7 : Collision Threshold 7Specifies the collision threshold value 7.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
bits : 0 - 6 (7 bit)
access : read-write
COL8 : Collision Threshold 8Specifies the collision threshold value 8.Note 1. These bits must be modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE bit is 0.
bits : 8 - 14 (7 bit)
access : read-write
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