\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
Debug Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CDBGPWRUPREQ : Debug power-up request
bits : 28 - 27 (0 bit)
access : read-only
Enumeration:
#0 : 0
0: OCD is not requesting debug power up
#1 : 1
0: OCD is requesting debug power up
End of enumeration elements list.
CDBGPWRUPACK : Debug power-up acknowledge
bits : 29 - 28 (0 bit)
Enumeration:
#0 : 0
Debug power-up request is not acknowledged
#1 : 1
Debug power-up request is acknowledged
End of enumeration elements list.
Debug Stop Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGSTOP_IWDT : Mask bit for IWDT reset/interrupt
bits : 0 - -1 (0 bit)
DBGSTOP_WDT : Mask bit for WDT reset/interrupt
bits : 1 - 0 (0 bit)
DBGSTOP_LVD0 : Mask bit for LVD reset/interupt
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Enable reset/interupt on corresponding LVD
#1 : 1
Mask reset/interupt on corresponding LVD
End of enumeration elements list.
DBGSTOP_LVD1 : Mask bit for LVD reset/interupt
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Enable reset/interupt on corresponding LVD
#1 : 1
Mask reset/interupt on corresponding LVD
End of enumeration elements list.
DBGSTOP_LVD2 : Mask bit for LVD reset/interupt
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Enable reset/interupt on corresponding LVD
#1 : 1
Mask reset/interupt on corresponding LVD
End of enumeration elements list.
DBGSTOP_RPER : Mask bit for SRAM parity error
bits : 24 - 23 (0 bit)
DBGSTOP_RECCR : Mask bit for SRAM ECC error
bits : 25 - 24 (0 bit)
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