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R_DRW

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x64 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x74 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x90 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xB4 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xDC Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CONTROL

STATUS

L1START

L2START

L3START

L4START

L5START

L6START

L1XADD

L2XADD

L3XADD

L4XADD

L5XADD

L6XADD

CONTROL2

HWREVISION

L1YADD

L2YADD

L3YADD

L4YADD

L5YADD

L6YADD

L1BAND

L2BAND

COLOR1

COLOR2

PATTERN

SIZE

PITCH

ORIGIN

LUSTART

LUXADD

LUYADD

LVSTARTI

LVSTARTF

LVXADDI

LVYADDI

LVYXADDF

TEXPITCH

TEXMASK

TEXORIGIN

IRQCTL

CACHECTL

DLISTSTART

PERFCOUNT1

PERFCOUNT2

PERFTRIGGER

TEXCLADDR

TEXCLDATA

TEXCLOFFSET

COLKEY


CONTROL

Geometry Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CONTROL CONTROL write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIM1ENABLE LIM2ENABLE LIM3ENABLE LIM4ENABLE LIM5ENABLE LIM6ENABLE QUAD1ENABLE QUAD2ENABLE QUAD3ENABLE LIM1THRESHOLD LIM2THRESHOLD LIM3THRESHOLD LIM4THRESHOLD LIM5THRESHOLD LIM6THRESHOLD BAND1ENABLE BAND2ENABLE UNION12 UNION34 UNION56 UNIONAB UNIONCD SPANABORT SPANSTORE

LIM1ENABLE : Enable limiter 1
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.

LIM2ENABLE : Enable limiter 2
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.

LIM3ENABLE : Enable limiter 3
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.

LIM4ENABLE : Enable limiter 4
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.

LIM5ENABLE : Enable limiter 5
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.

LIM6ENABLE : Enable limiter 6
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.

QUAD1ENABLE : Enable quadratic coupling of limiters 1 and 2
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.

QUAD2ENABLE : Enable quadratic coupling of limiters 3 and 4
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.

QUAD3ENABLE : Enable quadratic coupling of limiters 5 and 6
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.

LIM1THRESHOLD : Enable limiter 1 threshold mode
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.

LIM2THRESHOLD : Enable limiter 2 threshold mode
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.

LIM3THRESHOLD : Enable limiter 3 threshold mode
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.

LIM4THRESHOLD : Enable limiter 4 threshold mode
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.

LIM5THRESHOLD : Enable limiter 5 threshold mode
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.

LIM6THRESHOLD : Enable limiter 6 threshold mode
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.

BAND1ENABLE : Enable band postprocess for limiter 1 (see L1BAND)
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.

BAND2ENABLE : Enable band postprocess for limiter 1 (see L1BAND)
bits : 16 - 15 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.

UNION12 : Combine limter 1 and 2 as union (output is called A)
bits : 17 - 16 (0 bit)
access : write-only

Enumeration:

#0 : 0

minimum/intersect

#1 : 1

maximum/union

End of enumeration elements list.

UNION34 : Combine limter 3 and 4 as union (output is called B)
bits : 18 - 17 (0 bit)
access : write-only

Enumeration:

#0 : 0

minimum/intersect

#1 : 1

maximum/union

End of enumeration elements list.

UNION56 : Combine limter 5 and 6 as union (output is called D)
bits : 19 - 18 (0 bit)
access : write-only

Enumeration:

#0 : 0

minimum/intersect

#1 : 1

maximum/union

End of enumeration elements list.

UNIONAB : Combine outputs A and B as union (output is called C)
bits : 20 - 19 (0 bit)
access : write-only

Enumeration:

#0 : 0

minimum/intersect

#1 : 1

maximum/union

End of enumeration elements list.

UNIONCD : Combine outputs C and D as union (output is final)
bits : 21 - 20 (0 bit)
access : write-only

Enumeration:

#0 : 0

minimum/intersect

#1 : 1

maximum/union

End of enumeration elements list.

SPANABORT : Shape is horizontally convex, only a single span per scanline
bits : 22 - 21 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.

SPANSTORE : Nextline span start is always equal or left to current-line span start
bits : 23 - 22 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.


STATUS

Status Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : CONTROL
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSYENUM BUSYWRITE CACHEDIRTY DLISTACTIVE ENUMIRQ DLISTIRQ BUSIRQ BUSERRMFB BUSERRMTXMRL BUSERRMDL

BUSYENUM : Enumeration unit status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : 0

enumeration unit idle

#1 : 1

enumeration unit busy, new primitive can not be started

End of enumeration elements list.

BUSYWRITE : Framebuffer writeback status
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : 0

framebuffer writeback finished

#1 : 1

framebuffer writeback busy, framebuffer type can not be changed

End of enumeration elements list.

CACHEDIRTY : Framebuffer cache status
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : 0

framebuffer cache is not dirty

#1 : 1

framebuffer cache is dirty, frame should not be flipped

End of enumeration elements list.

DLISTACTIVE : Display list reader status
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : 0

display list reader is idle

#1 : 1

display list reader busy, no direct write access to registers allowed

End of enumeration elements list.

ENUMIRQ : enumeration finished interrupt triggered
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : 0

enumeration not finished or interrupt disabled

#1 : 1

enumeration finished interrupt triggered

End of enumeration elements list.

DLISTIRQ : display list finished interrupt triggered
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : 0

display list not finished or interrupt disabled

#1 : 1

display list finished interrupt triggered

End of enumeration elements list.

BUSIRQ : bus error interrupt triggered
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : 0

no bus error occurred or interrupt disabled

#1 : 1

bus error interrupt triggered

End of enumeration elements list.

BUSERRMFB : framebuffer bus error interrupt triggered
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : 0

no framebuffer bus error occured or interrupt disabled

#1 : 1

framebuffer bus error interrupt triggered

End of enumeration elements list.

BUSERRMTXMRL : texture bus error interrupt triggered
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

#0 : 0

no texture bus error occurred or interrupt disabled

#1 : 1

texture bus error interrupt triggered

End of enumeration elements list.

BUSERRMDL : display list bus error interrupt triggered
bits : 10 - 9 (0 bit)
access : read-only

Enumeration:

#0 : 0

no display list bus error occurred or interrupt disabled

#1 : 1

display list bus error interrupt triggered

End of enumeration elements list.


L1START

Limiter %s Start Value Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L1START L1START write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSTART

LSTART : Start value of the n'th limiter(n=1-6)
bits : 0 - 30 (31 bit)
access : write-only


L2START

Limiter %s Start Value Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L2START L2START write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSTART

LSTART : Start value of the n'th limiter(n=1-6)
bits : 0 - 30 (31 bit)
access : write-only


L3START

Limiter %s Start Value Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L3START L3START write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSTART

LSTART : Start value of the n'th limiter(n=1-6)
bits : 0 - 30 (31 bit)
access : write-only


L4START

Limiter %s Start Value Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L4START L4START write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSTART

LSTART : Start value of the n'th limiter(n=1-6)
bits : 0 - 30 (31 bit)
access : write-only


L5START

Limiter %s Start Value Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L5START L5START write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSTART

LSTART : Start value of the n'th limiter(n=1-6)
bits : 0 - 30 (31 bit)
access : write-only


L6START

Limiter %s Start Value Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L6START L6START write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSTART

LSTART : Start value of the n'th limiter(n=1-6)
bits : 0 - 30 (31 bit)
access : write-only


L1XADD

Limiter %s X-Axis Increment Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L1XADD L1XADD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LXADD

LXADD : X-axis increment
bits : 0 - 30 (31 bit)
access : write-only


L2XADD

Limiter %s X-Axis Increment Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L2XADD L2XADD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LXADD

LXADD : X-axis increment
bits : 0 - 30 (31 bit)
access : write-only


L3XADD

Limiter %s X-Axis Increment Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L3XADD L3XADD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LXADD

LXADD : X-axis increment
bits : 0 - 30 (31 bit)
access : write-only


L4XADD

Limiter %s X-Axis Increment Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L4XADD L4XADD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LXADD

LXADD : X-axis increment
bits : 0 - 30 (31 bit)
access : write-only


L5XADD

Limiter %s X-Axis Increment Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L5XADD L5XADD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LXADD

LXADD : X-axis increment
bits : 0 - 30 (31 bit)
access : write-only


L6XADD

Limiter %s X-Axis Increment Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L6XADD L6XADD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LXADD

LXADD : X-axis increment
bits : 0 - 30 (31 bit)
access : write-only


CONTROL2

Surface Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CONTROL2 CONTROL2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PATTERNENABLE TEXTUREENABLE PATTERNSOURCEL5 USEACB READFORMAT32 BSFA BDFA WRITEFORMAT2 BSF BDF BSI BDI BC2 TEXTURECLAMPX TEXTURECLAMPY TEXTUREFILTERX TEXTUREFILTERY READFORMAT10 WRITEFORMAT10 WRITEALPHA RLEENABLE CLUTENABLE COLKEYENABLE CLUTFORMAT BSIA BDIA RLEPIXELWIDTH

PATTERNENABLE : Pixel source is a pattern color (blend of COLOR1 and COLOR2 depending on PATTERN and pattern index)
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled pattern

#1 : 1

enabled pattern

End of enumeration elements list.

TEXTUREENABLE : Pixel source is read from texture and used as an alpha to blend between COLOR1 and COLOR2
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : 0

disabled texture

#1 : 1

enabled texture

End of enumeration elements list.

PATTERNSOURCEL5 : Limiter 5 is used as pattern index instead of the default U limiter.Limiter 5 can be combined with limiter 6 to form a quadratic limiter which can be used to make quadratic pattern functions to draw radial patterns.
bits : 2 - 1 (0 bit)
access : write-only

USEACB : Alpha blend mode
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : 0

use WRITEALPHA[1:0] mode

#1 : 1

use full alpha channel blending mode

End of enumeration elements list.

READFORMAT32 : Bit 4 and 3 of the texture buffer format.See READFORMAT above for description
bits : 4 - 4 (1 bit)
access : write-only

BSFA : Blend source factor for alpha channel in alpha channel blending mode (USEACB = 1)
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

#0 : 0

use 1.0 as blend source factor for alpha channel

#1 : 1

use alpha as blend source factor for alpha channel

End of enumeration elements list.

BDFA : Blend destinetion factor for alpha channel in alpha channel blending mode (USEACB = 1)
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : 0

use 1.0 as blend destination factor for alpha channel

#1 : 1

use alpha as blend destination factor for alpha channel

End of enumeration elements list.

WRITEFORMAT2 : Bit 3 of framebuffer pixel formatSee WRITEFORMAT above description.
bits : 8 - 7 (0 bit)
access : write-only

BSF : Blend source factorsrc factor is alpha (factor is 1 per default)
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : 0

use 1.0 as blend source factor

#1 : 1

use alpha as blend source factor

End of enumeration elements list.

BDF : Blend destination factordst factor is alpha (factor is 1 per default)
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : 0

use 1.0 as blend destination factor

#1 : 1

use alpha as blend destination factor

End of enumeration elements list.

BSI : Blend source factor is invertedsrc factor will be inverted (meaning 1-a or 1-1 depending on BSF)
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : 0

use blend factor as specified through BSF

#1 : 1

invert blend source factor (1-x)

End of enumeration elements list.

BDI : Blend destination factor is inverteddst factor will be inverted (meaning 1-a or 1-1 depending on BDF)
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

#0 : 0

use blend factor as specified through BDF

#1 : 1

invert blend destinationfactor (1-x)

End of enumeration elements list.

BC2 : Blend color 2 instead of framebuffer pixel
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : 0

use pixel from framebuffer as destination (DST)

#1 : 1

use color 2 as destination (DST)

End of enumeration elements list.

TEXTURECLAMPX : Calculating U limiter outside use textureThe bit describes what happens if the U limiter (x direction in texture space) calculates a U value outside of the used texture
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

#0 : 0

Texture wrap mode: The integer part of the calculated value from the u limiter is anded with TEXUMASK. This results in a repetition of the texture in x/u direction.

#1 : 1

Texture clamp mode: The texture color at the border of the texture is taken. This results in a repetition of the texture border color in x/u direction.

End of enumeration elements list.

TEXTURECLAMPY : Calculating V limiter outside use textureThe bit describes what happens if the V limiter (y direction in texture space) calculates a V value outside of the used texture
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

#0 : 0

Texture wrap mode: The integer part of the calculated value from the v limiter is anded with TEXVMASK. This results in a repetition of the texture in y/v direction.

#1 : 1

Texture clamp mode: The texture color at the border of the texture is taken. This results in a repetition of the texture border color in y/v direction.

End of enumeration elements list.

TEXTUREFILTERX : Linear filtering on texture U axis
bits : 16 - 15 (0 bit)
access : write-only

Enumeration:

#0 : 0

no filtering on texture U axis

#1 : 1

linear filtering on texture U axis

End of enumeration elements list.

TEXTUREFILTERY : Linear filtering on texture V axis
bits : 17 - 16 (0 bit)
access : write-only

Enumeration:

#0 : 0

no filtering on texture V axis

#1 : 1

linear filtering on texture V axis

End of enumeration elements list.

READFORMAT10 : Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000: 8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011: 16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44) 4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8), 8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4), 4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2), 2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1), 1 bit indexed color/luminance
bits : 18 - 18 (1 bit)
access : write-only

Enumeration:

#00 : 00

8 bpp a(8) (READFORMAT32=00) / 16 bpp aRGB(1555) (READFORMAT32=01) / 1 bpp CLUT(1)/I(1), 1 bit indexed color/luminance (READFORMAT32=11)

#01 : 01

16 bpp RGB(565) (READFORMAT32=00) / 8 bpp aCLUT(44) 4 bit alpha and 4 bit indexed color (READFORMAT32=01) / 8 bpp CLUT(8)/I(8), 8 bit indexed color/luminance (READFORMAT32=10)

#10 : 10

32 bpp aRGB(8888) (READFORMAT32=00) / 4 bpp CLUT(4)/I(4), 4 bit indexed color/luminance (READFORMAT32=10)

#11 : 11

16 bpp aRGB(4444) (READFORMAT32=00) / 2 bpp CLUT(2)/I(2), 2 bit indexed color/luminance (READFORMAT32=10)

End of enumeration elements list.

WRITEFORMAT10 : Pixel format of the framebuffer
bits : 20 - 20 (1 bit)
access : write-only

Enumeration:

#00 : 00

8bpp a(8)0

#01 : 01

16bpp RGB(565)

#10 : 10

32bpp aRGB(8888)

#11 : 11

16bpp aRGB(4444)

End of enumeration elements list.

WRITEALPHA : Writeback alpha source for framebufferSet the 'alpha source' for the framebuffer(USEACB = 0)Blend alpha in color 2 instead of framebuffer alpha((USEACB = 1))In not alpha channel blending mode (USEACB = 0):Set the 'alpha source' for the framebuffer.In alpha channel blending mode (USEACB = 1):Blend alpha in color 2 instead of framebuffer alpha00B: BC2A = 1: use alpha from framebuffer as destination (DST_A)else: BC2A = 0: use alpha in color 2 as destination (DST_A)
bits : 22 - 22 (1 bit)
access : write-only

Enumeration:

#00 : 00

use alpha from color 2

#01 : 01

use source alpha (pixel coverage)

#10 : 10

use 0.0 as alpha

#11 : 11

use alpha from framebuffer

End of enumeration elements list.

RLEENABLE : RLE enable
bits : 24 - 23 (0 bit)
access : write-only

Enumeration:

#0 : 0

RLE disabled

#1 : 1

RLE enabled

End of enumeration elements list.

CLUTENABLE : CLUT enable
bits : 25 - 24 (0 bit)
access : write-only

Enumeration:

#0 : 0

CLUT disabled

#1 : 1

CLUT enabled

End of enumeration elements list.

COLKEYENABLE : color keying enable
bits : 26 - 25 (0 bit)
access : write-only

Enumeration:

#0 : 0

color keying disabled

#1 : 1

color keying enabled

End of enumeration elements list.

CLUTFORMAT : Format of the CLUT
bits : 27 - 26 (0 bit)
access : write-only

Enumeration:

#0 : 0

aRGB(8888)

#1 : 1

RGB(565)

End of enumeration elements list.

BSIA : Blend source factor inverted in alpha channel (USEACB = 1)
bits : 28 - 27 (0 bit)
access : write-only

Enumeration:

#0 : 0

use blend factor as specified through BSFA

#1 : 1

invert blend source factor (1-x)

End of enumeration elements list.

BDIA : Blend destination factor inverted in alpha channel (USEACB = 1)
bits : 29 - 28 (0 bit)
access : write-only

Enumeration:

#0 : 0

use blend factor as specified through BDFA

#1 : 1

invert blend destination factor (1-x)

End of enumeration elements list.

RLEPIXELWIDTH : Texel width for RLE unit
bits : 30 - 30 (1 bit)
access : write-only

Enumeration:

#00 : 00

1 byte per texel

#01 : 01

2 byte per texel

#10 : 10

3 byte per texel

#11 : 11

4 byte per texel

End of enumeration elements list.


HWREVISION

Hardware Version and Feature Set ID Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : CONTROL2
reset_Mask : 0x0

HWREVISION HWREVISION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REV DLR FBCACHE TXCACHE PERFCOUNT TEXCLU RLEUNIT TEXCLUT256 COLORKEY ACBLEND

REV : Revision number
bits : 0 - 10 (11 bit)
access : read-only

DLR : Display list reader feature
bits : 17 - 16 (0 bit)
access : read-only

Enumeration:

#0 : 0

Display list reader unavailable

#1 : 1

Display list reader available

End of enumeration elements list.

FBCACHE : Framebuffer cache feature
bits : 18 - 17 (0 bit)
access : read-only

Enumeration:

#0 : 0

Framebuffer cache unavailable

#1 : 1

Framebuffer cache available

End of enumeration elements list.

TXCACHE : Texture cache feature
bits : 19 - 18 (0 bit)
access : read-only

Enumeration:

#0 : 0

Texture cache unavailable

#1 : 1

Texture cache available

End of enumeration elements list.

PERFCOUNT : Two performance counter feature
bits : 20 - 19 (0 bit)
access : read-only

Enumeration:

#0 : 0

Two performance counter unavailable

#1 : 1

Two performance counter available

End of enumeration elements list.

TEXCLU : Texture CLUT with 16 or 256 entries feature
bits : 21 - 20 (0 bit)
access : read-only

Enumeration:

#0 : 0

Texture CLUT with 16 or 256 entries unavailable

#1 : 1

Texture CLUT with 16 or 256 entries available

End of enumeration elements list.

RLEUNIT : RLE unit feature
bits : 23 - 22 (0 bit)
access : read-only

Enumeration:

#0 : 0

RLE unit unavailable

#1 : 1

RLE unit available

End of enumeration elements list.

TEXCLUT256 : Texture CLUT feature
bits : 24 - 23 (0 bit)
access : read-only

Enumeration:

#0 : 0

Texture CLUT unavailable

#1 : 1

Texture CLUT available

End of enumeration elements list.

COLORKEY : Colorkey feature
bits : 25 - 24 (0 bit)
access : read-only

Enumeration:

#0 : 0

Colorkey unavailable

#1 : 1

Colorkey available

End of enumeration elements list.

ACBLEND : Alpha channel blending feature
bits : 27 - 26 (0 bit)
access : read-only

Enumeration:

#0 : 0

Alpha channel blending unavailable

#1 : 1

Alpha channel blending available

End of enumeration elements list.


L1YADD

Limiter %s Y-Axis Increment Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L1YADD L1YADD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LYADD

LYADD : Y-axis increment
bits : 0 - 30 (31 bit)
access : write-only


L2YADD

Limiter %s Y-Axis Increment Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L2YADD L2YADD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LYADD

LYADD : Y-axis increment
bits : 0 - 30 (31 bit)
access : write-only


L3YADD

Limiter %s Y-Axis Increment Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L3YADD L3YADD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LYADD

LYADD : Y-axis increment
bits : 0 - 30 (31 bit)
access : write-only


L4YADD

Limiter %s Y-Axis Increment Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L4YADD L4YADD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LYADD

LYADD : Y-axis increment
bits : 0 - 30 (31 bit)
access : write-only


L5YADD

Limiter %s Y-Axis Increment Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L5YADD L5YADD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LYADD

LYADD : Y-axis increment
bits : 0 - 30 (31 bit)
access : write-only


L6YADD

Limiter %s Y-Axis Increment Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L6YADD L6YADD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LYADD

LYADD : Y-axis increment
bits : 0 - 30 (31 bit)
access : write-only


L1BAND

Limiter %s Band Width Parameter Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L1BAND L1BAND write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LBAND

LBAND : Limiter m band width parameter
bits : 0 - 30 (31 bit)
access : write-only


L2BAND

Limiter %s Band Width Parameter Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L2BAND L2BAND write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LBAND

LBAND : Limiter m band width parameter
bits : 0 - 30 (31 bit)
access : write-only


COLOR1

Base Color Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

COLOR1 COLOR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COLOR1B COLOR1G COLOR1R COLOR1A

COLOR1B : Blue channel of color 1
bits : 0 - 6 (7 bit)
access : write-only

COLOR1G : Green channel of color 1
bits : 8 - 14 (7 bit)
access : write-only

COLOR1R : Red channel of color 1
bits : 16 - 22 (7 bit)
access : write-only

COLOR1A : Alpha channel of color 1(0x00: transparent. . . 0xFF: opaque)
bits : 24 - 30 (7 bit)
access : write-only


COLOR2

Secondary Color Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

COLOR2 COLOR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COLOR2B COLOR2G COLOR2R COLOR2A

COLOR2B : Blue channel of color 2
bits : 0 - 6 (7 bit)
access : write-only

COLOR2G : Green channel of color 2
bits : 8 - 14 (7 bit)
access : write-only

COLOR2R : Red channel of color 2
bits : 16 - 22 (7 bit)
access : write-only

COLOR2A : Alpha channel of color 2(0x00: transparent. . . 0xFF: opaque)
bits : 24 - 30 (7 bit)
access : write-only


PATTERN

Pattern Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PATTERN PATTERN write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PATTERN

PATTERN : Bitmap of the pattern
bits : 0 - 6 (7 bit)
access : write-only


SIZE

Bounding Box Dimension Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SIZE SIZE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZEX SIZEY

SIZEX : Width of the bounding box in pixelsvalid range: 0 to 1024
bits : 0 - 14 (15 bit)
access : write-only

SIZEY : Height of the bounding box in pixelsvalid range: 0 to 1024
bits : 16 - 30 (15 bit)
access : write-only


PITCH

Framebuffer Pitch And Spanstore Delay Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PITCH PITCH write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PITCH SSD

PITCH : pitch of the framebuffer. A negative width can be used to render bottom-up instead of top-down
bits : 0 - 14 (15 bit)
access : write-only

SSD : Spanstore delay
bits : 16 - 30 (15 bit)
access : write-only


ORIGIN

Framebuffer Base Address Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ORIGIN ORIGIN write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ORIGIN

ORIGIN : Address of the first pixel in framebuffer
bits : 0 - 30 (31 bit)
access : write-only


LUSTART

U Limiter Start Value Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LUSTART LUSTART write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LUSTART

LUSTART : U limiter start value
bits : 0 - 30 (31 bit)
access : write-only


LUXADD

U Limiter X-Axis Increment Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LUXADD LUXADD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LUXADD

LUXADD : U limiter x-axis increment
bits : 0 - 30 (31 bit)
access : write-only


LUYADD

U Limiter Y-Axis Increment Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LUYADD LUYADD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LUYADD

LUYADD : U limiter y-axis increment
bits : 0 - 30 (31 bit)
access : write-only


LVSTARTI

V Limiter Start Value Integer Part Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LVSTARTI LVSTARTI write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVSTARTI

LVSTARTI : V limiter start value integer part
bits : 0 - 30 (31 bit)
access : write-only


LVSTARTF

V Limiter Start Value Fractional Part Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LVSTARTF LVSTARTF write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVSTARTF

LVSTARTF : V limiter start value fractional part
bits : 0 - 14 (15 bit)
access : write-only


LVXADDI

V Limiter X-Axis Increment Integer Part Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LVXADDI LVXADDI write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVXADDI

LVXADDI : V limiter x-axis increment integer part
bits : 0 - 30 (31 bit)
access : write-only


LVYADDI

V Limiter Y-Axis Increment Integer Part Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LVYADDI LVYADDI write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVYADDI

LVYADDI : V limiter y-axis increment integer part
bits : 0 - 30 (31 bit)
access : write-only


LVYXADDF

V Limiter Increment Fractional Parts Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LVYXADDF LVYXADDF write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVXADDF LVYADDF

LVXADDF : V xlimiter increment fractional part
bits : 0 - 14 (15 bit)
access : write-only

LVYADDF : V y limiter increment fractional part
bits : 16 - 30 (15 bit)
access : write-only


TEXPITCH

Texels Per Texture Line Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TEXPITCH TEXPITCH write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEXPITCH

TEXPITCH : Texels per texture linevalid range: 0 to 2048
bits : 0 - 30 (31 bit)
access : write-only


TEXMASK

Texture Size or Texture Address Mask Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TEXMASK TEXMASK write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEXUMASK TEXVMASK

TEXUMASK : U maskSet TEXUMASK[10:0] = texture_width -1In texture wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX = 1):all widths up to 2048 are allowed.
bits : 0 - 9 (10 bit)
access : write-only

TEXVMASK : V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY = 0): texture_height must be a power of 2In texture clamping mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024 are allowed.
bits : 11 - 30 (20 bit)
access : write-only


TEXORIGIN

Texture Base Address Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TEXORIGIN TEXORIGIN write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEXORIGIN

TEXORIGIN : Texture base address
bits : 0 - 30 (31 bit)
access : write-only


IRQCTL

Interrupt Control Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IRQCTL IRQCTL write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENUMIRQEN DLISTIRQEN ENUMIRQCLR DLISTIRQCLR BUSIRQEN BUSIRQCLR

ENUMIRQEN : ENUMIRQ interrupt mask enable
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : 0

disable (mask) ENUMIRQ

#1 : 1

enable (unmask) ENUMIRQ

End of enumeration elements list.

DLISTIRQEN : DLISTIRQ interrupt mask enable
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : 0

disable (mask) DLISTIRQ

#1 : 1

enable (unmask) DLISTIRQ

End of enumeration elements list.

ENUMIRQCLR : Clear enumeration interrupt ENUMIRQ
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : 0

no ENUMIRQCLR clear

#1 : 1

clear ENUMIRQCLR

End of enumeration elements list.

DLISTIRQCLR : Clear display list interrupt DLISTIRQ
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : 0

no DLISTRQCLR clear

#1 : 1

clear DLISTRQCLR

End of enumeration elements list.

BUSIRQEN : BUSIRQ interrupt mask enable
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : 0

disable (mask) BUSIRQ

#1 : 1

enable (unmask) BUSIRQ

End of enumeration elements list.

BUSIRQCLR : Clear bus error interrupt BUSIRQ
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

#0 : 0

no BUSIRQCLR clear

#1 : 1

clear BUSIRQCLR

End of enumeration elements list.


CACHECTL

Cache Control Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CACHECTL CACHECTL write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CENABLEFX CFLUSHFX CENABLETX CFLUSHTX

CENABLEFX : Framebuffer cache enable
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : 0

disable the framebuffer cache

#1 : 1

enable the framebuffer cache

End of enumeration elements list.

CFLUSHFX : Flush framebuffer cache
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : 0

do not flush the framebuffer cache

#1 : 1

flush the framebuffer cache

End of enumeration elements list.

CENABLETX : Texture cache enable
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : 0

disable the texture cache

#1 : 1

enable the texture cache

End of enumeration elements list.

CFLUSHTX : Flush texture cache
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : 0

do not flush the texture cache

#1 : 1

flush the texture cache

End of enumeration elements list.


DLISTSTART

Display List Start Address Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DLISTSTART DLISTSTART write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLISTSTART

DLISTSTART : Display list start address
bits : 0 - 30 (31 bit)
access : write-only


PERFCOUNT1

Performance Counter %s
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERFCOUNT1 PERFCOUNT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERFCOUNT

PERFCOUNT : Counter value.The counter is reset by writing PERFCOUNT = 0000 0000H.
bits : 0 - 30 (31 bit)
access : read-write


PERFCOUNT2

Performance Counter %s
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERFCOUNT2 PERFCOUNT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERFCOUNT

PERFCOUNT : Counter value.The counter is reset by writing PERFCOUNT = 0000 0000H.
bits : 0 - 30 (31 bit)
access : read-write


PERFTRIGGER

Performance Counters Control Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PERFTRIGGER PERFTRIGGER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERFTRIGGER1 PERFTRIGGER2

PERFTRIGGER1 : Selects the internal event that will increment PERFCOUNT1 register.
bits : 0 - 14 (15 bit)
access : write-only

Enumeration:

0x00 : 0x00

disable performance counter

0x01 : 0x01

2D Drawing Engine active cycles

0x02 : 0x02

framebuffer read access

0x03 : 0x03

framebuffer write access

0x04 : 0x04

texture read access

0x05 : 0x05

invisible pixels (enumerated but selected with alpha 0percent)

0x06 : 0x06

invisible pixels while internal FIFO is empty (lost cycles)

0x07 : 0x07

display list reader active cycles

0x08 : 0x08

framebuffer read hits

0x09 : 0x09

framebuffer read misses

0x0A : 0x0A

framebuffer write hits

0x0B : 0x0B

framebuffer write misses

0x0C : 0x0C

texture read hits

0x0D : 0x0D

texture read misses

0x1F : 0x1F

every clock cycle (for use as timer)

: others

Setting prohibited

End of enumeration elements list.

PERFTRIGGER2 : Selects the internal event that will increment PERFCOUNT2 register
bits : 16 - 30 (15 bit)
access : write-only

Enumeration:

0x00 : 0x00

disable performance counter

0x01 : 0x01

2D Drawing Engine active cycles

0x02 : 0x02

framebuffer read access

0x03 : 0x03

framebuffer write access

0x04 : 0x04

texture read access

0x05 : 0x05

invisible pixels (enumerated but selected with alpha 0percent)

0x06 : 0x06

invisible pixels while internal FIFO is empty (lost cycles)

0x07 : 0x07

display list reader active cycles

0x08 : 0x08

framebuffer read hits

0x09 : 0x09

framebuffer read misses

0x0A : 0x0A

framebuffer write hits

0x0B : 0x0B

framebuffer write misses

0x0C : 0x0C

texture read hits

0x0D : 0x0D

texture read misses

0x1F : 0x1F

every clock cycle (for use as timer)

: others

Setting prohibited

End of enumeration elements list.


TEXCLADDR

CLUT Start Address Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TEXCLADDR TEXCLADDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLADDR

CLADDR : Texture CLUT start address for indexed texture format
bits : 0 - 6 (7 bit)
access : write-only


TEXCLDATA

CLUT Data Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TEXCLDATA TEXCLDATA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLDATA

CLDATA : Texture CLUT data for Indexed texture format
bits : 0 - 30 (31 bit)
access : write-only


TEXCLOFFSET

CLUT Offset Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TEXCLOFFSET TEXCLOFFSET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLOFFSET

CLOFFSET : Texture CLUT offset for Indexed texture format. CLOFFSET[7:0] is or'ed with the original index
bits : 0 - 6 (7 bit)
access : write-only


COLKEY

Color Key Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

COLKEY COLKEY write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COLKEYB COLKEYG COLKEYR

COLKEYB : Blue channel of color key
bits : 0 - 6 (7 bit)
access : write-only

COLKEYG : Green channel of color key
bits : 8 - 14 (7 bit)
access : write-only

COLKEYR : Red channel of color key
bits : 16 - 22 (7 bit)
access : write-only



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