\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x60 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xE4 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
ETHERC Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRM : Promiscuous Mode
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Promiscuous mode is disabled.
#1 : 1
Promiscuous mode is enabled.
End of enumeration elements list.
DM : Duplex Mode
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Half-duplex mode
#1 : 1
Full-duplex mode
End of enumeration elements list.
RTM : Bit Rate
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
10 Mbps
#1 : 1
100 Mbps
End of enumeration elements list.
ILB : Internal Loopback Mode
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Normal data transmission or reception is performed.
#1 : 1
Data is looped back in the ETHERC when full-duplex mode is selected.
End of enumeration elements list.
TE : Transmission Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmit function is disabled.
#1 : 1
Transmit function is enabled.
End of enumeration elements list.
RE : Reception Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Receive function is disabled.
#1 : 1
Receive function is enabled.
End of enumeration elements list.
MPDE : Magic Packet Detection Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Magic Packet detection is disabled.
#1 : 1
Magic Packet detection is enabled.
End of enumeration elements list.
PRCEF : CRC Error Frame Receive Mode
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : 0
EDMAC is notified of a CRC error.
#1 : 1
EDMAC is not notified of a CRC error.
End of enumeration elements list.
TXF : Transmit Flow Control Operating Mode
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Automatic PAUSE frame transmission is disabled.(PAUSE frame is not automatically transmitted.)
#1 : 1
Automatic PAUSE frame transmission is enabled.(PAUSE frame is automatically transmitted as required.)
End of enumeration elements list.
RXF : Receive Flow Control Operating Mode
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
PAUSE frame detection is disabled.
#1 : 1
PAUSE frame detection is enabled.
End of enumeration elements list.
PFR : PAUSE Frame Receive Mode
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
PAUSE frame is not transferred to the EDMAC.
#1 : 1
PAUSE frame is transferred to the EDMAC.
End of enumeration elements list.
ZPF : 0 Time PAUSE Frame Enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
PAUSE frame that contains the pause_time parameter of 0 is not used.
#1 : 1
PAUSE frame that contains the pause_time parameter of 0 is used.
End of enumeration elements list.
TPC : PAUSE Frame Transmit
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
PAUSE frame is transmitted even during a PAUSE period.
#1 : 1
PAUSE frame is not transmitted during a PAUSE period.
End of enumeration elements list.
ETHERC Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICD : False Carrier Detect Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
PHY-LSI has not detected a false carrier on the line.
#1 : 1
PHY-LSI has detected a false carrier on the line.
End of enumeration elements list.
MPD : Magic Packet Detect Flag
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Magic Packet has not been detected.
#1 : 1
Magic Packet has been detected.
End of enumeration elements list.
LCHNG : LCHNG Link Signal Change Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Change in the ETn_LINKSTA signal has not been detected.
#1 : 1
Change in the ETn_LINKSTA signal has been detected (high to low, or low to high).
End of enumeration elements list.
PSRTO : PAUSE Frame Retransmit Over Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
PAUSE frame retransmit count has not reached the upper limit.
#1 : 1
PAUSE frame retransmit count has reached the upper limit.
End of enumeration elements list.
BFR : Continuous Broadcast Frame Reception Flag
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Continuous reception of broadcast frames has not been detected.
#1 : 1
Continuous reception of broadcast frames has been detected.
End of enumeration elements list.
ETHERC Interrupt Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICDIP : False Carrier Detect Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Notification of the false carrier detect interrupt is disabled.
#1 : 1
Notification of the false carrier detect interrupt is enabled.
End of enumeration elements list.
MPDIP : Magic Packet Detect Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Notification of the Magic Packet detect interrupt is disabled.
#1 : 1
Notification of the Magic Packet detect interrupt is enabled.
End of enumeration elements list.
LCHNGIP : LINK Signal Change Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Notification of ETn_LINKSTA signal change interrupt is disabled.
#1 : 1
Notification of ETn_LINKSTA signal change interrupt is enabled.
End of enumeration elements list.
PSRTOIP : PAUSE Frame Retransmit Over Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Notification of PAUSE frame retransmit over interrupt is disabled.
#1 : 1
Notification of PAUSE frame retransmit over interrupt is enabled.
End of enumeration elements list.
BFSIPR : Continuous Broadcast Frame Reception Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : 0
Notification of continuous broadcast frame reception interrupt is disabled.
#1 : 1
Notification of continuous broadcast frame reception interrupt is enabled.
End of enumeration elements list.
PHY Interface Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDC : MII/RMII Management Data ClockThe MDC bit value is output from the ETn_MDC pin to supply the management data clock to the MII or RMII.
bits : 0 - -1 (0 bit)
access : read-write
MMD : MII/RMII Management Mode
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Read
#1 : 1
Write
End of enumeration elements list.
MDO : MII/RMII Management Data-OutThe MDO bit value is output from the ETn_MDIO pin when the MMD bit is 1 (write). The value is not output when the MMD bit is 0 (read).
bits : 2 - 1 (0 bit)
access : read-write
MDI : MII/RMII Management Data-InThis bit indicates the level of the ETn_MDIO pin. The write value should be 0.
bits : 3 - 2 (0 bit)
access : read-only
PHY Status Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LMON : ETn_LINKSTA Pin Status FlagThe link status can be read by connecting the link signal output from the PHY-LSI to the ETn_LINKSTA pin. For details on the polarity, refer to the specifications of the connected PHY-LSI.
bits : 0 - -1 (0 bit)
access : read-only
Random Number Generation Counter Upper Limit Setting Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RMD : Random Number Generation Counter
bits : 0 - 18 (19 bit)
access : read-write
Enumeration:
0x00000 : 00000h
Normal operation
: others
Setting prohibited
End of enumeration elements list.
IPG Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPG : Interpacket Gap Range: 16bit time(0x00) - 140bit time(0x1F)
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x14 : 14h
96 bit time (initial value)
: others
(IPGx4+16) bit time
End of enumeration elements list.
Automatic PAUSE Frame Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AP : Automatic PAUSE Time SettingThese bits set the value of the pause_time parameter for a PAUSE frame that is automatically transmitted. Transmission is not performed until the set value multiplied by 512 bit time has elapsed.
bits : 0 - 14 (15 bit)
access : read-write
Manual PAUSE Frame Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MP : Manual PAUSE Time SettingThese bits set the value of the pause_time parameter for a PAUSE frame that is manually transmitted. Transmission is not performed until the set value multiplied by 512 bit time has elapsed. The read value is undefined.
bits : 0 - 14 (15 bit)
access : write-only
Received PAUSE Frame Counter
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RPAUSE : Received PAUSE Frame CountNumber of received PAUSE frames
bits : 0 - 6 (7 bit)
access : read-only
PAUSE Frame Retransmit Count Setting Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPAUSE : Automatic PAUSE Frame Retransmit Setting
bits : 0 - 14 (15 bit)
access : read-write
Enumeration:
0x0000 : 0x0000
Number of retransmissions is unlimited
: others
Maximum number of retransmissions is (TPAUSE)
End of enumeration elements list.
PAUSE Frame Retransmit Counter
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Broadcast Frame Receive Count Setting Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCF : Broadcast Frame Continuous Receive Count Setting
bits : 0 - 14 (15 bit)
access : read-write
Enumeration:
0x0000 : 0000h
Number of receptions is unlimited.
: others
Receive (BFC) frame.
End of enumeration elements list.
Receive Frame Maximum Length Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFL : Receive Frame Maximum LengthThe set value becomes the maximum frame length. The minimum value that can be set is 1,518 bytes, and the maximum value that can be set is 2,048 bytes. Values that are less than 1,518 bytes are regarded as 1,518 bytes, and values larger than 2,048 bytes are regarded as 2,048 bytes.
bits : 0 - 10 (11 bit)
access : read-write
MAC Address Upper Bit Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAHR : MAC Address Upper Bit RegisterThe MAHR register sets the upper 32 bits (b47 to b16) of the 48-bit MAC address.
bits : 0 - 30 (31 bit)
access : read-write
MAC Address Lower Bit Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MALR : MAC Address Lower Bit RegisterThe MALR register sets the lower 16 bits of the 48-bit MAC address.
bits : 0 - 14 (15 bit)
access : read-write
Transmit Retry Over Counter Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TROCR : Transmit Retry Over Counter RegisterThe TROCR register is a counter indicating the number of frames that fail to be retransmitted.
bits : 0 - 30 (31 bit)
access : read-write
Late Collision Detect Counter Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Lost Carrier Counter Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCCR : Lost Carrier Counter RegisterThe LCCR register is a counter indicating the number of times a loss of carrier is detected during frame transmission.
bits : 0 - 30 (31 bit)
access : read-write
Carrier Not Detect Counter Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNDCR : Carrier Not Detect Counter RegisterThe CNDCR register is a counter indicating the number of times a carrier is not detected during preamble transmission.
bits : 0 - 30 (31 bit)
access : read-write
CRC Error Frame Receive Counter Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEFCR : CRC Error Frame Receive Counter RegisterThe CEFCR register is a counter indicating the number of received frames where a CRC error has been detected.
bits : 0 - 30 (31 bit)
access : read-write
Frame Receive Error Counter Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRECR : Frame Receive Error Counter RegisterThe FRECR register is a counter indicating the number of times a frame receive error has occurred.
bits : 0 - 30 (31 bit)
access : read-write
Too-Short Frame Receive Counter Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSFRCR : Too-Short Frame Receive Counter RegisterThe TSFRCR register is a counter indicating the number of times a short frame that is shorter than 64 bytes has been received.
bits : 0 - 30 (31 bit)
access : read-write
Too-Long Frame Receive Counter Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLFRCR : Too-Long Frame Receive Counter RegisterThe TLFRCR register is a counter indicating the number of times a long frame that is longer than the RFLR register value has been received.
bits : 0 - 30 (31 bit)
access : read-write
Received Alignment Error Frame Counter Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFCR : Received Alignment Error Frame Counter RegisterThe RFCR register is a counter indicating the number of times a frame has been received with the alignment error (frame is not an integral number of octets).
bits : 0 - 30 (31 bit)
access : read-write
Multicast Address Frame Receive Counter Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAFCR : Multicast Address Frame Receive Counter RegisterThe MAFCR register is a counter indicating the number of times a frame where the multicast address is set has been received.
bits : 0 - 30 (31 bit)
access : read-write
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