Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x48 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x38 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x58 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD4 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x78 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x64 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC8 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
EDMAC Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWR : Software Reset
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : 0
no effect.
#1 : 1
the corresponding channels of the EDMAC and ETHERC are reset. Registers TDLAR, RDLAR, RMFCR, TFUCR, and RFOCR are not reset.
End of enumeration elements list.
DL : Transmit/Receive DescriptorLength
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : 00
16 bytes
#01 : 01
32 bytes
#10 : 10
64 bytes
#11 : 11
16 bytes
End of enumeration elements list.
DE : Big Endian Mode/Little Endian ModeNOTE: This setting applies to data for the transmit/receive buffer. It does not apply to transmit/receive descriptors and registers.
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : 0
Big endian mode
#1 : 1
Little endian mode
End of enumeration elements list.
EDMAC Receive Request Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RR : Receive Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Receive function is disabled.
#1 : 1
Receive descriptor is read, and the receive function is enabled.
End of enumeration elements list.
Transmit Descriptor List Start Address Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDLAR : The start address of the transmit descriptor list is set. Set the start address according to the descriptor length selected by the EDMR.DL[1:0] bits.16-byte boundary: Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte boundary: Lower 6 bits = 000000b
bits : 0 - 30 (31 bit)
access : read-write
Receive Descriptor List Start Address Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDLAR : The start address of the receive descriptor list is set. Set the start address according to the descriptor length selected by the EDMR.DL[1:0] bits.16-byte boundary: Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte boundary: Lower 6 bits = 000000b
bits : 0 - 30 (31 bit)
access : read-write
ETHERC/EDMAC Status Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CERF : CRC Error Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
CRC error has not been detected.
#1 : 1
CRC error has been detected.
End of enumeration elements list.
PRE : PHY-LSI Receive Error Flag
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
PHY-LSI receive error has not been detected.
#1 : 1
PHY-LSI receive error has been detected.
End of enumeration elements list.
RTSF : Frame-Too-Short Error Flag
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Frame-too-short error has not been detected.
#1 : 1
Frame-too-short error has been detected.
End of enumeration elements list.
RTLF : Frame-Too-Long Error Flag
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Frame-too-long error has not been detected.
#1 : 1
Frame-too-long error has been detected.
End of enumeration elements list.
RRF : Alignment Error Flag
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Alignment error has not been detected.
#1 : 1
Alignment error has been detected.
End of enumeration elements list.
RMAF : Multicast Address Frame Receive Flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Multicast address frame has not been received.
#1 : 1
Multicast address frame has been received.
End of enumeration elements list.
TRO : Transmit Retry Over Flag
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmit retry-over condition has not been detected.
#1 : 1
Transmit retry-over condition has been detected.
End of enumeration elements list.
CD : Late Collision Detect Flag
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Late collision has not been detected.
#1 : 1
Late collision has been detected during frame transmission.
End of enumeration elements list.
DLC : Loss of Carrier Detect Flag
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Loss of carrier has not been detected.
#1 : 1
Loss of carrier has been detected during frame transmission.
End of enumeration elements list.
CND : Carrier Not Detect Flag
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
A carrier has been detected when transmission starts.
#1 : 1
A carrier has not been detected during preamble transmission.
End of enumeration elements list.
RFOF : Receive FIFO Overflow Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Overflow has not occurred.
#1 : 1
Overflow has occurred.
End of enumeration elements list.
RDE : Receive Descriptor Empty Flag
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
The EDMAC detects that the receive descriptor valid bit (RDn.RACT) is 1.
#1 : 1
The EDMAC detects that the receive descriptor valid bit (RDn.RACT) is 0.
End of enumeration elements list.
FR : Frame Receive Flag
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Frame has not been received.
#1 : 1
Frame has been received. Update of the receive descriptor is complete.
End of enumeration elements list.
TFUF : Transmit FIFO Underflow Flag
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Underflow has not occurred.
#1 : 1
Underflow has occurred.
End of enumeration elements list.
TDE : Transmit Descriptor Empty Flag
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
The EDMAC detects that the transmit descriptor valid bit (TDn.TACT) is 1.
#1 : 1
The EDMAC detects that the transmit descriptor valid bit (TDn.TACT) is 0.
End of enumeration elements list.
TC : Frame Transfer Complete Flag
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transfer have not been completed, or no transfer has been requested.
#1 : 1
All frames indicated by the transmit descriptor have been completely transferred to the transmit FIFO.
End of enumeration elements list.
ECI : ETHERC Status Register Source FlagNOTE: When the source in the ETHERCn.ECSR register is cleared, the ECI flag is also cleared.
bits : 22 - 21 (0 bit)
access : read-only
Enumeration:
#0 : 0
ETHERC status interrupt source has not been detected.
#1 : 1
ETHERC status interrupt source has been detected.
End of enumeration elements list.
ADE : Address Error Flag
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Invalid memory address has not been detected (normal operation).
#1 : 1
Invalid memory address has been detected.
End of enumeration elements list.
RFCOF : Receive Frame Counter Overflow Flag
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
Receive frame counter has not overflowed.
#1 : 1
Receive frame counter has overflowed.
End of enumeration elements list.
RABT : Receive Abort Detect Flag
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : 0
Frame reception has not been aborted or no reception has been requested.
#1 : 1
Frame reception has been aborted.
End of enumeration elements list.
TABT : Transmit Abort Detect Flag
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : 0
Frame transmission has not been aborted or no transmission has been requested.
#1 : 1
Frame transmission has been aborted.
End of enumeration elements list.
TWB : Write-Back Complete Flag
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write-back has not been completed, or no transmission has been requested.
#1 : 1
Write-back to the transmit descriptor has been completed.
End of enumeration elements list.
ETHERC/EDMAC Status Interrupt Enable Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CERFIP : CRC Error Interrupt Request Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
CRC error interrupt request is disabled.
#1 : 1
CRC error interrupt request is enabled.
End of enumeration elements list.
PREIP : PHY-LSI Receive Error Interrupt Request Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
PHY-LSI receive error interrupt request is disabled.
#1 : 1
PHY-LSI receive error interrupt request is enabled.
End of enumeration elements list.
RTSFIP : Frame-Too-Short Error Interrupt Request Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Frame-too-short error interrupt request is disabled.
#1 : 1
Frame-too-short error interrupt request is enabled.
End of enumeration elements list.
RTLFIP : Frame-Too-Long Error Interrupt Request Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Frame-too-long error interrupt request is disabled.
#1 : 1
Frame-too-long error interrupt request is enabled.
End of enumeration elements list.
RRFIP : Alignment Error Interrupt Request Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Alignment error interrupt request is disabled.
#1 : 1
Alignment error interrupt request is enabled.
End of enumeration elements list.
RMAFIP : Multicast Address Frame Receive Interrupt Request Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
Multicast address frame receive interrupt request is disabled.
#1 : 1
Multicast address frame receive interrupt request is enabled.
End of enumeration elements list.
TROIP : Transmit Retry Over Interrupt Request Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmit retry over interrupt request is disabled.
#1 : 1
Transmit retry over interrupt request is enabled.
End of enumeration elements list.
CDIP : Late Collision Detect Interrupt Request Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : 0
Late collision detect interrupt request is disabled.
#1 : 1
Late collision detect interrupt request is enabled.
End of enumeration elements list.
DLCIP : Loss of Carrier Detect Interrupt Request Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : 0
Loss of carrier detect interrupt request is disabled.
#1 : 1
Loss of carrier detect interrupt request is enabled.
End of enumeration elements list.
CNDIP : Carrier Not Detect Interrupt Request Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : 0
Carrier not detect interrupt request is disabled.
#1 : 1
Carrier not detect interrupt request is enabled.
End of enumeration elements list.
RFOFIP : Receive FIFO Overflow Interrupt Request Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : 0
Overflow interrupt request is disabled.
#1 : 1
Overflow interrupt request is enabled.
End of enumeration elements list.
RDEIP : Receive Descriptor Empty Interrupt Request Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : 0
Receive descriptor empty interrupt request is disabled.
#1 : 1
Receive descriptor empty interrupt request is enabled.
End of enumeration elements list.
FRIP : Frame Receive Interrupt Request Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : 0
Frame reception interrupt request is disabled.
#1 : 1
Frame reception interrupt request is enabled.
End of enumeration elements list.
TFUFIP : Transmit FIFO Underflow Interrupt Request Enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : 0
Underflow interrupt request is disabled.
#1 : 1
Underflow interrupt request is enabled.
End of enumeration elements list.
TDEIP : Transmit Descriptor Empty Interrupt Request Enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmit descriptor empty interrupt request is disabled.
#1 : 1
Transmit descriptor empty interrupt request is enabled.
End of enumeration elements list.
TCIP : Frame Transfer Complete Interrupt Request Enable
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : 0
Frame transmission complete interrupt request is disabled.
#1 : 1
Frame transmission complete interrupt request is enabled.
End of enumeration elements list.
ECIIP : ETHERC Status Register Source Interrupt Request Enable
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : 0
ETHERC status interrupt request is disabled.
#1 : 1
ETHERC status interrupt request is enabled.
End of enumeration elements list.
ADEIP : Address Error Interrupt Request Enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : 0
Address error interrupt request is disabled.
#1 : 1
Address error interrupt request is enabled.
End of enumeration elements list.
RFCOFIP : Receive Frame Counter Overflow Interrupt Request Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : 0
Receive frame counter overflow interrupt request is disabled.
#1 : 1
Receive frame counter overflow interrupt request is enabled.
End of enumeration elements list.
RABTIP : Receive Abort Detect Interrupt Request Enable
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : 0
Receive abort detect interrupt request is disabled.
#1 : 1
Receive abort detect interrupt request is enabled.
End of enumeration elements list.
TABTIP : Transmit Abort Detect Interrupt Request Enable
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmit abort detect interrupt request is disabled.
#1 : 1
Transmit abort detect interrupt request is enabled.
End of enumeration elements list.
TWBIP : Write-Back Complete Interrupt Request Enable
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : 0
Write-back complete interrupt request is disabled.
#1 : 1
Write-back complete interrupt request is enabled.
End of enumeration elements list.
ETHERC/EDMAC Transmit/Receive Status Copy Enable Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RRFCE : RRF Flag Copy Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
The EDMACn.EESR.RRF flag status is reflected in the RDn.RFE bit of the receive descriptor.
#1 : 1
The EDMACn.EESR.RRF flag status is not reflected in the RDn.RFE bit of the receive descriptor.
End of enumeration elements list.
RMAFCE : RMAF Flag Copy Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : 0
The EDMACn.EESR.RMAF flag status is reflected in the RDn.RFE bit of the receive descriptor.
#1 : 1
The EDMACn.EESR.RMAF flag status is not reflected in the RDn.RFE bit of the receive descriptor.
End of enumeration elements list.
Missed-Frame Counter Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFC : Missed-Frame CounterThese bits indicate the number of frames that are discarded and not transferred to the receive buffer during reception.
bits : 0 - 14 (15 bit)
access : read-write
Transmit FIFO Threshold Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFT : Transmit FIFO Threshold00Dh to 200h: The threshold is the set value multiplied by 4. Example: 00Dh: 52 bytes 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes
bits : 0 - 9 (10 bit)
access : read-write
Enumeration:
0x000 : 0x000
Store and forward mode
: others
The threshold is the set value multiplied by 4. (001h to 00Ch and 201h to 7FFh: Setting prohibited)
End of enumeration elements list.
Transmit FIFO Threshold Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFD : Transmit FIFO Depth
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#00111 : 00111
2048 bytes
: others
Settings other than above are prohibited.
End of enumeration elements list.
TFD : Receive FIFO Depth
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#01111 : 01111
4096 bytes
: others
Settings other than above are prohibited.
End of enumeration elements list.
Receive Method Control Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RNR : Receive Request Reset
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
EDRRR.RR bit (receive request bit) is set to 0 when one frame has been received.
#1 : 1
EDRRR.RR bit (receive request bit) is not set to 0 when one frame has been received.
End of enumeration elements list.
Transmit FIFO Underflow Counter
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UNDER : Transmit FIFO Underflow CountThese bits indicate how many times the transmit FIFO has underflowed. The counter stops when the counter value reaches FFFFh.
bits : 0 - 14 (15 bit)
access : read-write
Receive FIFO Overflow Counter
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVER : Receive FIFO Overflow CountThese bits indicate how many times the receive FIFO has overflowed. The counter stops when the counter value reaches FFFFh.
bits : 0 - 14 (15 bit)
access : read-write
Independent Output Signal Setting Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ELB : External Loopback Mode
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
The ETn_EXOUT pin outputs low.
#1 : 1
The ETn_EXOUT pin outputs high.
End of enumeration elements list.
Flow Control Start FIFO Threshold Setting Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFDO : Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 bytes of data is stored in the receive FIFO.)
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : 000
When 224 ( 256 - 32) bytes of data is stored in the receive FIFO.
#001 : 001
When 480 ( 512 - 32) bytes of data is stored in the receive FIFO.
#010 : 010
When 736 ( 768 - 32) bytes of data is stored in the receive FIFO.
#011 : 011
When 992 (1024 - 32) bytes of data is stored in the receive FIFO.
#100 : 100
When 1248 (1280 - 32) bytes of data is stored in the receive FIFO.
#101 : 101
When 1504 (1536 - 32) bytes of data is stored in the receive FIFO.
#110 : 110
When 1760 (1792 - 32) bytes of data is stored in the receive FIFO.
#111 : 111
When 2016 (2048 - 32) bytes of data is stored in the receive FIFO.
End of enumeration elements list.
RFFO : Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) receive frames have been stored in the receive FIFO.)
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#000 : 000
When 2 receive frames have been stored in the receive FIFO.
#001 : 001
When 4 receive frames have been stored in the receive FIFO.
#010 : 010
When 6 receive frames have been stored in the receive FIFO.
#011 : 011
When 8 receive frames have been stored in the receive FIFO.
#100 : 100
When 10 receive frames have been stored in the receive FIFO.
#101 : 101
When 12 receive frames have been stored in the receive FIFO.
#110 : 110
When 14 receive frames have been stored in the receive FIFO.
#111 : 111
When 16 receive frames have been stored in the receive FIFO.
End of enumeration elements list.
Receive Data Padding Insert Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PADR : Padding Slot
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0x00 : 00h
Padding is inserted at the head of received data.
: others
Padding is inserted between the (PADR)th byte and (PADR+1)th byte of received data.
End of enumeration elements list.
PADS : Padding Size
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#00 : 00
No padding is inserted.
#01 : 01
1 byte is inserted.
#10 : 10
2 bytes are inserted.
#11 : 11
3 bytes are inserted.
End of enumeration elements list.
Transmit Interrupt Setting Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIS : Transmit Interrupt EnableSet the EESR.TWB flag to 1 in the mode selected by the TIM bit to notify an interrupt.
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmit Interrupt is disabled.
#1 : 1
Transmit Interrupt is enabled.
End of enumeration elements list.
TIM : Transmit Interrupt Mode
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Transmission complete interrupt mode: An interrupt occurs when a frame has been transmitted.
#1 : 1
Write-back complete interrupt mode: An interrupt occurs when write-back to the transmit descriptor has been completed.
End of enumeration elements list.
EDMAC Transmit Request Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TR : Transmit Request
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : 0
no effect.
#1 : 1
When 1 is written, the EDMAC reads the corresponding descriptor and transmits frames where the TD0.TACT bit is 1. The TR bit becomes 0 after all the valid frames are transmitted.
End of enumeration elements list.
Receive Buffer Write Address Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBWAR : Receive Buffer Write Address RegisterThe RBWAR register indicates the last address that the EDMAC has written data to when writing to the receive buffer.Refer to the address indicated by the RBWAR register to recognize which address in the receive buffer the EDMAC is writing data to. Note that the address that the EDMAC is outputting to the receive buffer may not match the read value of the RBWAR register during data reception.
bits : 0 - 30 (31 bit)
access : read-only
Receive Descriptor Fetch Address Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDFAR : Receive Descriptor Fetch Address RegisterThe RDFAR register indicates the start address of the last fetched receive descriptor when the EDMAC fetches descriptor information from the receive descriptor.Refer to the address indicated by the RDFAR register to recognize which receive descriptor information the EDMAC is using for the current processing. Note that the address of the receive descriptor that the EDMAC fetches may not match the read value of the RDFAR register during data reception.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Buffer Read Address Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBRAR : Transmit Buffer Read Address RegisterThe TBRAR register indicates the last address that the EDMAC has read data from when reading data from the transmit buffer.Refer to the address indicated by the TBRAR register to recognize which address in the transmit buffer the EDMAC is reading from. Note that the address that the EDMAC is outputting to the transmit buffer may not match the read value of the TBRAR register.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Descriptor Fetch Address Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TDFAR : Transmit Descriptor Fetch Address RegisterThe TDFAR register indicates the start address of the last fetched transmit descriptor when the EDMAC fetches descriptor information from the transmit descriptor.Refer to the address indicated by the TDFAR register to recognize which transmit descriptor information the EDMAC is using for the current processing. Note that the address of the transmit descriptor that the EDMAC fetches may not match the read value of the TDFAR register.
bits : 0 - 30 (31 bit)
access : read-only
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